KR20010067447A - Semiconductor device having a low k material within a shallow trench isolation and a method of manufacture - Google Patents

Abstract

PURPOSE: To provide a semiconductor deice possessed of an original insulation structure. CONSTITUTION: A semiconductor device (100) may include a substrate (110) where an insulation opening 210 is provided, a dielectric layer (310) of silicon oxide or the like formed inside the insulation opening (210), and a material (410) which is low in dielectric properties (K) and formed on the dielectric layer (310) and inside the insulation opening (210) to form an insulation structure (510) of the semiconductor device (100). The relative permittivity of material low in dielectric properties may be lower than that of a dielectric layer. Spin-on- glass material, carbonate, silk or other materials of low K can be used as the above material of low K.

Description

TECHNICAL FIELD OF THE INVENTION A semiconductor device having a low temperature material in a shallow trench isolation and a manufacturing method.

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, in particular semiconductor devices having low K materials deposited in shallow trench isolation structures, and methods of manufacturing the devices.

Integrated circuits are now well known and widely used in various technical fields. In recent decades, device speeds have been dramatically reduced while operating speeds and packing densities have increased substantially. The combination of increased integration density and reduced device size has raised new challenges that have not previously been of concern to the semiconductor manufacturing industry. One of them involves forming an isolation structure between transistor devices located on the same semiconductor wafer substrate to provide electrical isolation between the devices. In general, various techniques of the term isolation process have been developed to isolate devices in integrated circuits.

One of them is local oxidation of silicon (LOCOS), in which silicon nitride (Si ₃ N ₄ ) films are used to isolate selected areas of the semiconductor substrate on which field oxide structures are formed. This isolation technology has been widely used as isolation technology for Very Large-Scale Integrated (VLSI) circuits. Although this technique is very useful and widely used for larger submicron devices, smaller current submicron techniques have faced geographical limitations due to increased integration density.

To overcome the limitations associated with LOCOS processes, an optional isolation process, known as shallow trench isolation (STI), has been devised in the semiconductor manufacturing industry. This particular process provides an isolation structure that requires less surface portion on the semiconductor substrate. However, even this process has faced limitations in increased integration density.

One of them relates to maintaining or increasing a threshold voltage while simultaneously reducing capacitance. As is well known, maintaining a high threshold voltage of the isolation material associated with a transistor device to minimize the formation of spurious conductive channels (i.e. current leakage) between transistor devices, which can cause device malfunction. Very preferred. In fact, it is even more desirable to increase the threshold voltage of the isolation structure to ensure that no such current leakage occurs.

In order to maintain the threshold voltage of the isolation structure at a desired level, considering the increased integration density, it is necessary to increase the depth of the structure while maintaining the current width. Alternatively, you can maintain the current depth and increase the width. However, all of these options are undesirable for different reasons. Increasing the depth is undesirable because it can increase the aspect ratio of the resulting feature and cause gaps in the structure. This gap is due to the difficulty of completely filling the structure with silicon dioxide. Increasing the width is likewise undesirable because larger widths occupy more surface area and reduce transistor integration density.

Capacitance is also a major concern for isolation structures. An isolation structure with low coupling capacitance is highly desirable to minimize parasitic capacitance without adversely affecting the switching speed of the transistor. As noted above, it is highly desirable to maintain the threshold voltage of the isolation structure in order to minimize current leakage and also to increase the threshold voltage of the isolation structure in light of the increased performance requirements. Unfortunately, increasing the threshold voltage causes a corresponding increase in capacitance. Thus, in the state of the art, not only is it difficult to achieve the desired threshold voltage for the reasons described above, but even if the desired threshold voltage is achieved, this may undesirably increase the capacitance of the isolation structure.

Thus, there is a need in the field of semiconductor manufacturing for isolation structures that avoid the disadvantages associated with prior art structures and processes and processes for forming such isolation structures.

In order to address the above-mentioned drawbacks of the prior art, the present invention provides a semiconductor device having a unique isolation structure. In a preferred embodiment, a semiconductor device comprises a substrate having an isolation opening formed in the substrate, a dielectric layer such as silicon dioxide formed in the isolation opening, and in and on the isolation opening to form an isolation structure in the semiconductor device. Low dielectric (K) material formed. In a preferred embodiment, the low K material has a dielectric constant less than the dielectric constant of the dielectric layer. The low K material may be a spin on glass material, black diamond, silk, or other similar low K material.

Thus, the present invention provides a unique isolation structure formed from low K material that provides a desired level of threshold voltage at low capacitance over a large area and with minimal current leakage and parasitic capacitance.

1 is a cross-sectional view of a semiconductor device according to the present invention in an intermediate manufacturing step,

2 is a cross-sectional view of the semiconductor device of FIG. 1 followed by formation of an isolation opening;

3 is a cross-sectional view of the semiconductor device of FIG. 2 followed by the formation of a dielectric layer in the isolation opening;

4 is a cross-sectional view of the semiconductor device of FIG. 3 followed by the formation of a low K dielectric material in an isolation opening;

5 is a cross-sectional view of the semiconductor device of FIG. 4 followed by a planarization process;

6 is a sectional view of a transistor structure formed between isolation structures.

The depth of the isolation opening may vary depending on the design, process and quality parameters. However, in one advantageous embodiment, the isolation openings have a depth of approximately 300 nm. The width may also vary but a width in the range of approximately 0.2 μm to 0.4 μm is preferred. In another aspect of the invention, the isolation structure has a threshold voltage of approximately 26V. However, the threshold voltage can also vary depending on the design parameters. As discussed briefly above, capacitance is an important factor in the isolation structure. In the isolation structure provided by the present invention, capacitance is equally important. It is desirable for the capacitance to be as low as possible and to have a high switching speed. Thus, in one specific embodiment, the isolation structure has a capacitance of approximately 4.87 nF / cm ² . This capacitance can be higher or lower depending on the design parameters.

Both the thickness of the dielectric layer and the low K material can vary depending on the selected depth of the isolation openings described above. However, in a preferred embodiment of the present invention the thickness of the dielectric layer is approximately 20 nm, and in another embodiment the thickness of the low K material is approximately 280 nm.

In another aspect of the invention, the semiconductor device also includes a transistor structure formed between a pair of isolation structures. Transistors, which may be CMOS devices, may include conventional features such as gate regions formed in the tub regions, and source / drain regions. Inherent isolation structures provide electrical isolation between transistor structures formed and coupled on both sides of the transistor structure. In one preferred embodiment, the isolation structure is formed in an epitaxial layer that has been conventionally formed on a semiconductor wafer.

In yet another embodiment, the present invention provides a method of manufacturing a semiconductor device having the isolation structure described above. In this particular aspect of the invention, the method comprises forming an isolation opening in a substrate of a semiconductor device, forming a dielectric layer in the isolation opening, and also in the isolation opening and on the dielectric layer to form an isolation structure in the semiconductor device. Forming a low dielectric (K) material.

The preferred and other features of the present invention have been described somewhat broadly so that those skilled in the art will better understand the construction of the invention that follows. Additional features of the invention, which form the subject of the claims of the invention, will be described below. Those skilled in the art should understand that the disclosed concepts and specific embodiments of the present invention can be readily used as a basis for designing and modifying other structures for carrying out the same purposes as the present invention. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present invention.

Referring first to FIG. 1, there is shown a cross-sectional view of a semiconductor device 100 in accordance with the present invention at an intermediate stage of manufacture. The semiconductor device 100 is formed on a conventional semiconductor substrate 110. An epitaxial layer 120 that is typically formed is located on the semiconductor substrate 110. Of course, epitaxial layer 120 may be doped with different dopants depending on the desired transistor design. While this particular embodiment includes epitaxial layer 120, it should be understood that other embodiments may not include epitaxial layer 120. A pad oxide layer 130 and a nitride layer 140 that are typically formed are located on the epitaxial layer 120. Pad oxide layer 130 and nitride layer 140 serve as etching masks to improve the isolation process described below. Also shown is a photoresist layer 150 that is typically formed and developed. Part of the photoresist layer 150 was removed to form an etch guide opening 160 where an isolation opening would later be formed.

Referring to FIG. 2, a cross-sectional view of the semiconductor device 100 of FIG. 1 is followed by the formation of the isolation opening 210. Isolation openings 210 are formed by conventional etching techniques. As shown, the isolation opening 210 is formed into the tub region of the epitaxial layer 120. However, due to the advantages associated with the present invention, it should be noted that the size of the isolation opening 210 need not be increased to obtain the high threshold voltages required by the isolation structure of the prior art. In fact, the width of the isolation opening 210 can still be much smaller now without deepening the isolation opening, thereby avoiding the problems associated with conventional isolation processes. Although the width of the isolation opening 210 can be made smaller, the threshold voltage can still be the same or increased because of the advantages provided by the present invention. For example, in one embodiment the width of the isolation opening 210 may range from approximately 0.2 μm to 0.4 μm and the depth may be approximately 300 nm.

3 is a cross-sectional view of the semiconductor device 100 of FIG. 2 followed by the formation of a dielectric layer 310 in the isolation opening 210. Dielectric layer 310 is preferably silicon dioxide having a high dielectric constant of approximately 4.4. Dielectric layer 310 provides stress relief for the material to be deposited and filled later, which again minimizes current leakage.

Referring to FIG. 4, a cross-sectional view of the semiconductor device 100 of FIG. 3 is shown followed by the formation of a low K dielectric material 410 in the isolation opening 210. For the purposes of the present invention, low K is defined as any dielectric constant of less than approximately 4.4. However, it is more preferred that the low K dielectric material 410 has a dielectric constant of approximately 2.1. The low K dielectric material 410 may be a spin on glass material. However, in other embodiments black diamond, silk or other similar materials having a low K may also be used. In one embodiment, the low K material has a thickness of 280 nm. The use of low K materials in isolation openings 210 instead of high K materials such as silicon dioxide has shown unexpectedly improved results.

Referring briefly to FIG. 5, there is shown a cross-sectional view of the semiconductor device 100 of FIG. 4 followed by a planarization process. Following deposition of the low K material 410, the semiconductor device is planarized by a conventional chemical / mechanical process, with the isolation structure 510 eventually completed as shown in FIG.

Following the planarization process, transistor structure 600 as shown in FIG. 6 is formed by a conventional process. Transistor structure 600 is preferably a metal oxide semiconductor (MOS), or more preferably a complementary metal oxide semiconductor (CMOS). In an exemplary embodiment, transistor structure 600 includes a gate 620 formed over gate oxide 630 in contact with source and drain regions 640. Isolation structure 510 isolates transistor structure 600 from the coupled transistor structure that makes up the MOS device. For example, if the MOS device is a CMOS device, transistor structure 600 is p-type while coupled transistor structure is n-type, thereby forming an npn CMOS device. Alternatively, however, transistor structure 600 is n-type while coupled transistor structure is p-type, thus forming a pnp CMOS device. For subsequent illustration, FIG. 6 also shows a dielectric layer 650 having contact openings 660 formed in dielectric layer 650. Those skilled in the art will understand how to complete a MOS device.

In one embodiment provided by the present invention, isolation structure 510 is formed having a width of approximately 0.4 μm and a depth of approximately 300 nm. A 20 nm layer of silicon dioxide is typically deposited in isolation opening 210, followed by deposition of spin on glass material having a low K of approximately 2.1. Testing of the threshold voltage and capacitance was performed on the conventional isolation structure and the present isolation structure 510 having dimensions equivalent to the present isolation structure 510, which is made of silicon dioxide, a high K dielectric material. Filled up. The threshold voltage of the conventional isolation structure is 15V, while the isolation structure 510 provided by the present invention exhibits a threshold voltage improvement of approximately 76% at approximately 26V. Capacitance is also measured. The conventional isolation structure has a coupling capacitance of 8.63 nF / cm ² , while the isolation structure 510 provided by the present invention has a capacitance of approximately 4.87 nF / cm ² , resulting in approximately 56% coupling capacitance. Indicates an improvement. From the above-mentioned comparison, it is clear that the isolation structure 510 provided by the present invention shows better and unexpected results than the conventional isolation structure.

It is also clear from the foregoing that the present invention provides a semiconductor device having a low combined capacitance of high threshold voltage, minimum current leakage and minimum parasitic capacitance without increasing the depth or width of the isolation structure.

Although the present invention has been described in detail, those skilled in the art should understand that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

The present invention provides a semiconductor device and a fabrication method having a unique isolation structure to provide improved results in threshold voltage and coupling impedance compared to the prior art.

Claims (28)

In a semiconductor device, The substrate having an isolation opening formed in the substrate, A dielectric layer formed in said isolation opening, A low dielectric (K) material formed in the isolation opening and on the dielectric layer to form an isolation structure in the semiconductor device Semiconductor device. The method of claim 1, The low K material has a dielectric constant less than the dielectric constant of the dielectric layer. Semiconductor device. The method of claim 1, And the dielectric layer comprises silicon dioxide. The method of claim 1, And the low K material comprises a spin on glass material. The method of claim 1, And the low K material is black diamond or silk. The method of claim 1, And the isolation opening is approximately 300 nm deep. The method of claim 1, And the isolation opening has a width in a range of approximately 0.2 μm to 0.4 μm. The method of claim 1, And the isolation structure has a threshold voltage of approximately 26V. The method of claim 1, The isolation structure has a capacitance of approximately 4.87 nF / cm ² . The method of claim 1, And the thickness of the semiconductor layer is approximately 20 nm. The method of claim 1, And wherein said low K material is approximately 280 nm thick. The method of claim 1, Further comprising a transistor structure formed between a pair of said isolation structures Semiconductor device. The method of claim 12, And the transistor structure forms a transistor of a CMOS device. The method of claim 1, And the substrate is an epitaxial layer formed on the semiconductor wafer. In the method of manufacturing a semiconductor device, Forming an isolation opening in a substrate of the semiconductor device; Forming a dielectric layer in the isolation opening; Forming a low dielectric (K) material in the isolation opening and on the dielectric layer to form an isolation structure in the semiconductor device. Semiconductor device manufacturing method. The method of claim 15, Forming the low K dielectric material comprises forming a low K dielectric material having a dielectric constant less than the dielectric constant of the dielectric layer. The method of claim 15, Forming the dielectric layer comprises forming a silicon dioxide layer. The method of claim 15, Forming the low K material comprises forming a spin on glass material. The method of claim 15, Forming the low K material comprises forming black diamond or silk. The method of claim 15, Forming an isolation opening comprises forming the isolation opening to a depth of approximately 300 nm. The method of claim 15, Forming the isolation opening comprises forming the isolation opening in a width in the range of approximately 0.2 μm to 0.4 μm. The method of claim 15, Forming an isolation structure comprises forming the isolation structure having a threshold voltage of approximately 26V. The method of claim 15, Forming an isolation structure comprises forming the isolation structure having a capacitance of approximately 4.87 nF / cm ² . The method of claim 15, Forming the dielectric layer comprises forming the dielectric layer to a thickness of approximately 20 nm. The method of claim 15, Forming the low dielectric material comprises forming the low dielectric material to a thickness of approximately 280 nm. The method of claim 15, Forming a transistor structure between the pair of isolation structures. The method of claim 26, Forming the transistor structure forms a transistor of a CMOS device. The method of claim 15, Forming a substrate includes forming an epitaxial layer on the semiconductor wafer.