KR20010066142A - a inductor of integrated circuit - Google Patents
a inductor of integrated circuit Download PDFInfo
- Publication number
- KR20010066142A KR20010066142A KR1019990067727A KR19990067727A KR20010066142A KR 20010066142 A KR20010066142 A KR 20010066142A KR 1019990067727 A KR1019990067727 A KR 1019990067727A KR 19990067727 A KR19990067727 A KR 19990067727A KR 20010066142 A KR20010066142 A KR 20010066142A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- inductor
- wiring layers
- via hole
- lower wiring
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 150000001875 compounds Chemical class 0.000 claims description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 44
- 239000011229 interlayer Substances 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/20—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명에서는 반도체 소자를 포함하는 반도체 기판 위에 제1 내지 제7 하부 배선층이 형성되어 있고, 그 위에 층간 절연막이 하부 배선층을 덮고 있다. 층간 절연막에는 제1 내지 제7 하부 배선층의 양끝을 각각 드러내는 비아 홀이 형성되어 있으며 비아 홀은 각각 금속막으로 채워져 있다. 층간 절연막 상부에는 제1 내지 제8 상부 배선층이 형성되어 있는데, 상부 배선층은 하부 배선층과 일정한 각을 가지고 틀어져 있다. 여기서, 제1 상부 배선층은 제1 하부 배선층의 제1 비아 홀과 이어지고, 제2 상부 배선층은 제1 하부 배선층의 제2 비아 홀 및 제2 하부 배선층의 제1 비아 홀과 이어지며, 제3 상부 배선층은 제2 하부 배선층의 제2 비아 홀 및 제3 하부 배선층의 제1 비아 홀과 이어진다. 이와 같이 이어진 배선층은 코일 형태를 이루어 인덕터를 형성한다. 따라서, 집적 회로의 시정수를 제어하며 공진 주파수를 형성하여 소비 전력을 최소화할 수 있다.In the present invention, the first to seventh lower wiring layers are formed on the semiconductor substrate including the semiconductor elements, and the interlayer insulating film covers the lower wiring layers thereon. Via holes are formed in the interlayer insulating layer to expose both ends of the first to seventh lower wiring layers, and the via holes are respectively filled with metal films. First to eighth upper wiring layers are formed on the interlayer insulating film, and the upper wiring layers are twisted at a predetermined angle with the lower wiring layers. The first upper interconnection layer may be connected to the first via hole of the first lower interconnection layer, and the second upper interconnection layer may be connected to the second via hole of the first lower interconnection layer and the first via hole of the second lower interconnection layer. The wiring layer is connected to the second via hole of the second lower wiring layer and the first via hole of the third lower wiring layer. The wiring layer thus continued forms a coil to form an inductor. Accordingly, power consumption may be minimized by controlling the time constant of the integrated circuit and forming a resonance frequency.
Description
본 발명은 집적 회로의 인덕터에 관한 것이다.The present invention relates to an inductor of an integrated circuit.
집적 회로(integrate circuit)는 디지털용, 아날로그용으로 나누어질 수 있는데, 디지털 회로는 온(on)-오프(off) 상태로만 신호를 전달하는 것이며, 아날로그 회로는 연속된 신호를 처리하는 것이다.Integrated circuits can be divided into digital and analogue circuits, where digital circuits carry signals only in an on-off state, and analog circuits process continuous signals.
이러한 회로는 저항(R : resistance), 인덕턴스(L : inductance), 정전 용량(C : capacitance)의 세 가지 기본 요소들이 서로 조합되어 이루어진다.This circuit is made up of three basic elements combined: resistance (R), inductance (L), and capacitance (C).
교류 전원이 회로에 인가될 때 전압(V : voltage)과 전류(I : current)는 시간(t : time)에 대한 함수로 나타나며, L과 C의 주파수(혹은 각속도 ω=2πf)에 대한 전류-전압 특성 곡선을 그리면 L 회로의 전압은 전류보다 위상이 90도 앞서고 C회로의 전압은 전류보다 위상이 90도 뒤에 온다.When AC power is applied to the circuit, the voltage (V) and current (I: current) are represented as a function of time (t: time) and are currents for the frequencies of L and C (or angular velocity ω = 2π f ). If we plot the voltage characteristic curve, the voltage in the L circuit is 90 degrees out of phase with the current, and the voltage in the C circuit is 90 degrees behind the current.
이러한 점을 착안할 때 아날로그 신호 처리 VLSI(very large scale integration)에서 C 값을 가지는 집적 회로에 대해 적절한 L값을 갖는 인덕터(inductor)를 설계함으로써, 시정수(τ)를 제어할 수 있으며 공진 주파수를 만들어 소비 전력을 최소화시킬 수 있다.With this in mind, by designing an inductor with an appropriate L value for an integrated circuit with a C value in analog signal processing very large scale integration (VLSI), the time constant (τ) can be controlled and the resonant frequency To minimize power consumption.
본 발명의 과제는 인덕터를 형성하는 것이다.An object of the present invention is to form an inductor.
본 발명의 다른 과제는 집적 회로의 소비 전력을 감소시키는 것이다.Another object of the present invention is to reduce the power consumption of integrated circuits.
도 1은 본 발명에 따른 인덕터를 도시한 것이고,1 shows an inductor according to the invention,
도 2는 본 발명에 따른 인덕터에 대한 단면도이며,2 is a cross-sectional view of an inductor according to the present invention;
도 3은 본 발명에 따른 인덕터를 위에서 본 것이고,3 is a view from above of an inductor according to the invention,
도 4는 도 1의 인덕터에 대한 모식도이다.4 is a schematic diagram of the inductor of FIG. 1.
이러한 과제를 해결하기 위해 본 발명에서는 다수의 제1 및 제2 배선을 접촉구를 통하여 연결함으로써 인덕터를 형성한다.In order to solve this problem, the present invention forms an inductor by connecting a plurality of first and second wires through contact holes.
본 발명에 따른 인덕터는 기판 위에 형성되어 있는 다수의 제1 배선과 제1 배선을 덮고 있으며 제1 배선의 양끝을 각각 드러내는 제1 및 제2 접촉구를 가지고 있는 절연막, 그리고 절연막 상부에 형성되어 있으며 제1 및 제2 접촉구를 통하여 제1 배선과 이어져 있는 제2 배선으로 이루어진다.The inductor according to the present invention is formed on an insulating film covering a plurality of first wirings and first wirings formed on a substrate and having first and second contact holes respectively exposed at both ends of the first wirings, and an upper portion of the insulating film. The second wiring is connected to the first wiring through the first and second contact holes.
여기서, 절연막은 TEOS나 BPSG, PSG, SOG 및 SixOy중의 어느 하나로 이루어질 수 있다.Here, the insulating film may be made of any one of TEOS, BPSG, PSG, SOG, and Si x O y .
또한, 제1 및 제2 배선은 Al, Cu, W, Ni 및 Mo 그리고 Al 화합물, Cu 화합물, W 화합물, Ni 화합물 및 Mo 화합물 중의 어느 하나로 이루어질 수 있다.In addition, the first and second wirings may be made of any one of Al, Cu, W, Ni and Mo, and an Al compound, a Cu compound, a W compound, a Ni compound, and a Mo compound.
이와 같이 본 발명에서는 제1 및 제2 배선을 접촉구를 통하여 연결하여 인덕터를 형성함으로써 시정수를 조절할 수 있으며, 공진 주파수를 형성하여 소비 전력을 최소화할 수 있다.As described above, in the present invention, the time constant can be adjusted by forming the inductor by connecting the first and second wires through the contact hole, and the power consumption can be minimized by forming the resonance frequency.
그러면, 도면을 참조하여 본 발명에 따른 인덕터에 관하여 상세히 설명한다.Next, the inductor according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 인덕터를 도시한 것이고, 도 2는 본 발명에 따른 인덕터에 대한 단면도이며, 도 3은 본 발명에 따른 인덕터를 위에서 본 것이고, 도 4는 도 1의 인덕터에 대한 모식도이다.1 illustrates an inductor according to the present invention, FIG. 2 is a cross-sectional view of the inductor according to the present invention, FIG. 3 is a view of the inductor according to the present invention from above, and FIG. 4 is a schematic diagram of the inductor of FIG. 1. .
도 1 내지 도 3에 도시한 바와 같이 반도체 소자(도시하지 않음)를 포함하는 반도체 기판(10) 위에 제1 내지 제7 하부 배선층(21, 22, 23, 24, 25, 26, 27)이 형성되어 있고, 그 위에 층간 절연막(30)이 하부 배선층(20)을 덮고 있다. 층간 절연막(30)에는 제1 내지 제7 하부 배선층(21, 22, 23, 24, 25, 26, 27)의 양끝을 각각 드러내는 비아 홀(310, 320)이 형성되어 있으며 비아 홀(310, 320)은 각각 금속막으로 채워져 있다. 이때, 층간 절연막(30)은 TEOS(tetraethyl orthosilicate)나 BPSG(borophosphosilicate glass), PSG(phosphosilicate glass), SOG(spin-on glass) 및 SixOy중의 어느 하나로 이루어질 수 있다. 층간 절연막(30) 상부에는 제1 내지 제8 상부 배선층(41, 42, 43, 44, 45, 46, 47, 48)이 형성되어 있다. 여기서, 하부 배선층(21, 22, 23, 24, 25, 26, 27)과 상부 배선층(41, 42, 43, 44, 45, 46, 47, 48)은 Al(알루미늄), Cu(구리), W(텅스텐), Ni(니켈) 및 Mo(몰리브덴) 그리고 Al 화합물, Cu 화합물, W 화합물, Ni 화합물 및 Mo 화합물 중의 어느 하나로 이루어질 수 있다. 상부 배선층(41, 42, 43, 44, 45, 46, 47, 48)은 하부 배선층(21, 22, 23, 24, 25, 26, 27)에 대해 일정한 각을 가지고 틀어져 있으며, 제1 상부 배선층(41)은 제1 하부 배선층(21)의 제1 비아 홀(311)과 이어지고, 제2 상부 배선층(42)은 제1 하부 배선층(21)의 제2 비아 홀(321) 및 제2 하부 배선층(22)의 제1 비아 홀(312)과 이어지며, 제3 상부 배선층(43)은 제2 하부 배선층(22)의 제2 비아 홀(322) 및 제3 하부 배선층(23)의 제1 비아 홀(313)과 이어진다. 이와 같이 이어진 배선층은 도 4에 도시한 바와 같은 코일 형태를 이루어 인덕터를 형성한다.1 to 3, the first to seventh lower wiring layers 21, 22, 23, 24, 25, 26, and 27 are formed on the semiconductor substrate 10 including the semiconductor elements (not shown). The interlayer insulating film 30 covers the lower wiring layer 20 thereon. Via layers 310 and 320 are formed in the interlayer insulating layer 30 to expose both ends of the first to seventh lower wiring layers 21, 22, 23, 24, 25, 26, and 27, respectively. ) Are each filled with a metal film. In this case, the interlayer insulating layer 30 may be formed of any one of tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG), and Si x O y . First to eighth upper wiring layers 41, 42, 43, 44, 45, 46, 47, and 48 are formed on the interlayer insulating layer 30. Here, the lower wiring layers 21, 22, 23, 24, 25, 26, 27 and the upper wiring layers 41, 42, 43, 44, 45, 46, 47, 48 are Al (aluminum), Cu (copper), W (tungsten), Ni (nickel) and Mo (molybdenum) and Al compounds, Cu compounds, W compounds, Ni compounds and Mo compounds of any one. The upper wiring layers 41, 42, 43, 44, 45, 46, 47, and 48 are twisted at a predetermined angle with respect to the lower wiring layers 21, 22, 23, 24, 25, 26, and 27, and the first upper wiring layer 41 is connected to the first via hole 311 of the first lower wiring layer 21, and the second upper wiring layer 42 is the second via hole 321 and the second lower wiring layer of the first lower wiring layer 21. The first via hole 312 of the second wiring 22, and the third upper wiring layer 43 is connected to the second via hole 322 of the second lower wiring layer 22 and the first via of the third lower wiring layer 23. It leads to the hole 313. The wiring layer thus continued forms a coil as shown in FIG. 4 to form an inductor.
여기서, 제1 상부 배선층(41)과 제5 상부 배선층(45)에 회로를 연결하여 제1 내지 제5 상부 배선층(41, 42, 43, 44, 45)만으로 인덕터를 형성할 수 있으며, 필요에 따라 다른 배선층, 예를 들어 제1 상부 배선층(41)과 제8 상부 배선층(48)에 회로를 연결함으로써 인덕턴스(L) 값을 조절할 수 있다.Here, a circuit may be connected to the first upper wiring layer 41 and the fifth upper wiring layer 45 to form an inductor using only the first to fifth upper wiring layers 41, 42, 43, 44, and 45. Accordingly, the inductance L value can be adjusted by connecting a circuit to another wiring layer, for example, the first upper wiring layer 41 and the eighth upper wiring layer 48.
본 발명에서는 상부 및 하부 배선층을 비아 홀을 통해 연결하여 인덕터를 형성함으로써, 집적 회로의 시정수를 제어하고 공진 주파수를 형성함으로써 소비 전력을 최소화할 수 있다.In the present invention, the inductor is formed by connecting the upper and lower wiring layers through the via holes, thereby controlling the time constant of the integrated circuit and forming a resonance frequency, thereby minimizing power consumption.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067727A KR20010066142A (en) | 1999-12-31 | 1999-12-31 | a inductor of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067727A KR20010066142A (en) | 1999-12-31 | 1999-12-31 | a inductor of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010066142A true KR20010066142A (en) | 2001-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990067727A KR20010066142A (en) | 1999-12-31 | 1999-12-31 | a inductor of integrated circuit |
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| KR (1) | KR20010066142A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08172161A (en) * | 1994-12-16 | 1996-07-02 | Hitachi Ltd | Inductor element and its manufacture and monolithic microwave integrated circuit using the same |
| US5612660A (en) * | 1994-07-27 | 1997-03-18 | Canon Kabushiki Kaisha | Inductance element |
| US5640433A (en) * | 1992-09-11 | 1997-06-17 | Reltec Corporation | Conversion of synchronous/asynchronous signals |
| KR20000023863A (en) * | 1998-10-19 | 2000-05-06 | 김연태 | Inductor for high-frequency integrated circuit and method for fabricating the same |
-
1999
- 1999-12-31 KR KR1019990067727A patent/KR20010066142A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640433A (en) * | 1992-09-11 | 1997-06-17 | Reltec Corporation | Conversion of synchronous/asynchronous signals |
| US5612660A (en) * | 1994-07-27 | 1997-03-18 | Canon Kabushiki Kaisha | Inductance element |
| JPH08172161A (en) * | 1994-12-16 | 1996-07-02 | Hitachi Ltd | Inductor element and its manufacture and monolithic microwave integrated circuit using the same |
| KR20000023863A (en) * | 1998-10-19 | 2000-05-06 | 김연태 | Inductor for high-frequency integrated circuit and method for fabricating the same |
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