KR20010065781A - Circuit for yielding gate signal with multi-level in thin film transistor liquid crystal display - Google Patents

Abstract

PURPOSE: A gate driving signal generation circuit which has multi level is provided to improve flicker phenomenon of liquid crystal panel easily by generating gate driving signal of multi level using several resistances and capacitors and OP amp. CONSTITUTION: A high level signal generation unit(100) receives a gate-on enable signal(OE1) and a comparison signal(comp), and generates a high level signal(Vgh) of a gate driving signal(Von). A driving signal generation unit(200) receives the output signal(Vgh) of the high level signal generation unit(100) and a low level signal(Vgl) of the gate driving signal(Von), and outputs the gate driving signal(Von). In the high level signal generation unit(100), an inverse amplitude unit amplifies inversely the gate-on enable signal(OE1) using OP amp, and an output unit shifts the output signal of the inverse amplitude unit into high level of gate driving signal which has multi level.

Description

CIRCUIT FOR YIELDING GATE SIGNAL WITH MULTI-LEVEL IN THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY}

The present invention relates to a driving circuit of a thin film transistor liquid crystal display (TFT-LCD), and more particularly to a circuit for generating a gate driving signal having a multi level.

Cathode Ray Tube (CRT) cathode ray tube (CRT), which is the most widely used display device, has been spotlighted as a display device including TV and computer monitor because of its easy color and fast operation speed. However, the cathode ray tube has a disadvantage in that the portability is not only thick because of the structural characteristic of securing a certain distance between the electron gun and the screen, but also because the power consumption is large and the weight is considerably heavy.

In order to overcome the disadvantages of the cathode ray tube as described above, various various display devices have been devised. Among them, the most practical device is a liquid crystal display (LCD).

Although the LCD is darker in screen and somewhat slower in operation than the cathode ray tube, each pixel may be operated according to a signal scanned on a plane without having an electron gun. It can be used as a very thin display device such as a wall-mounted TV. In addition, since the liquid crystal display device is light in weight and consumes considerably less power than the cathode ray tube, it is recognized that the liquid crystal display device is most suitable as a portable display device such as being used as a display of a battery operated notebook computer.

As described above, a liquid crystal display that is in the spotlight as a next generation display device is briefly shown in FIG. 1. Referring to FIG. 1, the liquid crystal display includes a liquid crystal panel 10, a gate driving circuit 15 and a source driving circuit 14 capable of driving the liquid crystal panel 10. The liquid crystal panel 10 includes a plurality of gate lines 12 and a plurality of data lines 11 intersecting in a matrix form on a substrate, and thin film transistors (TFTs) 13 at the intersections thereof. ) And pixels are arranged. In addition, the gate driving circuit 15 sequentially applies a gate signal for turning on the thin film transistor 13 to the gate line 12, and the source driving circuit 14 The data signal is applied to the data line 11 to transmit the data signal to the pixel through the thin film transistor driven by the scan signal.

In the liquid crystal display as described above, all the thin film transistors connected to the gate line 12 are turned on by a gate signal sequentially applied to the gate line 12 of the liquid crystal panel 10 in the gate driving circuit 15. When turned on, the data signal applied to the data line 11 of the liquid crystal panel 10 operates on the principle that the data signal is transferred to the pixel through the source and the drain of the turned-on thin film transistor.

FIG. 2 is an electrical equivalent circuit diagram of a pixel of the thin film transistor liquid crystal display (TFT-LCD) as described above. Referring to FIG. 2, in the thin film transistor liquid crystal display, individual pixels are divided into gate lines Gn-1 and Gn and data lines Dn and Dn-1, and applied to the drain electrodes of the thin film transistor TFT through the data lines. The data signal is charged in the pixel electrode and the storage capacitor (Cst) when the gate signal through the gate line is applied to the gate electrode of the thin film transistor. In the above, the pixel electrode is represented by the liquid crystal capacitor Clc, and the common electrode voltage is represented by Vcom. The voltage of the data signal charged in the pixel electrode is lowered by the parasitic capacitance Cgd between the gate electrode and the drain electrode of the thin film transistor TFT, which is referred to as a kick back (Vk) voltage.

The thin film transistors connected to the respective pixel electrodes on the liquid crystal panel are not turned on or off independently, but all the thin film transistors connected to one gate line are turned on or off at the same time so that the data signal is applied to the pixel electrodes. Control what is applied. As described above, a data signal is applied to each gate line. This period is referred to as a horizontal line period, and a voltage in a saturation region must be applied to the gate line to turn on the thin film transistor. The gate signal becomes the turn-on voltage of the thin film transistor, and has a value of about 16 volts or more, and is generally referred to as a gate driving signal Von.

The gate driving signal as described above is distorted by the self-resistance and parasitic capacitance of the gate line, thereby distorting the data signal charged in the pixel electrode. Thus, a gate on enable signal (OE) controlling the application of the gate driving signal (OE) ) To reduce the width of the gate driving voltage and apply it to the pixel electrode.

3 is a waveform diagram illustrating a relationship between the gate driving voltage Von, the data voltage Vdata, and the gate-on control signal OE for one pixel. 2 and 3, when the gate driving voltage Von is applied, the thin film transistor TFT is turned on so that the data voltage is applied to the liquid crystal capacitor Clc, the storage capacitor Cst, and the parasitic capacitor Cgd. Is charged. The gate driving voltage Von is turned off by the gate on control signal OE and remains on-state only for a period shorter than the horizontal line period 1H. At this time, when the gate driving voltage Von is turned off, the applied data voltage is maintained at the pixel electrode at a value distorted by the kickback voltage due to the parasitic capacitor Cgd.

In order to prevent deterioration of the liquid crystal, the data signal applied to the pixel electrode is alternately applied with the positive and negative voltages with respect to the common electrode voltage Vcom. Therefore, the voltage charged in each pixel is applied with the polarity changed every frame. At this time, the effective value of the voltage actually applied to the liquid crystal is determined by the area between the data voltage and the common electrode voltage Vcom. Therefore, a constant voltage can be applied to the pixel electrode only when the area around the common voltage is symmetrical. have. However, since the kickback voltage Vk always acts in the direction of pulling down the data signal regardless of the polarity of the data signal, the positive data signal and the negative data signal have different values. This eventually causes the flicker to flicker.

The above-described flicker phenomenon has various causes, among which flicker occurs on the left and right sides of the panel according to the delay of the gate driving signal applied to the gate line at the input terminal and the output terminal, and the leakage current of the thin film transistor. By this, it can be divided into the flicker phenomenon which arises in the whole panel and the flicker phenomenon of the whole panel which arises by the leakage of a liquid crystal.

In particular, in order to solve the flicker phenomenon on the left and right of the panel as described above, in the related art, the common electrode voltage level is adjusted so that the positive data signal and the negative data signal are symmetric to reduce the flicker caused by the kickback voltage. Since the dielectric constant of the liquid crystal constituting the electrode changes depending on the applied voltage, it is difficult to accurately compensate the kickback voltage.

Therefore, in recent years, flicker is reduced by applying a gate driving signal having multiple levels to the gate electrode to reduce the absolute value of the kickback voltage and to reduce the kickback voltage deviation between the input terminal and the output terminal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate driving signal generation circuit having multiple levels so as to reduce the flicker phenomenon.

1 is a schematic diagram showing a liquid crystal panel and a driving circuit of a liquid crystal display device;

2 is an electrical equivalent circuit diagram of a pixel of a thin film transistor liquid crystal display device;

3 is a waveform diagram showing a relationship between a gate driving signal, a data signal, and a gate-on control signal;

4 is a waveform diagram illustrating a gate driving signal and a gate on control signal having multiple levels;

5 is a block diagram of a gate driving signal generation circuit having multiple levels according to an embodiment of the present invention;

6 is a circuit diagram of a high level signal generator in the gate driving signal generator of FIG. 5;

7 is a signal waveform diagram of each node in the high level signal generator of FIG. 6;

(Name of the code for the main part of the drawing)

100: high level signal generator 200: drive signal generator

110: inverting amplifier 120: output unit

111: inverting input unit 112: non-inverting input unit

OP: OP amplifier R1, ..., R4: resistor

C1, C2: Capacitor D1: Diode

OE1: Gate-On Enable Signal Comp: Comparison Signal

Vgh: high level output signal Vgh1: first high level

Vgh2: Second high level Von: Gate drive signal

In order to achieve the above object, the gate drive signal generation circuit of the present invention includes a high level signal generator for generating multiple high level signals of a gate drive signal using a gate on enable signal and a comparison signal, and the high level signal. And a driving signal generator for receiving the high level signal of the gate driving signal and the low level signal of the gate driving signal and outputting the gate driving signal.

The high level signal generation unit uses a gate on enable signal and a comparison signal as an input signal, an inverting amplifier for inverting and amplifying the gate on enable signal using an operational amplifier, and an output of the inverting amplifier. And an output unit for shifting the signal to a high level of the gate driving signal having multiple levels.

The comparison signal is characterized by using a first high level signal or a second high level signal in the multi-level gate driving signal.

The inverting amplifier unit transmits a gate-on enable signal and an output signal of the OP amplifier to the inverting input terminal of the OP amplifier through a resistor, and a non-inverting input of the comparison signal through a plurality of resistors and capacitors. It characterized in that it comprises a non-inverting input unit for transmitting to the terminal.

The inverting input unit may include a first resistor for transmitting a gate on enable signal to an inverting input terminal of an OP amplifier, and a second resistor for feeding back an output signal of the OP amplifier to an inverting input terminal. .

The non-inverting input unit may include a third resistor for transmitting a comparison signal to the non-inverting input terminal of the OP amplifier, a fourth resistor and a first capacitor connected in parallel to the non-inverting input terminal.

The output unit may be connected in parallel with a diode for transmitting the first high level signal of the gate driving signal and a second capacitor for transmitting the output signal of the inverting amplifier.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 illustrates waveforms of a gate driving signal using multiple levels and a gate on control signal for controlling the level of the gate driving signal in order to improve the left and right flicker of the liquid crystal panel due to the delay variation of the gate driving signal. will be.

Referring to FIG. 4, the gate driving signal Von has a dual level of the first high level Vgh1 and the second high level Vgh2, and thus, charges the pixel at the first high level Vgh1. And reduces the kickback voltage of the data signal at the second high level Vgh2.

At this time, if the time t1 for maintaining the second high level Vgh2 is too long in the horizontal line period, the charging time of the pixel is reduced, and if it is too short, the kickback voltage is not reduced, and thus it should be maintained for a proper time. 1 × 10 ⁻⁶ to 5 × 10 ⁻⁶ seconds. In the above, the time t1 of maintaining the second high level Vgh2 may be adjusted by using the gate on enable signal OE1.

In the present invention, the gate on enable signal OE1 is used to generate a gate driving signal having multiple levels.

5 is a block diagram of a multi-level gate driving signal generation circuit according to an embodiment of the present invention. Referring to FIG. 5, the gate driving signal generation circuit of the present invention receives a gate on enable signal OE1 and a comparison signal comp to generate a high level signal Vgh of the gate driving signal Von. Generation of a driving signal that receives the level signal generator 100, the output signal Vgh of the high level signal generator 100, and the low level signal Vgl of the gate driving signal, and outputs a gate driving signal Von. It consists of a portion (200).

6 illustrates a circuit diagram of the high level signal generator 100. Referring to FIG. 5, the high level signal generator 100 of the present invention uses a gate on enable signal OE1 and a comparison signal Comp as an input signal, and uses the OP amplifier OP to perform the gate on in. An inverting amplifier 110 for inverting and amplifying the enable signal OE1 and an output unit 120 for shifting the output signal node1 of the inverting amplifier 110 to a high level of a gate driving signal having multiple levels. )

The comparison signal Comp is a signal of the first high level Vgh1 or the second high level Vgh2 in the gate driving signal Von having the first high level Vgh1 and the second high level Vgh2. Can be used.

The inverting amplifier 110 inverts the gate on enable signal OE1 and the output signal node1 of the OP amplifier OP through the first and second resistors R1 and R2. The non-inverting of the OP amplifier OP by comparing the comparison signal (Comp) through the inverting input unit 111, the third and fourth resistors (R3, R4), and the first capacitor (C1) to the input terminal (-) It consists of a non-inverting input unit 112 for transmitting to the input terminal (+).

The inverting input unit 111 transmits the gate-on enable signal OE1 to the inverting input terminal (-) of the OP amplifier OP through the first resistor R1 and outputs the output signal of the OP amplifier OP. (node1) is fed back to the inverting input terminal (-) through the second resistor (R2).

Accordingly, the inverting amplifier 110 compares the voltage V1 applied to the inverting input terminal (−) of the OP amplifier OP with the voltage V2 applied to the non-inverting input terminal (+), respectively. Inverts and amplifies the difference between two input signals (V2-V1).

At this time, the voltage node1 output through the OP amplifier OP is represented by Equation 1 below.

× (V2-V1)

Therefore, by adjusting the values of the first and second resistors R1 and R2, the magnitude of the voltage node1 output from the OP amplifier OP may be adjusted. In this case, the resistance value is adjusted so that the pulse size of the voltage node1 output from the OP amplifier OP becomes a difference between the first high level Vgh1 and the second high level Vgh2 of the gate driving signal. The output voltage node1 of the OP amplifier OP has the same amplitude as the gate-on enable signal OE1.

The non-inverting input unit 112 includes a third resistor R3 for transmitting the comparison signal Comp to the non-inverting input terminal (+) of the OP amplifier (OP) and the non-inverting input terminal (+) in parallel. The fourth resistor R4 and the first capacitor C1 are connected to each other.

The third resistor R3 and the fourth resistor R4 divide the comparison signal Comp to adjust the magnitude of the input voltage V2 applied to the non-inverting input terminal + of the OP amplifier OP. In addition, the fourth resistor R4 and the first capacitor C1 block a high frequency portion of the comparison signal Comp and serve as a low pass filter (LPT) for passing the low frequency portion, thereby operating only a DC component. Pass it to the amplifier (OP).

As a result, the inverting amplifier 110 divides the comparison signal Comp by the third and fourth resistors R3 and R4 and applies the voltage V2 applied to the non-inverting input terminal + of the OP amplifier OP. And amplifies and outputs the difference (V2-V1) of the voltage (V1) applied to the inverting input terminal (-) by the first and second resistors (R1, R2).

The output unit 120 includes a diode D1 for transmitting the first high level Vgh1 signal of the gate driving signal and a second capacitor C2 for delivering the output signal node1 of the inverting amplifier 110. ) Are connected in parallel.

The diode D1 transfers only a positive portion of the first high level Vgh1 signal, and the second capacitor C2 blocks an AC component of the OP amplifier output signal node1 and transmits only a DC component. do. The first high level signal Vgh1 transmitted through the diode D1 and the output signal node1 of the inverting amplifier 110 transmitted through the second capacitor C2 are added to each other to generate a gate driving signal. By raising by one high level Vgh1, a high level signal Vgh having first and second high levels Vgh1 and Vgh2 is generated.

The high level signal Vgh generated as described above is combined with the low level signal Vgl of the gate driving signal in the driving signal generator 200, and thus has gates having the first and second high levels Vgh1 and Vgh2. The driving signal Von is generated.

FIG. 7 illustrates waveforms of each node in the high level signal generator 100 of FIG. 6. Referring to FIG. 7, the high level signal generator 100 uses a gate on enable signal OE1 to generate a gate driving signal Von having multiple levels, and a general gate on enable signal OE1. ) Is a signal having a magnitude of 3.3 volts, and is applied as a pulse during the time for generating the second high level Vgh2 of the gate driving signal Von.

The inverting amplifier 110 adjusts the value of the plurality of resistors R1,..., And R4 constituting the inverting amplifier 110 to adjust the pulse size of the signal node1 output from the OP amplifier OP. The difference between the first high level Vgh1 and the second high level Vgh2 of the gate driving signal Von is Vgh1 to Vgh2.

As a result, the output unit node 1 raises the output signal node1 of the OP amplifier OP by the first high level Vgh1 of the gate driving signal, thereby generating an output signal of the high level Vgh.

The high level (Vgh) signal generated in this manner is combined with the low level signal (Vgl) of the gate driving signal in the driving signal generator 200, and thus has a gate driving signal having the first and second high levels (Vgh1 and Vgh2). Von).

As described in detail above, according to the multi-level gate driving signal generating circuit of the present invention, the gate driving signal having the multi-level is generated by using a few resistors, capacitors, and an OP amplifier, thereby making it easier for the liquid crystal panel. The flicker phenomenon can be improved.

Therefore, it is possible to improve the quality of the liquid crystal display device at a low cost.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (7)

In the driving circuit of the liquid crystal display device, A high level signal generator for generating multiple high level signals of the gate driving signal using the gate on enable signal and the comparison signal; And a driving signal generator for generating a gate driving signal by combining the high level signal of the gate driving signal transmitted from the high level signal generator and the low level signal of the gate driving signal and combining the two signals. A gate drive signal generation circuit having a level. The method of claim 1, wherein the high level signal generator An inverting amplifier for inverting and amplifying the gate on enable signal by using a gate on enable signal and a comparison signal as an input signal, and And an output unit configured to shift the output signal of the inverting amplifier into a high level signal having multiple levels to generate a high level signal of the gate driving signal. The method of claim 2, wherein the comparison signal is The first high level of the gate drive signal, or And a second high level signal. The method of claim 2, wherein the inverting amplifier section An inverting input unit for transmitting a gate-on enable signal and an output signal of the OP amplifier to the inverting input terminal of the OP amplifier through a resistor; And a non-inverting input unit for transmitting a comparison signal to a non-inverting input terminal of the OP amplifier through a plurality of resistors and capacitors. The method of claim 4, wherein the inverting input unit A first resistor for transferring the gate on enable signal to the inverting input terminal of the OP amplifier, And a second resistor for feeding back the output signal of the OP amplifier to the inverting input terminal. The method of claim 4, wherein the non-inverting input unit A third resistor for transmitting the comparison signal to the non-inverting input terminal of the OP amplifier, And a fourth resistor connected in parallel to said non-inverting input terminal, and a first capacitor. The method of claim 2, wherein the output unit A diode for delivering a first high level signal of the gate drive signal; And a second capacitor for transmitting the output signal of the inverting amplifier part in parallel to generate a high level output signal.