KR20010063766A - Method for planarization of semiconductor device - Google Patents
Method for planarization of semiconductor device Download PDFInfo
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- KR20010063766A KR20010063766A KR1019990061853A KR19990061853A KR20010063766A KR 20010063766 A KR20010063766 A KR 20010063766A KR 1019990061853 A KR1019990061853 A KR 1019990061853A KR 19990061853 A KR19990061853 A KR 19990061853A KR 20010063766 A KR20010063766 A KR 20010063766A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
Description
본 발명은 반도체소자의 평탄화방법에 관한 것으로, 특히 화학적 기계적 연마방법에 의한 평탄화공정에서 웨이퍼의 가장자리부분의 금속층패턴이 노출되는 것을 방지하는 반도체소자의 평탄화방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and more particularly, to a planarization method of a semiconductor device for preventing the metal layer pattern of the edge portion of a wafer from being exposed in the planarization process by a chemical mechanical polishing method.
반도체소자가 고집적화됨에 따라 소자의 형성공정중 단차의 발생이 증가하면서, 사진공정이 더욱 어렵게 되었다. 그런 이유로 평탄화 공정의 중요성은 날로 증가되고 있다.As semiconductor devices have been highly integrated, the generation of steps in the device formation process has increased, and the photolithography process has become more difficult. That is why the importance of the planarization process is increasing day by day.
최근 각광 받고 있는 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정은 이에 적합한 공정이라 할 수 있으나, 직접 웨이퍼의 표면을 물리적인 마찰에 의해 식각하기 때문에 파티클(particle)이 많이 발생하고, 미세한 패턴을 보호하는 데에 문제점이 발생하였다. 특히, 웨이퍼 상의 막질 식각의 균일성 확보에 많은 어려움이 있다.The chemical mechanical polishing (CMP) process, which has recently been in the spotlight, may be a suitable process. However, since the surface of the wafer is directly etched by physical friction, particles are generated and fine. There was a problem protecting the pattern. In particular, there are many difficulties in ensuring the uniformity of the film quality etching on the wafer.
반도체 박막의 평탄화 방법 중에 하나인 CMP 공정에서 식각 균일성에 가장 크게 해를 끼치는 부분은 웨이퍼의 가장자리 부위가 과도하게 연마되는 현상이다. 상기와 같이 웨이퍼의 가장자리가 과도하게 연마되는 현상은, 애초의 식각면에 비해서 50 %, 많게는 100 % 가까이 발생되고 있다.In the CMP process, which is one of the planarization methods of the semiconductor thin film, the most damaging portion of the etching uniformity is a phenomenon in which the edge of the wafer is excessively polished. As described above, the phenomenon in which the edge of the wafer is excessively polished has occurred 50% and as much as 100% compared to the original etching surface.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 평탄화방법을 자세히 설명하기로 한다.Hereinafter, a planarization method of a semiconductor device according to the related art will be described in detail with reference to the accompanying drawings.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 평탄화방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a planarization method of a semiconductor device according to the related art.
먼저, 반도체기판(10) 상부에 게이트전극 등의 하부구조물을 형성하고, 제1층간절연막(11)을 증착하여 평탄화시킨다.First, a lower structure such as a gate electrode is formed on the semiconductor substrate 10, and the first interlayer insulating film 11 is deposited and planarized.
다음, 제1확산방지막, 금속층 및 제2확산방지막의 적층구조를 형성하고, 패턴으로 예정되는 부분을 보호하는 마스크를 식각마스크로 상기 적층구조를 식각하여 제2확산방지막 패턴(14), 금속층패턴(13) 및 제1확산방지막패턴(12)을 형성한다.Next, the second diffusion barrier layer pattern 14 and the metal layer pattern may be formed by forming a stacked structure of the first diffusion barrier layer, the metal layer, and the second diffusion barrier layer, and etching the layer structure with an etching mask using a mask that protects a predetermined portion as a pattern. (13) and the first diffusion barrier pattern 12 are formed.
그 다음, 전체표면 상부에 제2층간절연막(15)을 형성한다. 이때, 상기 제2층간절연막(15)은 BPSG(boro-phospho silicate glass)막, PSG(phospho silicate glass)막, FSG(fluorinated silicate glass)막, APL(advanced planarization layer)산화막, TEOS(tetra ethyl ortho silicate glass)산화막 및 HDP(high density plasma)산화막으로 이루어지는 군에서 임의로 선택되는 하나를 사용하여 형성한다. (도 1a 참조)Next, a second interlayer insulating film 15 is formed over the entire surface. In this case, the second interlayer insulating layer 15 may include a boro-phospho silicate glass (BPSG) film, a phosphorous silicate glass (PSG) film, a fluorinated silicate glass (FSG) film, an advanced planarization layer (APL) oxide film, and a tetra ethyl ortho (TEOS). It is formed by using one selected from the group consisting of silicate glass) oxide film and HDP (high density plasma) oxide film. (See Figure 1A)
다음, 상기 제2층간절연막(15)을 CMP공정으로 평탄화시키는 공정을 실시한다. 이때, 상기 CMP공정시 웨이퍼의 가장자리(Ⅰ)부분이 웨이퍼의 중심부(Ⅱ)의 연마속도보다 빠르기 때문에 상기 CMP공정후 잔류하는 제2층간절연막(15)의 두께가 다를 뿐만 아니라,상기 CMP공정이 과도하게 진행되는 경우 도 1b 의 ⓧ 부분과 같이 금속층패턴(13)이 노출되어 전기적 특성을 저하시키거나, 후속공정에서 상기 금속층패턴(13)이 리프팅(lifting)되어 웨이퍼 내의 전체소자에 오염원으로 작용하여 공정수율을 저하시키는 문제점이 있다. (도 1b 참조)Next, a process of flattening the second interlayer insulating film 15 by a CMP process is performed. At this time, since the edge (I) of the wafer during the CMP process is faster than the polishing speed of the center (II) of the wafer, the thickness of the second interlayer insulating film 15 remaining after the CMP process is different, and the CMP process In case of excessive progress, the metal layer pattern 13 is exposed as shown in FIG. 1B to deteriorate electrical characteristics, or in the subsequent process, the metal layer pattern 13 is lifted to act as a pollution source to all devices in the wafer. There is a problem of lowering the process yield. (See FIG. 1B)
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속층 패턴을 형성하고, CMP공정시 사용되는 슬러리에 대하여 낮은 연마속도를 갖는 Si를 다량함유하는 SiON(이하 SRON이라 함)막 또는 질화막을 식각방지막으로 형성한 다음, 층간절연막을 형성한 후 CMP공정을 실시하여 상기 층간절연막이 상기 금속층 패턴의 상부에 균일한 두께로 형성되도록 하는 반도체소자의 평탄화방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, to form a metal layer pattern, etching a SiON (hereinafter referred to as SRON) film or nitride film containing a large amount of Si having a low polishing rate for the slurry used in the CMP process The purpose of the present invention is to provide a method of planarizing a semiconductor device in which the interlayer insulating film is formed to have a uniform thickness on the upper portion of the metal layer pattern by forming a barrier film and then forming an interlayer insulating film and then performing a CMP process.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 평탄화방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a planarization method of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명에 따른 반도체소자의 평탄화방법을 도시한 단면도.2A to 2C are cross-sectional views showing a planarization method of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 20 : 반도체기판 11, 21 : 제1층간절연막10, 20: semiconductor substrate 11, 21: first interlayer insulating film
12, 22 : 제1확산방지막 13, 23 : 금속층패턴12, 22: first diffusion barrier 13, 23: metal layer pattern
14, 24 : 제2확산방지막 15, 26 : 제2층간절연막14, 24: second diffusion barrier 15, 26: second interlayer insulating film
25 : 식각방지막 27 : 제3층간절연막25: etch stop layer 27: third interlayer insulating film
Ⅰ : 웨이퍼의 가장자리 Ⅱ : 웨이퍼의 중심부Ⅰ: edge of wafer Ⅱ: center of wafer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 평탄화방법은,The planarization method of the semiconductor device according to the present invention for achieving the above object,
소정의 하부구조물이 구비되는 반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate provided with a predetermined lower structure;
상기 제1층간절연막 상부에 제1확산방지막패턴, 금속층패턴 및 제2확산방지막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a first diffusion barrier pattern, a metal layer pattern, and a second diffusion barrier pattern on the first interlayer insulating layer;
전체표면 상부에 Si를 다량함유하는 SiON막을 식각방지막으로 형성하는 공정과,Forming a SiON film containing a large amount of Si on the entire surface as an etching prevention film,
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 식각방지막이 노출될 때까지 상기 제2층간절연막을 제거하는 화학적 기계적 연마공정을 실시하여 웨이퍼의 가장자리 및 중심부를 균일하게 평탄화시키되, 상기 화학적 기계적 연마공정은 세리아계열의 슬러리를 사용하여 실시하는 공정과,A chemical mechanical polishing process is performed to remove the second interlayer dielectric layer until the etch stop layer is exposed to uniformly planarize the edge and the center of the wafer, and the chemical mechanical polishing process is performed using a ceria-based slurry. and,
전체표면 상부에 제3층간절연막을 형성하는 공정을 포함하는 것을 제1특징으로 한다.A first feature is to include a step of forming a third interlayer insulating film over the entire surface.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 평탄화방법은,The planarization method of the semiconductor device according to the present invention for achieving the above object,
소정의 하부구조물이 구비되는 반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate provided with a predetermined lower structure;
상기 제1층간절연막 상부에 제1확산방지막패턴, 금속층패턴 및 제2확산방지막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a first diffusion barrier pattern, a metal layer pattern, and a second diffusion barrier pattern on the first interlayer insulating layer;
전체표면 상부에 질화막을 식각방지막으로 형성하는 공정과,Forming a nitride film as an etch stop layer on the entire surface;
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 식각방지막이 노출될 때까지 상기 제2층간절연막을 제거하는 화학적 기계적 연마공정을 실시하되, 상기 화학적 기계적 연마공정은 실리카계열의 슬러리를 사용하여 실시하는 공정과,Performing a chemical mechanical polishing process of removing the second interlayer dielectric layer until the etch stop layer is exposed, wherein the chemical mechanical polishing process is performed using a silica-based slurry;
전체표면 상부에 제3층간절연막을 형성하는 공정을 포함하는 것을 제2특징으로 한다.A second feature is to include a step of forming a third interlayer insulating film over the entire surface.
이하, 본 발명에 따른 반도체소자의 평탄화방법에 관하여 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a planarization method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명에 따른 반도체소자의 평탄화방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a planarization method of a semiconductor device according to the present invention.
먼저, 반도체기판(20) 상에 여러가지 크기와 형태를 가지는 하부구조물들을 형성하고, 상기 구조의 전 표면에 제1층간절연막(21)을 형성한다. 이때, 상기 제1층간절연막(21)에는 후속공정으로 형성되는 배선과 상기 반도체기판(20)에서 콘택으로 예정되는 부분과 접속되는 콘택플러그가 구비되어 있다.First, substructures having various sizes and shapes are formed on the semiconductor substrate 20, and a first interlayer insulating layer 21 is formed on the entire surface of the structure. In this case, the first interlayer insulating film 21 is provided with a wiring formed in a subsequent process and a contact plug connected to a portion of the semiconductor substrate 20 which is intended as a contact.
다음, 전체표면 상부에 제1확산방지막(도시안됨), 금속층(도시안됨) 및 제2확산방지막(도시안됨)의 적층구조를 형성하고, 배선으로 예정되는 부분을 보호하는 식각마스크를 사용하여 상기 적층구조를 식각하여 제2확산방지막패턴(24), 금속층패턴(23) 및 제1확산방지막패턴(22)으로된 금속배선을 형성한다.Next, a lamination structure of a first diffusion barrier (not shown), a metal layer (not shown), and a second diffusion barrier (not shown) is formed on the entire surface, and the etching mask is used to protect a portion intended for wiring. The stacked structure is etched to form a metal wiring including the second diffusion barrier pattern 24, the metal layer pattern 23, and the first diffusion barrier pattern 22.
상기 제1확산방지막과 제2확산방지막은 Ti막 또는 TiN막 또는 TaN막 또는 TiSi2막을 사용하여 100 ∼ 1000Å 두께로 형성되고, 상기 금속층은 텅스텐층 또는 알루미늄층 또는 구리층 또는 구리합금층을 사용하여 3000 ∼ 8000Å 두께로 형성된다.The first diffusion barrier layer and the second diffusion barrier layer is formed to a thickness of 100 ~ 1000Å using a Ti film or a TiN film or TaN film or TiSi 2 film, the metal layer is a tungsten layer or an aluminum layer or a copper layer or a copper alloy layer To form a thickness of 3000 to 8000 Å.
그 다음, 전체표면 상부에 식각방지막(25)을 형성하되, 상기 식각방지막(25)은 Si를 다량 함유하는 SiON(이하 SRON 이라 함)막을 사용하여 700 ∼ 2000Å 두께로 형성한다. 이때, 상기 SRON막은 Si를 4 ∼ 30% 함유한다. 상기 식각방지막(25)은 PE-SiON막 또는 LP-SiON막으로 형성할 수도 있다.Then, an etch stop layer 25 is formed on the entire surface, the etch stop layer 25 is formed to a thickness of 700 ~ 2000 ∼ using a SiON (hereinafter referred to as SRON) film containing a large amount of Si. At this time, the SRON film contains 4 to 30% of Si. The etch stop layer 25 may be formed of a PE-SiON film or an LP-SiON film.
다음, 전체표면 상부에 제2층간절연막(26)을 형성한 후 300 ∼ 1000℃온도에서 플로우공정을 실시한다. 상기 제2층간절연막(26)은 BPSG막, PSG막, FSG막, APL산화막, TEOS산화막 및 HDP산화막으로 이루어지는 군에서 임의로 선택되는 하나를 사용하여 5000 ∼ 10000Å 두께로 형성한다.Next, after forming the second interlayer insulating film 26 over the entire surface, a flow process is performed at a temperature of 300 to 1000 ° C. The second interlayer insulating film 26 is formed to have a thickness of 5000 to 10000 kV using one arbitrarily selected from the group consisting of a BPSG film, a PSG film, an FSG film, an APL oxide film, a TEOS oxide film, and an HDP oxide film.
그 다음, 상기 식각방지막(25)이 노출될 때까지 CMP공정을 실시한다. 이때, 상기 CMP공정은 슬러리는 산화막 연마용 세리아계열 슬러리로서 pH 5 ∼ 11 의 산도를 갖으며, 50 ∼ 1000 ㎚ 정도 크기의 입자가 현탁된 슬러리를 50 ∼ 400ml/분 유량으로 유지하며 실시된다. (도 2b 참조)Next, the CMP process is performed until the etch stop layer 25 is exposed. At this time, the CMP process is carried out while maintaining the slurry at a flow rate of 50 to 400ml / min, the slurry is an oxide film polishing ceria-based slurry having a pH of 5 to 11, the particles suspended in the size of 50 to 1000 nm. (See Figure 2b)
그 후, 전체표면 상부에 제3층간절연막(27)을 형성하여 평탄화시키되, 상기 제3층간절연막(27)은 BPSG막, PSG막, FSG막, APL산화막, TEOS산화막 및 HDP산화막으로 이루어지는 군에서 임의로 선택되는 하나를 사용하여 2000 ∼ 10000Å 두께로형성한다. (도 2c 참조)Thereafter, a third interlayer insulating film 27 is formed and planarized over the entire surface, and the third interlayer insulating film 27 is formed of a BPSG film, a PSG film, an FSG film, an APL oxide film, a TEOS oxide film, and an HDP oxide film. It is formed to a thickness of 2000-10000 mm using one arbitrarily selected. (See Figure 2c)
한편, 상기 제2층간절연막(26)을 세리아계열 슬러리 이외에 실리카계열 슬러리를 사용하는 경우, 식각방지막(25)은 PE-질화막 또는 LP-질화막을 사용하여 형성할 수 있고, CMP공정은 슬러리는 산화막 연마용 슬러리로서 pH 9 ∼ 12 의 산도를 갖으며, 20 ∼ 200㎚ 정도 크기의 입자가 현탁된 슬러리를 50 ∼ 400ml/분 유량으로 유지하며 실시된다.On the other hand, when the second interlayer insulating film 26 using a silica-based slurry in addition to the ceria-based slurry, the etch stop layer 25 can be formed using a PE-nitride film or LP-nitride film, the CMP process is an oxide film slurry It is carried out while maintaining the slurry at a flow rate of 50 to 400 ml / min having an acidity of pH 9 to 12 as a polishing slurry and suspended particles of a size of about 20 to 200 nm.
상기한 바와 같이 본 발명에 따른 반도체소자의 평탄화방법은, 반도체기판에 금속층 패턴을 형성하고, 상기 금속층 패턴 상부에 식각방지막으로 Si를 다량함유하는 SiON막 또는 질화막을 형성하고 층간절연막을 형성한 후, 세리아계열 또는 실리카계열의 슬러리를 사용하여 상기 식각방지막이 노출될 때까지 CMP공정을 실시한 다음, 층간절연막을 재층착하여 웨이퍼의 가장자리와 중심부에 균일한 두께의 층간절연막이 잔류하도록 하여 CMP공정으로 상기 금속층 패턴이 리프팅되어 파티클의 소오스로 작용하여 소자의 전기적 특성이 저하되는 것을 방지하고, 후속공정을 용이하게 하여 공정 수율 및 소자 동작의 신뢰성을 향상시키는 이점이 있다.As described above, in the planarization method of a semiconductor device according to the present invention, a metal layer pattern is formed on a semiconductor substrate, a SiON film or a nitride film containing a large amount of Si is formed on the metal layer pattern as an etch stop layer, and an interlayer insulating film is formed. CMP process is performed using a slurry of ceria or silica series until the etch stop layer is exposed. Then, the interlayer dielectric layer is re-bonded so that an interlayer dielectric layer having a uniform thickness remains at the edge and the center of the wafer. The metal layer pattern is lifted to act as a source of particles to prevent the electrical characteristics of the device from being lowered, and to facilitate subsequent processes, thereby improving process yield and reliability of device operation.
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