KR20010063725A - A method of controlling a width of photoresist pattern for manufacturing a semiconductor device - Google Patents

A method of controlling a width of photoresist pattern for manufacturing a semiconductor device Download PDF

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KR20010063725A
KR20010063725A KR1019990061802A KR19990061802A KR20010063725A KR 20010063725 A KR20010063725 A KR 20010063725A KR 1019990061802 A KR1019990061802 A KR 1019990061802A KR 19990061802 A KR19990061802 A KR 19990061802A KR 20010063725 A KR20010063725 A KR 20010063725A
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South Korea
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photoresist pattern
line width
semiconductor device
controlling
manufacturing
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KR1019990061802A
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Korean (ko)
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유석빈
신강섭
문병오
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990061802A priority Critical patent/KR20010063725A/en
Publication of KR20010063725A publication Critical patent/KR20010063725A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Abstract

PURPOSE: A method for controlling a line width of a photoresist pattern for manufacturing a semiconductor device is provided to reduce manufacturing time and cost without a repeated exposure process, by forming an excellent fine photoresist pattern. CONSTITUTION: A conductive layer(12) is formed on a substrate(11) having various elements for forming a semiconductor device. The first photoresist pattern(13) is formed on the conductive layer. The first photoresist pattern is laterally etched to form the second photoresist pattern(130) having a desired line width by a plasma process.

Description

반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법{A method of controlling a width of photoresist pattern for manufacturing a semiconductor device}A method of controlling a width of photoresist pattern for manufacturing a semiconductor device

본 발명은 미세 선폭 조절 방법에 관한 것으로, 특히 포토레지스트 패턴에 의한 선 폭을 조절할 수 있는 미세 선폭 조절 방법에 관한 것이다.The present invention relates to a fine line width control method, and more particularly to a fine line width control method that can adjust the line width by the photoresist pattern.

반도체 기술의 진보와 더불어 반도체 장치, 더 나아가서는 반도체 소자의 고속화, 고 집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 패턴의 치수도 고 정밀화가 요구되고 있다.With advances in semiconductor technology, semiconductor devices, and moreover, high speed and high integration of semiconductor devices are in progress, and along with this, the necessity of miniaturization of patterns is increasing, and the size of patterns is also highly demanded.

특히, 패턴의 선 폭이 낮아짐에 따라 그 허용 오차의 한계치는 점점 낮아져, 예를 들어 게이트 전극의 형성에 있어서, 0.5㎛ 혹은 0.35㎛의 경우 오차는 ±0.04㎛, ±0.03㎛ 이상의 비교적 큰 여유도를 가진다. 하지만 0.18㎛의 경우에는 ±0.015㎛로 그 허용 오차의 한도가 매우 낮아진다. 만약 게이트 전극의 허용 오차를 넘어서 높게 되면, 후속의 트랜지스터를 구동할 수 있는 전류값이 부족하거나, 누설전류가 커져서 소자가 오동작을 하게 된다.In particular, as the line width of the pattern is lowered, the limit of the tolerance is gradually lowered. For example, in the formation of the gate electrode, in the case of 0.5 µm or 0.35 µm, the error has a relatively large margin of ± 0.04 µm and ± 0.03 µm or more. Has However, in the case of 0.18 µm, the limit of the tolerance is very low, ± 0.015 µm. If the gate electrode becomes high beyond the tolerance of the gate electrode, the device may malfunction due to a lack of a current value capable of driving a subsequent transistor or a large leakage current.

이 같은 측면에서 노광 공정은 그 정밀성 및 재현성이 더욱 요구되고 있지만, 하지층의 두께 변화, 노광 장비의 재현성 부족 등으로 인하여 일정하고 정확한 제어에 있어 재현성이 낮아지고 그로 인한 잦은 재작업을 실시해야 하여, 생산시간의 지연, 생산 경비 증가, 재 작업시 파티클 증가로 인한 생산 수율감소 등의 문제점이 있었다.In this respect, the exposure process requires more precision and reproducibility, but due to the change in the thickness of the underlying layer and the lack of reproducibility of the exposure equipment, the reproducibility is reduced in constant and accurate control, and frequent reworking is required. There was a problem such as a delay in production time, an increase in production cost, and a decrease in production yield due to an increase in particles during rework.

따라서 본 발명은, 포토레지스트 패턴에 의한 선 폭을 제어하며 재현성을 높일 수 있는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for adjusting the line width of a photoresist pattern for manufacturing a semiconductor device, which can control line width by a photoresist pattern and increase reproducibility.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판상에 도전층을 형성하는 단계; 상기 도전층상에 제 1 포토레지스트 패턴을 형성하는 단계; 및 플라즈마 공정으로 상기 제 1 포토레지스트 패턴을 측면 식각하여 원하는 선폭을 갖는 제 2 포토레지스트 패턴을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of controlling a line width of a photoresist pattern for manufacturing a semiconductor device, the method including: forming a conductive layer on a substrate on which various elements for forming a semiconductor device are formed; Forming a first photoresist pattern on the conductive layer; And side etching the first photoresist pattern by a plasma process to form a second photoresist pattern having a desired line width.

도 1a 내지 1c는 본 발명에 따른 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a line width adjusting method of a photoresist pattern for manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11:기판 12:도전층11: substrate 12: conductive layer

13:제 1 포토레지스트 패턴 120:도전층 패턴13: first photoresist pattern 120: conductive layer pattern

130:제 2 포토레지스트패턴130: second photoresist pattern

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하도록 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 1c는 본 발명에 따른 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a line width adjusting method of a photoresist pattern for manufacturing a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11)상에 도전층(12)을 형성하고, 그 도전층(12)의 상부에 제 1 포토레지스트 패턴(13)을 형성한다. 이때 제 1 포토레지스트 패턴(13)의 선폭은 형성하려고 하는 선폭보다 크게 형성하는데, 예를 들어 선폭이 0.25㎛인 공정 기술에서는 그 보다 0.01㎛ 내지 0.1㎛ 정도 크게 하여 0.26㎛ 내지 0.35㎛정도를 가지도록 제 1 포토레지스트 패(13)턴을 형성한다.Referring to FIG. 1A, a conductive layer 12 is formed on a substrate 11 on which various elements for forming a semiconductor element are formed, and a first photoresist pattern 13 is formed on the conductive layer 12. do. At this time, the line width of the first photoresist pattern 13 is formed to be larger than the line width to be formed. For example, in a process technology having a line width of 0.25 μm, the line width of the first photoresist pattern 13 is about 0.01 μm to 0.1 μm, which is 0.26 μm to 0.35 μm The first photoresist pattern 13 is formed.

도 1b를 참조하면, 플라즈마 공정에 의해 제 1 포토레지스트 패턴(13)을 식각하여 제 2 포토레지스트 패턴(130)을 형성한다.Referring to FIG. 1B, the first photoresist pattern 13 is etched by a plasma process to form a second photoresist pattern 130.

상기 플라즈마 공정은 O2가 함유된 가스 혹은 O2가 함유된 가스에 첨가가스로 N2, HBr 및 CF4중에서 하나 이상을 첨가하여 진행된다. O2가스는 플라즈마 상태에서 이온 및 라디칼로 분해, 생성되는데, 일반적으로 이온의 수보다 라디칼의 수가 103 이상 많이 발생되는데, 이 라디칼이 제 1 포토레지스트(13)와 주로 반응하며 방향성은 없다. 상기 라디칼은 포토레지스트를 구성하는 주요 원소인 C와 반응하여 CO(일산화탄소)이상의 산소비를 가지는 결합체가 되며, 이로 인하여 제 1 포토레지스트(13)가 식각된다.The plasma process is performed by adding one or more of N 2, HBr, and CF 4 as an additive gas to the gas containing O 2 or the gas containing O 2. The O 2 gas is decomposed and generated in the plasma state into ions and radicals, and in general, the number of radicals is 103 or more than the number of ions, and the radicals mainly react with the first photoresist 13 and have no aromaticity. The radical reacts with C, which is a main element constituting the photoresist, to form a binder having an oxygen ratio of more than CO (carbon monoxide), thereby etching the first photoresist 13.

상기한 바와 같이 O2가스에 N2, HBr 및 CF4등과 같은 다른 가스를 첨가하는 이유는, O2만으로 플라즈마 처리를 할 경우 제 1 포토레지스트(13)의 식각율이 너무 높아 조절이 용이하지 않으므로 재현성이 감소되기 때문에 안정적인 식각율(예를 들어 0.1㎛/min)을 확보하고 그 식각율을 용이하게 조절하기 위해서이다. 예를 들어 다른 공정 조건은 고정시키고 가스비를 조절하면, O2와 첨가가스(예를 들어 N2)의 비가 10:1일 경우 측면 식각율은 약 0.5㎛/min, 1:1일 경우에는 약 0.1㎛/min, 1:10일 경우에는 약 0.02㎛/min의 측면 식각율을 가지게 된다. 상기 플라즈마 공정에서 소오스 전력이 증가하면 라디칼이 많이 발생될 뿐만 아니라, 챔버내의 공정 진행 압력이 증가하여도 O2 라디칼의 양이 증가하므로, 제 1 포토레지스트 패턴(13)의 식각율을 조절할 수 있다. 또한 플라즈마 처리시간을 조절함으로써 제 1 포토레지스트 패턴(13)의 식각정도를 조절할 수 있다.As described above, the reason for adding other gases such as N2, HBr, CF4, etc. to the O2 gas is that when the plasma treatment is performed only with O2, the etching rate of the first photoresist 13 is too high, and thus the reproducibility is reduced. In order to secure a stable etching rate (for example 0.1㎛ / min) and to easily control the etching rate. For example, if other process conditions are fixed and the gas ratio is adjusted, the side etch rate is about 0.5 μm / min when the ratio of O 2 to the additive gas (eg N 2) is 10: 1, and about 0.1 μm when the ratio is 1: 1. / min, 1:10 has a side etch rate of about 0.02㎛ / min. When the source power increases in the plasma process, not only a lot of radicals are generated, but also the amount of O 2 radicals increases even when the process pressure in the chamber increases, so that the etching rate of the first photoresist pattern 13 may be controlled. In addition, the degree of etching of the first photoresist pattern 13 may be adjusted by adjusting the plasma treatment time.

도 2c를 참조하면, 건식식각을 하여 도전층 패턴(120)을 형성한다.Referring to FIG. 2C, the conductive layer pattern 120 is formed by dry etching.

상기한 본 발명의 실시예에 의하면, 플라즈마 공정시 O2에 대한 첨가가스 비의 변경, 소스전력 및 공정진행 압력 등을 변경함으로써 제 1 포토레지스트(13)의식각율을 조절하고, 플라즈마 처리시간을 조절함으로써 제 1 포토레지스트 패턴(13)의 식각정도를 조절함으로써 포토레지스트 패턴의 폭을 조절할 수 있다.According to the above-described embodiment of the present invention, the etching rate of the first photoresist 13 is adjusted by adjusting the ratio of additive gas to O 2, the source power, and the process running pressure during the plasma process, and the plasma treatment time is controlled. As a result, the width of the photoresist pattern may be adjusted by adjusting the etching degree of the first photoresist pattern 13.

상술한 바와 같이, 본 발명은 포토레지스트의 미세 패턴을 양호하게 실현할 수 있으며, 이로 인하여 노광 공정의 재작업을 하지 않아도 되므로 공정시간 및 제작비용을 절감할 수 있으며, 수율을 향상시킬 수 있다.As described above, the present invention can satisfactorily realize the fine pattern of the photoresist, thereby eliminating the need for rework of the exposure process, thereby reducing the processing time and manufacturing cost, and improving the yield.

Claims (6)

반도체 소자를 형성하기 위한 여러 요소가 형성된 기판상에 도전층을 형성하는 단계;Forming a conductive layer on a substrate on which various elements for forming a semiconductor device are formed; 상기 도전층상에 제 1 포토레지스트 패턴을 형성하는 단계; 및Forming a first photoresist pattern on the conductive layer; And 플라즈마 공정으로 상기 제 1 포토레지스트 패턴을 측면 식각하여 원하는 선폭을 갖는 제 2 포토레지스트 패턴을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.Forming a second photoresist pattern having a desired line width by laterally etching the first photoresist pattern by a plasma process. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 공정은 O2가 함유된 가스를 이용하는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.The plasma process is a method for adjusting the line width of the photoresist pattern for manufacturing a semiconductor device, characterized in that using a gas containing O2. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 공정은 O2가 함유된 가스에 첨가가스로 N2, HBr 및 CF4중에서 하나이상을 첨가하여 이용하며 그 비에 의하여 식각율을 조절하는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.The plasma process is a method for adjusting the line width of the photoresist pattern for manufacturing a semiconductor device, characterized in that by using at least one of N2, HBr and CF4 as an additive gas to the gas containing O2 and controlling the etching rate by the ratio. 제 1 항에 있어서,The method of claim 1, 상기 제 2 포토레지스트 패턴은 상기 플라즈마 공정의 처리시간에 따라 상기 제 2 포토레지스트 패턴의 선폭이 조절되는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.The second photoresist pattern is a line width control method of the semiconductor device manufacturing photoresist pattern, characterized in that the line width of the second photoresist pattern is adjusted according to the processing time of the plasma process. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 공정시 챔버내의 공정진행 압력을 조절하여 상기 제 1 포토레지스트 패턴의 식각율을 조절하는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.And controlling the etching rate of the first photoresist pattern by controlling a process progress pressure in the chamber during the plasma process. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 공정시 소스 전력을 조절하여 상기 제 1 포토레지스트 패턴의 식각율을 조절하는 것을 특징으로 하는 반도체 소자 제조용 포토레지스트 패턴의 선폭 조절방법.And controlling the etch rate of the first photoresist pattern by controlling source power during the plasma process.
KR1019990061802A 1999-12-24 1999-12-24 A method of controlling a width of photoresist pattern for manufacturing a semiconductor device KR20010063725A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2012057967A2 (en) * 2010-10-27 2012-05-03 Applied Materials, Inc. Methods and apparatus for controlling photoresist line width roughness

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JPS6424422A (en) * 1987-07-20 1989-01-26 Sanyo Electric Co Formation of fine pattern
JPH06310420A (en) * 1993-04-26 1994-11-04 Nippon Telegr & Teleph Corp <Ntt> Pattern formation
JPH07130631A (en) * 1993-11-05 1995-05-19 Sanyo Electric Co Ltd Pattern formation and manufacture of semiconductor storage device utilizing same
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JPS6424422A (en) * 1987-07-20 1989-01-26 Sanyo Electric Co Formation of fine pattern
JPH06310420A (en) * 1993-04-26 1994-11-04 Nippon Telegr & Teleph Corp <Ntt> Pattern formation
JPH07130631A (en) * 1993-11-05 1995-05-19 Sanyo Electric Co Ltd Pattern formation and manufacture of semiconductor storage device utilizing same
KR19990054904A (en) * 1997-12-26 1999-07-15 김영환 Fine photoresist pattern formation method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012057967A2 (en) * 2010-10-27 2012-05-03 Applied Materials, Inc. Methods and apparatus for controlling photoresist line width roughness
WO2012057967A3 (en) * 2010-10-27 2012-06-21 Applied Materials, Inc. Methods and apparatus for controlling photoresist line width roughness
US9039910B2 (en) 2010-10-27 2015-05-26 Applied Materials, Inc. Methods and apparatus for controlling photoresist line width roughness

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