KR20010063514A - Method for forming metal line in semiconductor device - Google Patents
Method for forming metal line in semiconductor device Download PDFInfo
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- KR20010063514A KR20010063514A KR1019990060627A KR19990060627A KR20010063514A KR 20010063514 A KR20010063514 A KR 20010063514A KR 1019990060627 A KR1019990060627 A KR 1019990060627A KR 19990060627 A KR19990060627 A KR 19990060627A KR 20010063514 A KR20010063514 A KR 20010063514A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring.
잘 알려진 바와 같이 반도체소자 제조 공정중 실리콘기판의 접합(junction) 상에 텅스텐 또는 알루미늄 등의 금속층을 콘택할 경우 접합의 저항값을 낮추고 보호하기 위하여 베리어메탈(barrier metal)로서 Ti/TiN을 증착하고 후속 열처리 공정을 실시하고 있다.As is well known, when contacting a metal layer such as tungsten or aluminum on a junction of a silicon substrate during a semiconductor device manufacturing process, Ti / TiN is deposited as a barrier metal to lower and protect the resistance of the junction. A subsequent heat treatment step is carried out.
베리어메탈은 접합 내의 실리콘 원자와 금속내의 원자가 상호 확산되는 것을 방지하는 역할을 한다는 의미에서 확산방지막이라고도 부른다.Barrier metal is also called a diffusion barrier in the sense that it serves to prevent the diffusion of silicon atoms in the junction and atoms in the metal.
이와 같이 실리콘층(접합) 상에 Ti/TiN을 증착하고 열처리하면 콘택 계면에서 Ti와 Si의 반응이 일어나 비저항값이 13∼20uΩcm 정도로서 비교적 낮은 TiSi2C49상이나 C54상이 형성되고, 또한 콘택계면에 존재하는 왜곡된 격자구조의 결함(defect)이 힐링(heeling)되는 긍정적인 효과를 얻을 수 있다.As such, when Ti / TiN is deposited and heat treated on the silicon layer (bonded), reaction between Ti and Si occurs at the contact interface to form a relatively low TiSi 2 C49 phase or C54 phase with a resistivity of about 13 to 20 uΩcm, and also exist at the contact interface. The positive effect that the defect of the distorted lattice structure is healed can be obtained.
한편, 콘택부에 산소(O2) 또는 불소(F) 등의 불순물이 존재할 경우 높은 콘택저항값의 원인이 될 수 있다. 현재 DRAM 양산에 적용되고 있는 금속배선 공정은 베리어메탈 증착후 열처리를 하기 위하여 대기노출이 불가피하며, 베리어메탈 표면에서의 자연산화 현상이 발생하게 된다. 따라서 베리어메탈 상에 금속층을 증착할 경우 베리어메탈 표면에서 발생된 산화막이 접합의 콘택 저항에 악영향을 주게 되고 또한 소자의 특성에까지 부정적 요인으로 작용할 가능성이 많다.On the other hand, the presence of impurities such as oxygen (O 2 ) or fluorine (F) in the contact portion may cause a high contact resistance value. At present, the metallization process applied to DRAM mass production is inevitable in the air exposure for heat treatment after deposition of barrier metal, and natural oxidation occurs on the surface of barrier metal. Therefore, in the case of depositing a metal layer on the barrier metal, the oxide film generated on the barrier metal surface adversely affects the contact resistance of the junction and may also negatively affect the characteristics of the device.
이러한 가능성은 실제로 소자 제조 공정이 끝난 후 전기적 특성을 테스트하는 작업(EPM : Electrical Parameter Monitoring)에서 나타나기도 한다.This possibility is often seen in the testing of electrical characteristics (EPM) after the device fabrication process is over.
도1은 보통 테스트 조건 즉 전압을 3.3V 인가해 주었을 경우 콘택에서의 체인(chain) 저항이 마치 절연막으로 차단되어 있는 것처럼 높게 나오다가 전압을 5.0V로 높여주면 갑자기 저항값이 떨어지는 현상이 발생하는 것을 보여주는 것으로서, 이와 같은 현상을 보면 콘택홀(Si/Ti/TiN)에서 산화막이 존재하는 것으로 보이며, 일련의 금속배선 공정에서 산화막이 존재할 수 있는 공정은 베리어메탈 증착이 끝난후 대기에 노출되고 상압에서 질소분위기의 열처리공정뿐이다.Figure 1 shows that when the test condition is applied, that is, when the voltage is applied to 3.3V, the chain resistance at the contact is high as if it is cut off with an insulating film, and then the resistance value suddenly drops when the voltage is increased to 5.0V. As a result, it is seen that an oxide film exists in the contact hole (Si / Ti / TiN), and a process in which an oxide film may exist in a series of metallization processes is exposed to the atmosphere after the barrier metal deposition is completed, and is subjected to atmospheric pressure. Is the only heat treatment process in nitrogen atmosphere.
한편, 이상과 같은 문제점을 해결하기 위하여 베리어메탈이 대기중에 노출되지 않도록 하면서 열처리를 실시해야 하는데, 즉 베리어메탈 증착 후 진공파괴없이 열처리를 해야하는데 이러한 장비는 아직까지 없으며 실질적으로 소자의 양산을 고려하면 실효성이 거의 없다.On the other hand, in order to solve the above problems, the heat treatment must be performed while the barrier metal is not exposed to the air. That is, the heat treatment must be performed without vacuum destruction after the deposition of the barrier metal. Such equipment is not yet available and practically considering mass production of devices. There is little effectiveness.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 베리어메탈 증착 후 진공 파괴 상태에서 열처리가 이루어지더라도 이에 의해 발생되는 베리어메탈 표면의 산화물을 손쉽게 제거하여 주므로써, 금속의 콘택 저항값을 낮추어 소자의 특성 저하를 방지할 수 있는 반도체소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art as described above, even if the heat treatment is performed in a vacuum fracture state after the barrier metal deposition, by easily removing the oxide on the surface of the barrier metal generated thereby, the contact of the metal SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of lowering a resistance value to prevent deterioration of device characteristics.
도1은 테스트 전압을 3.3V 인가해 주었을 경우 콘택에서의 체인(chain) 저항이 마치 절연막으로 차단되어 있는 것처럼 높게 나오다가 전압을 5.0V로 높여주면 갑자기 저항값이 떨어지는 현상이 발생하는 것을 보여주는 도면.1 is a diagram showing that when the test voltage is applied to 3.3V, the chain resistance at the contact is as high as if it is cut off by an insulating film, and then the resistance value suddenly drops when the voltage is increased to 5.0V. .
도2는 배선용 금속의 증착 장비 구성을 개략적으로 도시한 도면.Fig. 2 is a diagram schematically showing the construction of a deposition equipment for metal for wiring.
상기 목적을 달성하기 위한 본 발명의 금속배선 형성 방법은, 반도체층 상에 베리어메탈을 증착하고 열처리하는 제1단계; 불활성가스의 플라즈마 처리에 의해 상기 베리어메탈 표면을 식각하는 제2단계; 및 상기 제2단계 수행 후 진공파괴없이 상기 베리어메탈 상에 금속막을 증착하는 제3단계를 포함하여 이루어지는 것을 특징으로 한다.Metal wire forming method of the present invention for achieving the above object, the first step of depositing and heat-treating the barrier metal on the semiconductor layer; Etching the barrier metal surface by plasma treatment of an inert gas; And a third step of depositing a metal film on the barrier metal after the second step is performed without vacuum destruction.
이와 같이 본 발명은 베리어메탈 증착 및 열처리 공정에서 발생하는 것으로추정되는 산화물을 배선용 또는 플러그용 금속막을 증착하기전에 예컨대 아르곤이나 질소와 같은 불활성 가스의 처리에 의해 제거하고, 진공파괴없이 금속막을 증착하여 금속배선의 콘택 저항을 개선하는 것이다.As described above, the present invention removes an oxide, which is estimated to occur in the barrier metal deposition and heat treatment process, by treatment of an inert gas such as argon or nitrogen before depositing a metal film for wiring or plug, and deposits a metal film without vacuum destruction. To improve the contact resistance of the metal wiring.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2는 배선용 금속의 증착 장비 구성을 개략적으로 도시한 것으로서, 통상의 텅스텐 증착 장비를 나타낸 것이다.Figure 2 schematically shows the configuration of the deposition equipment of the metal for wiring, showing a conventional tungsten deposition equipment.
도2를 참조하면, 텅스텐 증착 장비는 웨이퍼 로딩 및 언로딩시 웨이퍼 냉각을 위하여 제1 및 제2 냉각챔버(201, 202)를 구비하고, 증착이 이루어지는 제1 및 제2 증착챔버(203, 204)를 구비하며, RF(Radio Frequency) 또는 DC(Direct Current) 식각용 챔버(205)를 구비하고 있다. 그리고 각 챔버간의 웨이퍼 이송시 진공 파괴가 일어나지 않도록 트랜스퍼 챔버(206)를 구비한다.Referring to FIG. 2, the tungsten deposition apparatus includes first and second cooling chambers 201 and 202 for wafer cooling during wafer loading and unloading, and first and second deposition chambers 203 and 204 where deposition is performed. ) And a chamber (205) for RF (Radio Frequency) or DC (Direct Current) etching. The transfer chamber 206 is provided to prevent vacuum breakage during wafer transfer between the chambers.
상술한 바와 같이 금속 증착 장비에 RF(Radio Frequency) 또는 DC(Direct Current) 식각용 챔버가 구비되어 있으므로, 본 발명은 배선용 또는 콘택 플러그(Plug)용 금속, 즉 텅스텐을 증착하기전에 TiN 표면에 발생된 산화물을 상기 RF 또는 DC 식각용 챔버에서 불활성가스 플라즈마로 제거하고, 이어서 진공 파괴 없이 금속(텅스텐)을 증착하는 것이다.As described above, since the metal deposition apparatus is provided with a chamber for etching an RF or a direct current, the present invention may occur on the TiN surface before depositing a metal for wiring or contact plug, that is, tungsten. The oxide is removed with an inert gas plasma in the RF or DC etching chamber, and then metal (tungsten) is deposited without vacuum breaking.
그러면 금속배선을 형성하기 위한 전반적인 공정 흐름을 살펴본다.Then look at the overall process flow for forming metallization.
먼저, 실리콘층이 일부 노출되도록 콘택홀을 형성한 다음, 베리어메탈로서 Ti/TiN을 증착한다. 상기 Ti의 두께는 100∼700Å, TiN의 두께는 50∼1000Å로 증착한다.First, contact holes are formed to partially expose the silicon layer, and then Ti / TiN is deposited as a barrier metal. The Ti is deposited at 100 to 700 GPa and the TiN is 50 to 1000 GPa.
여기서 TiN의 증착은 물리적증착(PVD) 또는 화학적증착(CVD) 등 여러가지 방법이 있을 수 있으나, 현재 박막의 특성을 고려하여 ∼700℃ 온도 및 ∼10-2Torr 압력하에서 유기금속화학증착법(MOCVD)을 사용하고 있으며, MOCVD TiN의 비저항을 개선하기 위하여 증착 후 진공파괴없이 수소(H2) 또는/및 질소(N2) 분위기에서 플라즈마 처리해주는 방법이 사용되고 있다.Here, the deposition of TiN may be a variety of methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), but in consideration of the characteristics of the current thin film, metal organic chemical vapor deposition (MOCVD) at -700 ℃ temperature and -10 -2 Torr pressure In order to improve the resistivity of MOCVD TiN, a method of plasma treatment in hydrogen (H 2 ) and / or nitrogen (N 2 ) atmosphere without vacuum destruction after deposition is used.
이어서, 앞선 종래기술에서도 언급한 바와 같이 열처리를 수행하는 바, 열처리를 위해서는 TiN 증착후 진공이 파괴되므로 TiN 표면에는 산화물이 발생하게 된다. 열처리는 급속열처리(RTP) 또는 퍼니스 어닐( Furnace Anneal)을 적용할 수 있으며, 질소분위기에서 ∼800℃ 및 ∼20분의 조건으로 실시한다.Subsequently, as mentioned in the prior art, heat treatment is performed, and since the vacuum is destroyed after the deposition of TiN for heat treatment, oxides are generated on the TiN surface. The heat treatment can be applied by rapid heat treatment (RTP) or furnace anneal (furnace anneal), and is carried out under nitrogen atmosphere at -800 ° C and -20 minutes.
이어서, 열처리가 완료된 웨이퍼를 도에 도시한 구성을 갖는 금속 증착 장비로 옮겨 RF 또는 DC 식각용 챔버에서 예컨대 아르곤(Ar) 또는 질소(N2) 가스와 같은 불활성가스의 플라즈마를 사용하여 산화물을 제거한다.Subsequently, the heat-treated wafer is transferred to a metal deposition apparatus having the configuration shown in the figure to remove oxides using a plasma of an inert gas such as argon (Ar) or nitrogen (N 2 ) gas, for example, in an RF or DC etching chamber. do.
아르곤 또는 질소 이온들은 50∼500W 정도의 RF 또는 DC 파워가 인가된 웨이퍼 척(Check) 방향으로 직진성을 가지면서 활성화되므로 이온 충격(bombardment)에 의해 TiN 표면을 ∼100Å 식각처리하고 이에 의해 산화물이 제거된다.Since argon or nitrogen ions are activated in a straight line toward the wafer chuck applied with RF or DC power of about 50 to 500 W, the TiN surface is etched at ~ 100 에 by ion bombardment, thereby removing oxides. do.
이때 RF 또는 DC 식각용 챔버 내의 압력은 ∼10-3Torr가 되도록 하여 실리콘층(접합)에 데미지(damage)를 주지 않도록 하는 것이 바람직하다.At this time, the pressure in the RF or DC etching chamber is preferably -10 -3 Torr so as not to damage the silicon layer (bonding).
또한 더욱 효과적인 식각을 위하여 챔버 벽(wall)에 RF 코일(coil)을 추가하여 주므로써, 즉 챔버벽에서 RF를 인가하여 주므로써 플라즈마 밀도를 높이고 균일하게 할 수 있다.In addition, by adding an RF coil to the chamber wall for more efficient etching, that is, by applying RF at the chamber wall, the plasma density can be increased and made uniform.
이후 진공파괴가 일어나지 않도록 트랜스퍼 챔버(206)를 경유하여 제1 또는 제2 증착챔버(203, 204)에서 텅스텐 증착을 행한다.Thereafter, tungsten deposition is performed in the first or second deposition chambers 203 and 204 via the transfer chamber 206 so that vacuum breakage does not occur.
본 실시예는 텅스텐이 배선용 금속으로 적용된 공정을 예로써 설명된 것으로, 금속은 Al, Au, Cu, At 등이 모두 적용될 수 있다. 또한 Ti/TiN 이외의 물질을 베리어메탈로 사용하는 경우에도 본 발명은 적용될 수 있다.The present embodiment has been described as an example in which tungsten is applied as a wiring metal, and the metal may be Al, Au, Cu, At, or the like. In addition, the present invention can be applied even when using a material other than Ti / TiN as a barrier metal.
이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
반도체소자 제조공정에서 별도의 추가비용이 소요되지 않는 조건으로 베리어메탈 표면의 산화물을 제거하여 주므로써, 추가 비용의 부담 없이 콘택 저항값을 낮추어 소자특성에서 RC 지연 시간을 줄일 수 있고, 소자동작에 있어 신뢰성을 높일 수 있다.By removing oxide on the surface of barrier metal in the semiconductor device manufacturing process without additional cost, RC delay time can be reduced in device characteristics by lowering contact resistance without additional cost. Can increase the reliability.
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| KR100591717B1 (en) * | 2000-04-11 | 2006-06-22 | 삼성전자주식회사 | Metal layer formation method of a semiconductor device |
| KR101113327B1 (en) * | 2009-12-29 | 2012-03-13 | 주식회사 하이닉스반도체 | Semiconductor device having through via and method of fabricating the same |
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| KR100591717B1 (en) * | 2000-04-11 | 2006-06-22 | 삼성전자주식회사 | Metal layer formation method of a semiconductor device |
| KR101113327B1 (en) * | 2009-12-29 | 2012-03-13 | 주식회사 하이닉스반도체 | Semiconductor device having through via and method of fabricating the same |
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