JPH09199586A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent undesirable oxidation and excessive overetching of the surface of substratum conductive material, by forming a protective layer in a thermal CVD process, and controlling the internal temperature of the thermal CVD equipment to be a temperature lower than or equal to a specified value when a substrate to be treated is carried in the thermal CVD equipment. SOLUTION: A plurality of substrates to be treated are mounted on a wafer board 15 of a low pressure CVD equipment, and inert gas like N2 is introduced into a bell-jar 16 while being purged. The temperature inside the bell-jar 16 is controlled to be 600 deg.C or lower. Thereby a thick natural oxide film can be prevented from being formed on the surface of a high melting point metal silicide layer, when atmosphere is somewhat introduced inevitably into the bell-jar 16 at the time of carrying-in. As a result, a manufacturing method excellent in throughput can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a process capable of highly reliably realizing an interlayer connection structure in a multilayer wiring.

[0002]

2. Description of the Related Art With the progress of higher integration and higher performance of semiconductor devices such as LSI, design rules for gate electrodes, wirings, etc. in MIS transistors are being reduced to quarter micron or smaller. . In such a highly integrated semiconductor device, ingenuity in layout is also adopted in the interlayer connection structure in the multilayer wiring in order to reduce the required area.

As an example thereof, SRAM (Static)
Shared Contact (Shared Contact) in Random Access Memory
t) A structure is mentioned. This will be described with reference to FIG. Each memory cell of SRAM constitutes a flip-flop circuit by a pair of driver transistor, access transistor and load transistor.
Of these transistors, the gate electrode of one driver transistor may be connected to the drain region of the other driver transistor by a shared contact structure. FIG. 3 is a schematic sectional view of this shared contact structure. A refractory metal polycide layer composed of a polycrystalline silicon layer 4 and a refractory metal silicide layer 5 is formed on the lower insulating film 3 on the semiconductor substrate 1,
This refractory metal polycide layer constitutes the gate electrode of one driver transistor and the wiring extending from this gate electrode. A flattened interlayer insulating film 6 is formed so as to cover the semiconductor substrate 1 and the refractory metal silicide layer 5, and the shared contact 7 that faces the impurity diffusion layer 2 and the refractory metal silicide layer 5 formed on the semiconductor substrate 1 together. Is opened. The impurity diffusion layer 2 corresponds to the drain region of the other driver transistor. A second-layer polycrystalline silicon layer 9 is formed in the shared contact 7 and on the interlayer insulating film 6, and the refractory metal silicide layer 5 forming the gate electrode / wiring of one driver transistor and the other driver. One shared contact 7 is commonly connected to the impurity diffusion layer 2 that forms the drain region of the transistor.

Since it is desired to form the surface of the interlayer insulating film 6 flat, a reflow glass film made of PSG or the like or a coating insulating film of SOG or the like is used for at least a part thereof. As is well known, these material layers do not have sufficient moisture resistance, and there is a high possibility that moisture or the like will penetrate and contact resistance will increase. Therefore, a structure in which a side wall protective layer 8 is formed on the side wall of the interlayer insulating film 6 exposed in the shared contact 7 to block the influence of moisture is adopted.

[0005]

The side wall protective layer of the shared contact is made of silicon nitride having a high moisture barrier property.
An inorganic insulating film such as silicon oxide or silicon oxynitride is used, and a thermal CVD method such as low pressure CVD that can achieve both dense film quality and conformality is applied as a method of forming the inorganic insulating film.

An example of the structure of this low pressure CVD apparatus is shown in FIG. FIG. 1 is a schematic sectional view of a general batch type vertical low pressure CVD apparatus. The bell jar 16 made of quartz or the like is heated by a heater 17 surrounding the bell jar 16, for example, 700 ° C.
The film formation temperature is kept at about 800 ° C. A plurality of (for example, 60) unillustrated substrates to be processed are also placed on the wafer boat 15 such as quartz, and are carried in and out from the lower open end of the bell jar 16.

Next, a step of forming a side wall protective layer on a substrate to be processed having a shared contact structure by using the low pressure CVD apparatus shown in FIG. 5 is shown in FIGS. 6 (a) to 6 (c) and 7 (d). This will be described with reference to (e). The processed substrate having the shared contact structure shown in FIG.
3 shows a state at an intermediate stage of forming the structure described above with reference to FIG. 3, and the same components as those in FIG. 3 are designated by the same reference numerals,
The overlapping description will be omitted. When carrying the wafer boat with the substrate to be processed into the bell jar,
The inert gas such as N ₂ is carried into the bell jar while being purged. At this time, the ambient air is slightly caught in the bell jar and comes into contact with the surface of the substrate to be processed carried into the bell jar. To do. At this time, the inside of the bell jar is, for example, 760 ° C.
6B, a thick natural oxide film 5a is formed on the surface of the refractory metal silicide layer 5 that is most easily oxidized in the conductive material layer exposed in the shared contact 7 as shown in FIG. 6B. It is formed undesirably.

From this state, the protective film 10 such as silicon nitride is formed.
FIG. 6C shows a state in which is formed conformally by the thermal CVD method, that is, a shape that reflects the stepped shape of the base material layer.
It is. FIG. 7D shows the just-etched state in which the entire surface is etched back from this state and removed from the surface of the impurity diffusion layer 2. In this state, the sidewall protection layer 8 is left in a desired shape on the sidewall of the interlayer insulating film 6. However, the natural oxide film 5 is formed on the refractory metal silicide layer 5.
a is still formed. Therefore, in order to obtain a good ohmic contact between the refractory metal silicide layer 5 and the second-layer polycrystalline silicon layer, it is necessary to further carry out overetching to remove the natural oxide film 5a.

FIG. 5 is a graph showing the relationship between the amount of overetching and the yield of shared contacts. The horizontal axis shows the over-etching amount (%), and the vertical axis shows the ratio of 3000 contact chains within a predetermined contact resistance value, that is, the yield. Curve B in the figure is the case of the conventional example in which the natural oxide film 5a is formed. As is clear from this figure, in order to achieve a contact resistance value within a predetermined range of almost 100%, it is necessary to perform overetching for 100% or more for a long time. However, in the shared contact that has undergone such excessive over-etching, the sidewall protection layer 8 is partly or wholly etched off and disappears as shown in FIG. Therefore, it becomes impossible to achieve the intended function as the moisture resistant protective layer. Further, there is a high possibility that a damage layer (not shown) is formed in the impurity diffusion layer 2 during the overetching process.

An object of the present invention is to solve the above-mentioned problems of the prior art. That is, an object of the present invention is to prevent damage due to undesired oxidation or excessive overetching of the surface of the underlying conductive material layer when forming the sidewall protective layer on the sidewall of the contact hole including the shared contact, and to prevent moisture resistance and the like. An object of the present invention is to provide a method for manufacturing a semiconductor device having excellent reliability.

[0011]

The present invention was created to achieve the above-mentioned objects. That is, the method of manufacturing a semiconductor device of the present invention includes a step of forming an interlayer insulating film on a conductive material layer on a substrate to be processed, a step of opening a connection hole facing the conductive material layer in the interlayer insulating film, A step of conformally forming a protective layer on the film and inside the contact hole; a step of etching back the protective layer and removing it from at least the conductive material layer, and forming a side wall protective layer remaining on the side wall of the contact hole; In the method for manufacturing a semiconductor device, the protective layer forming step is a thermal CVD step using a thermal CVD apparatus, and the internal temperature of the thermal CVD apparatus is controlled when the substrate to be processed is loaded into the thermal CVD apparatus. 600 ° C
It is characterized by the following control.

In one embodiment of the present invention, it can be particularly preferably applied when the conductive material layer includes at least a refractory metal silicide layer such as WSi ₂ , MoSi ₂ or TiSi ₂ . Further, the protective layer employed in the present invention is preferably made of at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride layer on which a dense film is formed by thermal CVD such as low pressure CVD. .

Next, the operation will be described. The gist of the present invention is that the conventional constant thermal CVD temperature, for example, 700 ° C. to 800 ° C.
The point is to control the temperature inside the bell jar 16 of the thermal CVD apparatus, which was constantly maintained at a high temperature of ℃ to 600 ℃ or less only when the substrate to be processed is loaded. This eliminates the possibility that a natural oxide film will be formed on the surface of the conductive material layer, such as the refractory metal silicide layer, which is easily oxidized even when the atmosphere is caught in the bell jar 16 at the time of loading. The lower limit of the temperature inside the bell jar 16 at the time of loading is not particularly limited, but the heat C
Considering the heating time for raising the temperature to the VD temperature, lowering the temperature inside the belger 16 to an unnecessarily low temperature causes a decrease in throughput. Further, if the temperature rising cycle up to the thermal CVD temperature capable of forming a dense protective film by cooling to an unnecessarily low temperature is repeated, the protective film material deposited in the bell jar 16 may be peeled off to deteriorate the particle level. There is Therefore, the temperature inside the bell jar 16 is, for example, 400
When the temperature is set to be not lower than 600 ° C. and not higher than 600 ° C., it is possible to obtain a manufacturing method with high throughput without generation of a natural oxide film.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 This embodiment is an example in which the present invention is applied to the shared contact between the gate electrode / wiring of one driver transistor of the SRAM and the drain region of the other driver transistor, which is shown in FIG. a) to (c) and FIG.
This will be described with reference to (d) to (e). The same components as those in FIGS. 6 to 7 referred to in the description of the conventional example are designated by the same reference numerals, and overlapping description will be omitted.

As shown in FIG. 1A, a refractory metal polycide composed of a polycrystalline silicon layer 4 and a refractory metal silicide layer 5 is formed on a lower insulating film 3 on a semiconductor substrate 1 made of silicon or the like as a substrate to be processed. A layer is formed, and the refractory metal polycide layer constitutes the gate electrode of one driver transistor and a wiring extending from this gate electrode. The lower insulating film 3 may be an element isolation region formed by a selective oxidation method or the like. The impurity diffusion layer 2 and the refractory metal silicide layer formed on the semiconductor substrate 1 are formed by covering the semiconductor substrate 1 and the refractory metal silicide layer 5 with the interlayer insulating film 6 such as PSG planarized by reflow heat treatment or the like. A shared contact 7 facing each other is opened. The impurity diffusion layer 2 corresponds to the drain region of the other driver transistor. The steps up to this point can be formed according to a conventional method.

The next step is the step that occupies the main part of this embodiment. A plurality of substrates to be processed having the shared contact shown in FIG. 1A are placed on the wafer boat 15 of the low pressure CVD apparatus shown in FIG. 4 and purged with an inert gas such as N _2. Carry it into Luja 16. At this time, the temperature inside the bell jar 16 was controlled to 500 ° C. For this reason,
Even if some air was inevitably caught in the bell jar 16 during the loading, a thick natural oxide film was not formed on the surface of the refractory metal silicide layer 5.

After the wafer boat 15 is carried in and the bell jar 16 becomes airtight, the bell jar 16 is purged with an inert gas such as N ₂ or Ar or is evacuated to a high vacuum with a vacuum pump (not shown). The internal temperature of 16 is increased to a film forming temperature of 760 ° C. After this, the following low pressure CVD
Depending on the conditions, a dense protective layer made of Si ₃ N ₄ may be formed,
It is formed to a thickness of 0 nm. Low-pressure CVD condition for protective layer SiH ₂ Cl ₂ flow rate 70 sccm NH ₃ flow rate 700 sccm Gas pressure 73 Pa Processed substrate temperature 760 ° C. The protective layer 10 reflects the shape of the shared contact 7 as shown in FIG. Formed conformally.

Next, the substrate to be processed having the protective layer 10 formed thereon is conveyed to, for example, a parallel plate type RIE apparatus, and the protective layer 10 is etched under the following etch back conditions to form the side wall protective layer 8. CF ₄ flow rate 20 sccm Ar flow rate 400 sccm Gas pressure 20 Pa RF power 150 W Substrate temperature 20 ° C. The relationship between the overetching amount and the yield of contact chains under this etchback condition is shown in the curve A shown in FIG. Show. The definition of contact chain yield is as described above in the description of the conventional example. As is clear from the figure, almost 1 when the overetching amount exceeds 20%.
A yield of 00% is obtained. In this example, 30% over-etching was performed.

As a result, a side wall protective layer 8 is formed on the side surface of the shared contact 7 as shown in FIG.
It was possible to remove the protective layer 10 from the surfaces of the impurity diffusion layer 2 and the refractory metal silicide layer 5 which are conductive material layers. Further, no damaged portion was formed in the impurity diffusion layer 2.

According to the present embodiment, the shared contact structure is adopted, and even when the protective layer is formed by thermal CVD on the substrate to be processed in which the conductive material layer which is easily oxidized is exposed, the natural oxide film is formed on the surface of the conductive material layer. Is not formed thick. Therefore, it is not necessary to perform excessive over-etching in the etch back for forming the sidewall protection layer, and a semiconductor device having excellent moisture resistance can be manufactured with good controllability. The manufacturing process of the sidewall protective layer of this embodiment can be similarly applied to a structure in which the polycrystalline silicon layer 4 extends directly on the surface of the impurity diffusion layer 2, that is, a shared direct contact structure.

Embodiment 2 The present invention is not limited to shared contacts and can be applied to general connection hole structures. As an example thereof, there is a case where a via hole is formed in an interlayer insulating film having a laminated structure in which a step is formed by the lower layer wiring and a flattening interlayer insulating film such as SOG is formed to absorb the step. This will be described with reference to the schematic sectional view shown in FIG.

On the lower insulating film 3, a lower wiring layer of a polycide structure composed of a polycrystalline silicon layer 4 and a refractory metal silicide layer 5 is formed, which causes a step. Next, the lower interlayer insulating film 11, S is formed by low pressure CVD or the like.
A flattened interlayer insulating film 12 is formed by coating and firing OG (Spin on glass), and an upper interlayer insulating film 13 is sequentially formed by low pressure CVD or the like to form a laminated interlayer insulating film having a flat surface. In this laminated interlayer insulating film,
When the via hole 14 facing the lower layer wiring is opened, the side surface of the planarizing interlayer insulating film 12 is exposed on the side wall thereof.

Although a coating insulating film such as SOG or polyimide has excellent flatness, it has a problem in moisture resistance, and if the via plug is buried as it is, there is a concern that the contact resistance may be deteriorated by the poisoned via. Therefore, also in such a structure, a protective layer (not shown) such as Si ₃ N ₄ is formed on the entire surface, and the sidewall protective layer 8 is formed by etchback. At this time, if the protective layer is formed by thermal CVD with a good film quality, a thick natural oxide film may be formed on the surface of the refractory metal silicide layer 5 that is easily oxidized.

Therefore, also in this embodiment, when the substrate to be processed is loaded into a thermal CVD apparatus such as low pressure CVD, the temperature inside the chamber is controlled to 600 ° C. or lower, and then the low pressure CVD is performed.
By raising the temperature, it is possible to avoid such inconvenience. The low pressure CVD condition and the etch back condition may be the same as in the first embodiment.

Although the present invention has been described in detail with reference to the two examples, the present invention is not limited to these examples.

For example, the impurity diffusion layer formed on the semiconductor substrate as the conductive material layer or the refractory metal polycide layer in which the polycrystalline silicon and the refractory metal silicide layer are laminated has been exemplified. The effect can be achieved by applying it to a conductive material layer such as a refractory metal or a copper-based metal in which a natural oxide film is easily formed.

Although silicon nitride is used as an example of the protective layer, silicon oxide, silicon oxynitride or the like, which can obtain a dense film quality by thermal CVD, may be optionally used.

Further, when the substrates to be processed are carried into a thermal CVD device such as low pressure CVD, when the batches are piled up, the film deposited on the inner wall of the device may peel off and adhere to the substrate to be processed. In this case, before carrying in, chamber cleaning may be performed by in-situ gas etching with a fluorine-based gas such as NF ₃ , ClF ₃ or C ₂ F ₆ . By adding such a step, particle contamination can be avoided, and the substrate to be processed can be carried into the thermal CVD apparatus at a lower temperature, so that the effect of avoiding the formation of a natural oxide film on the conductive material layer is thoroughly achieved.

[0030]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, in forming the side wall protective layer on the side wall of the connection hole by the thermal CVD method for the purpose of improving moisture resistance, etc. Undesired oxidation of the surface of the underlying conductive material layer can be prevented. Therefore, excessive over-etching is not necessary, and it is possible to prevent disappearance of the sidewall protective layer due to etch-off and damage to the conductive material layer such as the impurity diffusion layer. The present invention is particularly effective when used for forming a shared contact structure of SRAM.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a first embodiment to which the present invention is applied in the order of steps, in which (a) is a state in which a shared contact is opened, (b) is a state in which a protective layer is formed on the entire surface, c) shows the state that the side wall protective layer is formed by etching back the protective layer.

FIG. 2 is a schematic cross-sectional view showing a via hole shape of Example 2 to which the present invention is applied.

FIG. 3 is a schematic cross-sectional view showing a shared contact structure.

FIG. 4 is a schematic cross-sectional view showing a configuration example of a vertical decompression CVD apparatus as an example of a thermal CVD apparatus.

FIG. 5 is a graph showing the amount of overetching and the yield of contact chains when a sidewall protective layer is formed by etchback in a shared contact structure, where A is the present invention and B is a conventional example.

6A and 6B are schematic cross-sectional views illustrating the first half of the steps of the conventional example in the order of the steps, where FIG. 6A is a state in which a shared contact is opened, and FIG. 6B is a refractory metal silicide when being carried into a thermal CVD apparatus. An undesired natural oxide film is formed thick on the layer, and (c) a protective layer is formed on the entire surface.

6A and 6B are schematic cross-sectional views illustrating the latter half of the steps of the conventional example in the order of the steps. FIG. 6D is a state in which the sidewall protective layer is formed by etching back the protective layer, and FIG. This is a state in which a part of the side wall protective layer has disappeared.

[Explanation of symbols]

 1 semiconductor substrate 2 impurity diffusion layer 3 lower insulating layer 4 polycrystalline silicon layer 5 refractory metal silicide layer 5a natural oxide film 6 interlayer insulating film 7 shared contact 8 sidewall protective layer 9 second layer polycrystalline silicon layer 10 protective layer 11 lower layer Interlayer insulating film 12 Flattening interlayer insulating film 13 Upper interlayer insulating film 14 Via hole 15, 15 'Wafer boat 16 Belleger 17 Heater

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/31 H01L 21/90 C 21/95

Claims (3)

[Claims] 1. A step of forming an interlayer insulating film on a conductive material layer on a substrate to be processed, a step of opening a connection hole facing the conductive material layer in the interlayer insulating film, the interlayer insulating film and the connection. A step of conformally forming a protective layer inside the hole, a step of etching back the protective layer to remove it from at least the conductive material layer, and a sidewall protective layer remaining on the sidewall of the connection hole. A method of manufacturing a semiconductor device, wherein the protective layer forming step is a thermal CVD step using a thermal CVD apparatus, and when the substrate to be processed is carried into the thermal CVD apparatus, an internal temperature of the thermal CVD apparatus is set. Is controlled to be 600 ° C. or lower. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material layer includes at least a refractory metal silicide layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the protective layer is made of at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.