KR20010061048A - A method of fabricating semiconductor device for removing defect caused by plasma etch - Google Patents
A method of fabricating semiconductor device for removing defect caused by plasma etch Download PDFInfo
- Publication number
- KR20010061048A KR20010061048A KR1019990063526A KR19990063526A KR20010061048A KR 20010061048 A KR20010061048 A KR 20010061048A KR 1019990063526 A KR1019990063526 A KR 1019990063526A KR 19990063526 A KR19990063526 A KR 19990063526A KR 20010061048 A KR20010061048 A KR 20010061048A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- mixed solution
- etching
- silicon substrate
- silicon layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조를 위한 플라즈마 식각시 발생한 결함을 제거하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a technique for removing defects generated during plasma etching for semiconductor device manufacturing.
반도체 소자 제조시 각 층의 패터닝을 위하여 수많은 플라즈마 식각을 수행하고 있다. 이러한 플라즈마 식각을 실시하는 경우 식각 대상층에 어느 정도의 손상을 입히는 것은 피할 수 없다. 특히, 실리콘 기판에 대해 플라즈마 식각을 수행하는 경우에는 실리콘 격자 구조의 변형을 가져와 반도체 소자가 제조된 후 결함으로 작용하여 소자의 신뢰도를 저하시키는 문제점이 있다.Numerous plasma etching is performed for patterning each layer in semiconductor device manufacturing. When the plasma etching is performed, some damage to the etching target layer is unavoidable. In particular, in the case of performing plasma etching on the silicon substrate, there is a problem in that the silicon lattice structure is deformed to act as a defect after the semiconductor device is manufactured, thereby lowering the reliability of the device.
한편, 트렌치 소자분리(shallow trench isolation, STI) 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인과, 버즈비크에 따른 활성 영역의 감소와 같은 문제점을 근본적으로 해결할 수 있는 소자분리 공정으로 부각되고 있으며, 1G DRAM 또는 4G DRAM급 이상의 초고집적 반도체 소자 제조 공정에의 적용이 유망하다.On the other hand, the trench trench isolation (STI) process has problems such as instability of the process such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device, and problems such as the reduction of the active region due to the Burj bek. It is emerging as a device isolation process that can fundamentally solve the problem, and it is promising to be applied to an ultra-high density semiconductor device manufacturing process of 1G DRAM or 4G DRAM level or higher.
종래의 STI 공정은 실리콘 기판 상에 패드 산화막 및 질화막을 형성하고, 이를 선택 식각하여 트렌치 마스크를 형성한 다음, 패터닝된 질화막을 식각 마스크로 사용하여 실리콘 기판을 건식 식각함으로써 트렌치를 형성하고, 계속하여 일련의 트렌치 측벽 희생산화 공정(건식 식각에 의한 실리콘 표면의 식각 결함의 제거 목적) 및 트렌치 측벽 재산화 공정을 실시한 후, 트렌치 매립용 산화막을 증착하여트렌치를 매립하고, 화학·기계적 연마(chemical mechanical polishing, CMP) 공정을 실시한 다음, 질화막 및 패드 산화막을 제거하여 소자분리막을 형성하게 된다.A conventional STI process forms a pad oxide film and a nitride film on a silicon substrate, selectively etches to form a trench mask, and then forms a trench by dry etching the silicon substrate using the patterned nitride film as an etch mask, and subsequently After performing a series of trench sidewall sacrificial oxidation processes (to remove etching defects on the surface of silicon by dry etching) and trench sidewall reoxidation processes, an oxide film for filling trenches is deposited to fill the trench, and the chemical and mechanical polishing is performed. After the polishing (CMP) process, the nitride and pad oxide layers are removed to form an isolation layer.
상기의 공정 중 트렌치 형성을 위하여 실리콘 기판의 플라즈마 식각을 실시하는데, 이때 트렌치 영역의 실리콘 기판 표면 부분에 결함이 발생하게 된다. 이러한 결함은 후속 열공정시 실리콘 기판 내부로 확산되어 디펙트 사이트(defect site)로 작용하게 되며, 반도체 소자의 수명을 감소시키는 요인이 되고 있다.Plasma etching of the silicon substrate is performed to form trenches in the above process, in which defects are generated in the silicon substrate surface portion of the trench region. These defects are diffused into the silicon substrate during the subsequent thermal process to act as a defect site, reducing the life of the semiconductor device.
첨부된 도면 도 1a는 실리콘 기판(10) 상에 패터닝된 패드 산화막(11) 및 질화막(12)를 식각 마스크로 하는 플라즈마 식각을 통해 트렌치가 형성된 상태를 도시한 것으로, 트렌치 영역의 실리콘 기판(10) 표면 부분에 플라즈마 손상에 의한 결함층(A)이 형성된 상태를 나타내고 있다.1A illustrates a state in which trenches are formed through plasma etching using the pad oxide film 11 and the nitride film 12 as an etching mask on the silicon substrate 10, and the silicon substrate 10 in the trench region. The state where the defect layer A by plasma damage was formed in the surface part is shown.
다음으로, 첨부된 도면 도 1b는 트렌치 식각 공정의 후속 공정인 희생 산화 공정을 진행한 상태를 도시한 것으로, 열공정을 거치면서 결함층(A)이 실리콘 기판(10) 내부로 확산된 상태를 나타내고 있다. 이 경우, 희생 산화막(13)을 습식 제거하더라도 결함층(A)은 여전히 잔류하게 된다.Next, FIG. 1B illustrates a state in which a sacrificial oxidation process, which is a subsequent process of the trench etching process, is performed, and the defect layer A is diffused into the silicon substrate 10 through a thermal process. It is shown. In this case, even when the sacrificial oxide film 13 is wet removed, the defect layer A still remains.
본 발명은 플라즈마 식각에 의해 실리콘층 표면에 발생한 결함층을 제거할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of removing a defect layer generated on a surface of a silicon layer by plasma etching.
도 1a는 실리콘 기판 상에 트렌치가 형성된 상태의 단면도.1A is a cross-sectional view of a trench formed on a silicon substrate.
도 1b는 트렌치 식각 공정의 후속 공정인 희생 산화 공정을 진행한 상태의 단면도.1B is a cross-sectional view illustrating a sacrificial oxidation process that is a subsequent process of the trench etching process.
도 2는 세정액에 따른 열파(thermal wave) 측정 결과를 나타낸 그래프.Figure 2 is a graph showing the thermal wave (thermal wave) measurement results according to the cleaning liquid.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판10: silicon substrate
11 : 패드 산화막11: pad oxide film
12 : 질화막12: nitride film
13 : 희생 산화막13: sacrificial oxide film
A : 결함층A: defective layer
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자 제조방법은, 실리콘층을 플라즈마 식각하는 제1 단계와, 암모니아(NH4OH), 과산화수소(H2O2) 및 순수(H2O)의 혼합용액을 사용하여 노출된 상기 실리콘층의 표면 일부를 식각하는 제2 단계를 포함하여 이루어진다.The characteristic semiconductor device manufacturing method of the present invention for solving the above technical problem, the first step of plasma etching the silicon layer, ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and pure water (H 2 O A second step of etching a part of the surface of the exposed silicon layer using a mixed solution).
또한, 본 발명은, 실리콘층을 플라즈마 식각하는 제1 단계와, 불산과 질산을 1 : 50∼100 비율로 포함하는 혼합용액을 사용하여 노출된 상기 실리콘층의 표면 일부를 식각하는 제2 단계를 포함하는 것을 특징으로 한다.In addition, the present invention, the first step of plasma etching the silicon layer and the second step of etching a portion of the surface of the exposed silicon layer using a mixed solution containing hydrofluoric acid and nitric acid in a ratio of 1: 50 to 100. It is characterized by including.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
본 발명의 일 실시예는 상기의 기술적 원리를 STI 공정에 적용한 것으로, 이하 이를 설명한다.One embodiment of the present invention is to apply the above technical principle to the STI process, it will be described below.
본 실시예에 따른 STI 공정은, 우선 실리콘 기판 상에 패드 산화막 및 질화막을 형성하고, 이를 선택 식각하여 트렌치 마스크를 형성한 다음, 패터닝된 질화막을 식각 마스크로 사용하여 실리콘 기판을 플라즈마 식각함으로써 트렌치를 형성한다. 이때, 트렌치 영역의 실리콘 기판 표면 부분에 수십Å 깊이에 이르는 결함층이 형성된다.In the STI process according to the present embodiment, a trench is formed by first forming a pad oxide film and a nitride film on a silicon substrate, and selectively etching the trench to form a trench mask, and then plasma etching the silicon substrate using the patterned nitride film as an etching mask. Form. At this time, a defect layer reaching a depth of several tens of micrometers is formed in the silicon substrate surface portion of the trench region.
계속하여, 암모니아(NH4OH), 과산화수소(H2O2) 및 순수(DI water)의 혼합용액을 사용하여 노출된 실리콘 기판(트렌치 영역)을 수십Å 정도 식각한다. 이때, NH4OH : H2O2: DI의 비는 X : 1 : 5 (X = 1∼3)로 하는 것이 바람직하다. 또한, 혼합용액의 온도는 50∼90℃가 적당하며, 식각시간은 결함층의 깊이에 의존하나 보통 5분 이상이면 충분하다.Subsequently, the exposed silicon substrate (trench region) is etched for several tens of microseconds using a mixed solution of ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and pure water (DI water). At this time, the ratio of NH 4 OH: H 2 O 2 : DI is preferably set to X: 1: 5 (X = 1 to 3). In addition, the temperature of the mixed solution is suitable 50 ~ 90 ℃, the etching time depends on the depth of the defect layer, but usually 5 minutes or more is sufficient.
이어서, 트렌치 매립용 산화막을 증착하여 트렌치를 매립하고, 화학·기계적 연마(chemical mechanical polishing, CMP) 공정을 실시한 다음, 질화막 및 패드 산화막을 제거하여 트렌치형 소자분리막 형성 공정을 완료한다.Subsequently, a trench buried oxide film is deposited to fill the trench, a chemical mechanical polishing (CMP) process is performed, and the nitride film and the pad oxide film are removed to complete the trench type isolation film forming process.
상기와 같이 트렌치 식각 직후에 암모니아(NH4OH)와 과산화수소(H2O2) 및 순수(DI water)의 혼합용액을 사용하여 노출된 실리콘 기판(트렌치 영역)을 10∼100Å 정도 식각하는 공정을 추가하게 되면 실리콘 기판 표면 부분의 결함층을 완전히 제거할 수 있다. 또한, 이와 같이 결함층이 제거된 상태이므로 기존의 희생 산화 공정 및 희생 산화막 제거 공정은 실시하지 않아도 된다.Immediately after the trench is etched, the exposed silicon substrate (trench region) is etched by using a mixed solution of ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and pure water (DI water) as described above. The addition can completely eliminate the defect layer on the surface of the silicon substrate. In addition, since the defect layer is removed in this manner, the existing sacrificial oxidation process and the sacrificial oxide film removing process may not be performed.
첨부된 도면 도 2는 세정액에 따른 열파(thermal wave) 측정 결과를 나타낸 그래프로서, 각각의 케이스(case)에 대해 세정전과 세정후의 열파 측정 결과를 나타내고 있다. 참고적으로, 열파값(TW)은 단위가 없는 값이며, 그 값이 낮을 수록 결함이 적다는 것을 의미한다.2 is a graph showing a measurement result of the thermal wave according to the cleaning liquid, and shows the results of the measurement of the thermal wave before and after the cleaning for each case. For reference, the heat wave value TW is a unitless value, and a lower value means less defects.
이 중에서 Bare는 베어 웨이퍼(bare wafer) 상태의 TW값을 나타낸 것이며, Bare+N은 베어 웨이퍼에 대해 NH4OH:H2O2:DI = 1:1:5인 혼합용액을 사용한 세정을 실시한 경우를 나타낸 것이다.Among them, Bare shows the TW value of the bare wafer state, and Bare + N shows the bare wafer cleaning using a mixed solution of NH 4 OH: H 2 O 2 : DI = 1: 1: 5. The case is shown.
이하의 경우는 모두 플라즈마 식각을 실시하여 트렌치가 형성된 기판에 대한 데이터이다. 우선, PF(50s)N(10m)은 황산(H2SO4):과산화수소(H2O2) = 3:1인 혼합용액을 사용한 세정과, 불산(HF):DI = 1:50 용액을 사용한 세정(50초)과, NH4OH:H2O2:DI = 1:1:5인 혼합용액을 사용한 세정(10분)을 연속적으로 실시한 경우를 나타낸 것이다. 한편, PF(100s)N(10m)은 바로 위의 조건에서 불산(HF):DI = 1:50 용액을 불산(HF):DI = 1:50 용액으로 바꾸어 세정(100초)한 경우이며, PF(100s)N(7m)은 바로 위의 조건에서 NH4OH:H2O2:DI = 1:1:5인 혼합용액을 사용한 세정시간을 7분으로 바꾼 경우를 나타낸 것이다. 또한, N(10m), N(7m), N(5m), N(2m)는 각각 NH4OH:H2O2:DI = 1:1:5인 혼합용액만을 사용한 세정시 세정시간을 각각 10분, 7분, 5분, 2분으로 설정한 경우를 나타낸 것이며, P는 황산(H2SO4):과산화수소(H2O2) = 3:1인 혼합용액을 사용한 세정만을 실시한 경우를 나타낸 것이며, F(50s) 및 F(100s)는 각각 불산(HF):DI = 1:50 용액과 염산(HCl) 용액의 혼합용액 및 불산(HF):DI = 1:50 용액을 사용한 세정(100초)을 실시한 경우를 각각 나타낸 것이다.All of the following cases are data on a substrate on which trenches are formed by performing plasma etching. First, PF (50s) N (10m) was washed with a mixed solution of sulfuric acid (H 2 SO 4 ): hydrogen peroxide (H 2 O 2 ) = 3: 1, and hydrofluoric acid (HF): DI = 1:50 solution. 5 shows a mixed cleaning solution (10 minutes) with the case successively subjected to: use the cleaning (50 seconds) and, NH 4 OH: H 2 O 2: DI = 1: 1. On the other hand, PF (100s) N (10m) is a case of cleaning (100 seconds) by replacing the solution of hydrofluoric acid (HF): DI = 1:50 to the solution of hydrofluoric acid (HF): DI = 1:50 under the above conditions, PF (100s) N (7m) shows the case where the cleaning time using the mixed solution of NH 4 OH: H 2 O 2 : DI = 1: 1: 5 was changed to 7 minutes under the above conditions. In addition, N (10m), N (7m), N (5m), and N (2m) respectively indicate the cleaning time at the time of cleaning using only a mixed solution of NH 4 OH: H 2 O 2 : DI = 1: 1: 5, respectively. 10 minutes, 7 minutes, 5 minutes, and 2 minutes, and P is the case where only washing with a mixed solution of sulfuric acid (H 2 SO 4 ): hydrogen peroxide (H 2 O 2 ) = 3: 1 is performed. F (50s) and F (100s) are each washed with a mixed solution of hydrofluoric acid (HF): DI = 1:50 solution and hydrochloric acid (HCl) solution and hydrofluoric acid (HF): DI = 1:50 solution. 100 seconds) is shown respectively.
도면을 참조하면, F(50s), F(100s) 및 P를 적용한 경우에는 세정 전에 비해 결함 제거 효과가 미미함을 알 수 있으며, N(5m) 이상 즉, NH4OH:H2O2:DI = 1:1:5인 혼합용액을 사용하여 5분 이상 세정하는 경우 베어 웨이퍼 상태와 비슷하거나 오히려 낮은 TW값을 나타냄을 확인할 수 있다.Referring to the drawings, it can be seen that when the F (50s), F (100s) and P is applied, the defect removal effect is insignificant compared to before cleaning, N (5m) or more, that is, NH 4 OH: H 2 O 2 : When the cleaning solution was used for more than 5 minutes using a mixed solution of DI = 1: 1: 5, the TW value was similar to or lower than that of the bare wafer.
PF(50s)N(10m), PF(100s)N(10m) 및 PF(100s)N(7m)은 세정 효과가 NH4OH:H2O2:DI = 1:1:5인 혼합용액을 사용한 세정시간에 크게 의존함을 나타내고 있다.PF (50 s) N (10 m), PF (100 s) N (10 m), and PF (100 s) N (7 m) are mixed solutions with a cleaning effect of NH 4 OH: H 2 O 2 : DI = 1: 1: 5. It greatly depends on the washing time used.
본 발명의 다른 실시예는 암모니아(NH4OH)와 과산화수소(H2O2) 및 순수(DI water)의 혼합용액을 사용한 식각 공정을 대신하여 불산과 질산을 1 : 50∼100 비율로 혼합한 혼합용액을 사용하는 것이다. 이 경우, 혼합용액의 온도는 실온으로 하며, 경우에 따라 순수를 혼합하거나 혼합하지 않을 수 있다.Another embodiment of the present invention is a mixture of hydrofluoric acid and nitric acid 1: 1: 50 to 100 in place of the etching process using a mixed solution of ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and pure water (DI water). It is to use a mixed solution. In this case, the temperature of the mixed solution is room temperature, and pure water may or may not be mixed in some cases.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 STI 공정을 일례로 들어 설명하였으나, 본 발명은 실리콘층(폴리실리콘 포함) 플라즈마 식각을 포함하는 거의 모든 공정에 적용될 수 있다.For example, the above-described embodiment has been described using the STI process as an example, but the present invention can be applied to almost all processes including silicon layer (including polysilicon) plasma etching.
전술한 본 발명은 플라즈마 식각에 의한 실리콘층 표면의 결함을 완전히 제거할 수 있는 효과가 있으며, 이로 인하여 반도체 소자의 누설전류 감소, 리프레시 타임의 증가를 기대할 수 있다.The present invention described above has the effect of completely removing the defects on the surface of the silicon layer due to plasma etching, thereby reducing the leakage current of the semiconductor device, it can be expected to increase the refresh time.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063526A KR20010061048A (en) | 1999-12-28 | 1999-12-28 | A method of fabricating semiconductor device for removing defect caused by plasma etch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063526A KR20010061048A (en) | 1999-12-28 | 1999-12-28 | A method of fabricating semiconductor device for removing defect caused by plasma etch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010061048A true KR20010061048A (en) | 2001-07-07 |
Family
ID=19630854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990063526A KR20010061048A (en) | 1999-12-28 | 1999-12-28 | A method of fabricating semiconductor device for removing defect caused by plasma etch |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010061048A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100909136B1 (en) * | 2002-12-24 | 2009-07-23 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
-
1999
- 1999-12-28 KR KR1019990063526A patent/KR20010061048A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100909136B1 (en) * | 2002-12-24 | 2009-07-23 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3802507B2 (en) | Manufacturing method of semiconductor device | |
| JP4347431B2 (en) | Trench element isolation method | |
| US20060141731A1 (en) | Method for forming shallow trench isolation in semiconductor device | |
| JPH11340317A (en) | Formation of isolation structure | |
| US7476622B2 (en) | Method of forming a contact in a semiconductor device | |
| KR100478253B1 (en) | Method of fabricating semiconductor devices | |
| US6716718B2 (en) | Method of producing a semiconductor device | |
| KR0172792B1 (en) | Method of manufacturing isolation for semiconductor device | |
| KR20010061048A (en) | A method of fabricating semiconductor device for removing defect caused by plasma etch | |
| JP2825878B2 (en) | Trench forming method | |
| KR100196420B1 (en) | Method for forimg isolation region in semiconductor device | |
| KR100244299B1 (en) | Isolation region of semiconductor device and method forming the same | |
| KR100515034B1 (en) | A method for fabricating trench isolation | |
| KR100559042B1 (en) | Method of shallow trench isolation film in a semiconductor device | |
| US6245643B1 (en) | Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution | |
| KR20040059445A (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR100446285B1 (en) | Method for forming trench isolation region having round-shaped profile formed at upper corner of trench | |
| KR100470160B1 (en) | Device isolation film formation method of semiconductor device | |
| KR100792709B1 (en) | Manufacturing method for semiconductor device | |
| KR101127033B1 (en) | Semiconductor Device and Method for Forming STI Type Device Isolation Film of Semiconductor Device | |
| KR100241508B1 (en) | Method for manufacturing field oxygen film of semiconductor device | |
| KR20000044658A (en) | Method for forming isolation layer of semiconductor device | |
| KR100800106B1 (en) | Method for forming trench isolation layer in semiconductor device | |
| KR19990055212A (en) | Method of forming device isolation film in semiconductor device | |
| KR19990055199A (en) | Method of forming device isolation film in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |