KR20010059663A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR20010059663A KR20010059663A KR1019990067184A KR19990067184A KR20010059663A KR 20010059663 A KR20010059663 A KR 20010059663A KR 1019990067184 A KR1019990067184 A KR 1019990067184A KR 19990067184 A KR19990067184 A KR 19990067184A KR 20010059663 A KR20010059663 A KR 20010059663A
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- South Korea
- Prior art keywords
- polysilicon
- oxide film
- deposited
- pattern
- metal
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 230000008878 coupling Effects 0.000 claims abstract description 22
- 238000010168 coupling process Methods 0.000 claims abstract description 22
- 238000005859 coupling reaction Methods 0.000 claims abstract description 22
- 238000003860 storage Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000007943 implant Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 230000036039 immunity Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 디램 소자에 파워라인의 사이에 사용되고 있는 커플링 캡(coupling cap.)의 캐패시턴스를 증가시킴에 의해 노이즈의 면역성(noise immunity)을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to improve noise immunity by increasing the capacitance of a coupling cap used between power lines in a semiconductor DRAM device. It relates to a semiconductor device manufacturing method that can improve the reliability of the.
일반적으로 반도체 디램소자에서는 파워라인(Vcc, Vss) 들의 노이즈 면역성을 개선하기 위하여 파워라인인 Vcc 와 Vss 의 라인 사이에 커플링 캡을 사용하고 있다. 그리고 노이즈 면역성을 개선하기 위해서는 커플링 캡의 캐패시턴스를 증가시키거나 파워라인의 저항을 증가 시켜야 한다.In general, the semiconductor DRAM device uses a coupling cap between the lines of power lines Vcc and Vss to improve noise immunity of power lines Vcc and Vss. To improve noise immunity, either increase the capacitance of the coupling cap or increase the resistance of the power line.
그러나 상기 커플링 캡의 캐패시턴스를 증가시키기 위해서는 커플링 캡의 면적을 증가시키는 것이 가장 쉬운 방법이나 칩 사이즈를 증가시키게 되므로 면적을 증가시키는 데에는 한계가 따르는 문제점이 있다.However, in order to increase the capacitance of the coupling cap, it is easy to increase the area of the coupling cap or increase the chip size. Therefore, there is a problem in that there is a limit in increasing the area.
다른 하나의 방법으로는 파워라인의 저항을 증가시키는 방법이 있는데, 이 방법은 소자의 동작에 치명적인 영향을 주기 때문에 실제로 적용하는 데에는 문제점이 있다.Another method is to increase the resistance of the power line, which has a problem in practical application because it has a fatal effect on the operation of the device.
따라서 본 발명은 상기와 같은 종래의 문제점을 해소하기 위해 안출된 것으로서, 본 발명은 좁은 면적에서도 충분한 양의 캐패시턴스를 확보함과 아울러, 칩 사이즈를 증대시키지 않고도 커플링 캡의 캐패시턴스를 증가시킬 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, the present invention can secure a sufficient amount of capacitance even in a small area, and can increase the capacitance of the coupling cap without increasing the chip size It is an object of the present invention to provide a method for manufacturing a semiconductor device.
도 1 내지 도 5 는 본 발명의 방법에 따른 반도체 소자의 제조공정 단계를 도시한 단면도1 to 5 are cross-sectional views showing the manufacturing process steps of the semiconductor device according to the method of the present invention
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체 기판 2 : 웰 정션(well junction)1 semiconductor substrate 2 well junction
3 : 웰 피크 정션(well pick junction) 4 : 게이트 산화막3: well pick junction 4: gate oxide film
5 : 제1 다결정실리콘 6 : 제2 다결정실리콘5: first polycrystalline silicon 6: second polycrystalline silicon
7 : 유전막 8 : 제3 다결정실리콘7: dielectric film 8: third polycrystalline silicon
9 : 제1 평탄화 산화막 10 : 제2 평탄화 산화막9: first planarization oxide film 10: second planarization oxide film
11 : 메탈 콘택홀 11 : 제3 다결정실리콘 연결 메탈11 metal contact hole 11 third polysilicon connection metal
12 : 웰 피크 메탈 13 : 제1 다결정실리콘 연결 메탈12: well peak metal 13: first polycrystalline silicon-linked metal
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은,The semiconductor device manufacturing method of the present invention for achieving the above object,
임플란트 공정으로 반도체 기판상에 웰 정션(2) 및 웰 피크 정션(3)을 형성하는 단계와,Forming a well junction (2) and a well peak junction (3) on a semiconductor substrate by an implant process;
상기 구조의 상부에 게이트 산화막(4)을 형성한 후, 제1 다결정실리콘(5)을 증착한 다음, 상기 게이트 산화막(4)을 이용하여 커플링 캡을 형성하는 단계와,Forming a gate oxide film 4 on the structure, depositing a first polycrystalline silicon 5, and then forming a coupling cap using the gate oxide film 4;
전체구조 상부에 제1 평탄화 산화막(9)을 증착한 후, 식각공정으로 상기 제1 다결정실리콘 패턴(5)의 상부에 콘택을 형성한 다음, 제2 다결정실리콘(6)을 증착하여 저장전극 패턴을 형성한 후, 상기 저장전극 패턴의 상부에 유전막(7)을 증착하는 단계와,After depositing a first planarization oxide layer 9 on the entire structure, a contact is formed on the first polysilicon pattern 5 by an etching process, and then a second polysilicon 6 is deposited to form a storage electrode pattern. Forming a dielectric film 7 on the storage electrode pattern;
제3 다결정실리콘(8)을 증착하여 플레이트 폴리 패턴을 형성하는 단계와'Depositing a third polysilicon 8 to form a plate poly pattern;
전체구조 상부에 제2 평탄화 산화막(9')을 증착한 후, 메탈 콘택(10)을 상기 웰 피크 정션(3)/제1 다결정실리콘(5)/제3 다결정실리콘(8) 영역 상부에 각각 오픈하는 단계와,After depositing the second planarization oxide film 9 'over the entire structure, the metal contacts 10 are respectively formed on the well peak junction 3 / first polysilicon 5 / third polysilicon 8 regions. To open,
상기 각 메탈콘택(10)에 메탈을 증착하여 패턴을 형성하고, 상기 웰 피크 정션(3)과 상기 제3 다결정실리콘(8)에 연결된 메탈(12,11)에 Vss를, 상기 제1 다결정실리콘(5)에 연결된 메탈(13)에 Vcc를 연결하는 단계로 이루어지는 것을 특징으로 한다.A metal is deposited on each of the metal contacts 10 to form a pattern. Vss is applied to the metals 12 and 11 connected to the well peak junction 3 and the third polysilicon 8, and the first polysilicon is formed. It characterized in that the step consisting of connecting the Vcc to the metal 13 connected to (5).
이하 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법의 적합한 실시예에 대해 상세히 설명한다.Hereinafter, a preferred embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5 는 본 발명의 일실시예에 따른 반도체 소자의 제조공정 단계를 도시한 단면도이다.1 to 5 are cross-sectional views showing the manufacturing process steps of the semiconductor device according to an embodiment of the present invention.
먼저, 반도체 기판(1)의 상부에 임플란트 공정을 실시하여 기판내의 소정 영역에 웰 정션(2) 및 웰 피크 정션(3)을 형성한다.(도 1 참조)First, an implant process is performed on the semiconductor substrate 1 to form a well junction 2 and a well peak junction 3 in a predetermined region of the substrate (see FIG. 1).
상기 구조의 상부에 게이트 산화막(4)을 형성한 후, 다시 그 상부에 제1 다결정실리콘(5)을 증착하고, 상기 게이트 산화막(4)을 이용하여 커플링 캡을 형성한다.(도 2 참조)After the gate oxide film 4 is formed on the structure, the first polycrystalline silicon 5 is further deposited on the structure, and the coupling cap is formed using the gate oxide film 4 (see FIG. 2). )
다음, 전체구조 상부에 제1 평탄화 산화막(9)을 증착한 후, 상기 게이트 산화막(4)을 이용한 커플링 캡의 상기 제1 다결정실리콘 패턴(5)의 상부에 콘택을 형성한다. 상기 공정은 소자 셀 지역의 저장전극 콘택을 형성하는 공정과 같다.Next, after the first planarization oxide film 9 is deposited on the entire structure, a contact is formed on the first polycrystalline silicon pattern 5 of the coupling cap using the gate oxide film 4. The process is the same as forming a storage electrode contact in the device cell region.
그리고 전체구조 상부에 제2 다결정실리콘(8)을 증착한 후, 저장전극 패턴을 형성하고, 그 상부에 유전막(7)을 증착한다. 그 후 다시 제3 다결정실리콘(8)을 증착하여 플레이트 폴리 패턴(8)을 형성한다.After depositing the second polysilicon 8 on the entire structure, a storage electrode pattern is formed, and a dielectric film 7 is deposited on the second polycrystalline silicon 8. Thereafter, the third polysilicon 8 is deposited to form a plate poly pattern 8.
이때 상기 게이트 산화막(4)을 이용한 커플링 캡과 셀 캐패시터의 유전막(7)을 이용한 커플링 캡은 병렬로 형성된다.(도 3 참조)At this time, the coupling cap using the gate oxide film 4 and the coupling cap using the dielectric film 7 of the cell capacitor are formed in parallel (see FIG. 3).
전체구조 상부에 제2 평탄화 산화막(9')을 증착한 후, 메탈 콘택(10)을 상기 웰 피크 정션(3)/제1 다결정실리콘(5)/제3 다결정실리콘(8) 영역 상부에 각각 오픈한다.(도 4 참조)After depositing the second planarization oxide film 9 'over the entire structure, the metal contacts 10 are respectively formed on the well peak junction 3 / first polysilicon 5 / third polysilicon 8 regions. Open it (see Figure 4).
다음, 전체구조 상부에 메탈을 증착한 후, 패턴을 형성한다. 그리고 상기 웰 피크 정션(3)에 채워진 메탈인 웰 피크 메탈(12)과 상기 제3 다결정실리콘(8)에 연결된 메탈(11)에 Vss를, 상기 제1 다결정실리콘(5)에 연결된 메탈(13)에 Vcc를 연결한다.Next, a metal is deposited on the entire structure, and then a pattern is formed. In addition, Vss is connected to the well peak metal 12, which is the metal filled in the well peak junction 3, and the metal 11 connected to the third polycrystalline silicon 8, and the metal 13 connected to the first polycrystalline silicon 5. To Vcc.
한편, 상기에서 상기 다결정실리콘을 폴리사이드로 사용하여 커플링 캡을 형성할 수 있으며, 또한 상기 제1 다결정실리콘 패턴에 연결된 메탈(13)에 Vcc 대신Vpp 레벨을 사용할 수 도 있다.(도 5 참조)Meanwhile, the polysilicon may be used as a polyside to form a coupling cap, and a Vpp level may be used instead of Vcc for the metal 13 connected to the first polysilicon pattern. )
상기와 같은 본 발명의 공정으로 총 커플링 캐패시턴스(total coupling capitance)는 종래의 캐패시턴스 C1에 C2 가 병렬로 추가되어 C2 만큼의 캐패시턴스가 추가되게 된다.In the process of the present invention as described above, the total coupling capacitance (total coupling capitance) is C2 is added in parallel to the conventional capacitance C1, so that the capacitance of C2 is added.
이상 상기한 바와 같이, 본 발명은 상기 게이트 산화막을 이용한 커플링 캡과 셀 캐패시터의 유전막을 이용한 커플링 캡을 병렬로 형성시켜 커플링 캡의 캐패시턴스를 증가시킴으로써 소자의 칩 크기를 증가시키지 않고도 충분한 양의 캐패시턴스를 확보함으로써 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention provides a sufficient amount without increasing the chip size of the device by increasing the capacitance of the coupling cap by forming the coupling cap using the gate oxide film and the coupling cap using the dielectric film of the cell capacitor in parallel. The reliability of the device can be improved by securing the capacitance of the device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067184A KR20010059663A (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067184A KR20010059663A (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
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| Publication Number | Publication Date |
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| KR20010059663A true KR20010059663A (en) | 2001-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990067184A KR20010059663A (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602043B2 (en) | 2005-11-03 | 2009-10-13 | Samsung Electronics Co., Ltd. | Coupling capacitor and semiconductor memory device using the same |
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1999
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602043B2 (en) | 2005-11-03 | 2009-10-13 | Samsung Electronics Co., Ltd. | Coupling capacitor and semiconductor memory device using the same |
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