KR20010059168A - A method for manufacturing of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to form an interlayer dielectric layer as a two-layered structure to improve the characteristic of the semiconductor device. CONSTITUTION: At first, a conductive wiring is formed on a semiconductor substrate. Then, a nitride layer is formed up to a predetermined thickness on the overall surface including the conductive wiring. Then, the lower first interlayer dielectric layer is formed on the overall surface. At forth step, the first lower interlayer dielectric layer is etched back to leave only between the conductive wrings with a predetermined thickness. At fifth, the first upper interlayer dielectric layer(9) is accumulated on the overall surface and flattened. Then, a contact hole is formed by using an LPC(landing plug contact) process exposing the semiconductor substrate, the first interlayer dielectric layer is etched with slant by using a dry etching method, the first interlayer dielectric layer is etched by using the wet etching method and the nitride layer on the surface of the semiconductor surface is etched. At last, an LPP(landing plug poly) is coupled with the semiconductor substrate formed.

Description

A method for manufacturing of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in forming a first interlayer insulating film and a landing plug, a lower insulating film and an oxide film having a high etching rate with respect to an oxide film. During the etching process of the landing plug contact (hereinafter referred to as LPC), the LPC DICD is made small by reducing the etching damage of the SAC process by depositing it in a laminated structure of the upper insulating film having a slow etching rate. In addition, the present invention relates to a technique for securing a lower size of a contact hole by etching a lower insulating layer having a high etching selectivity by a wet etching process.

In the prior art, after forming poly1 and poly spacer, a material such as BPSG is deposited with a first interlayer insulating film, and then planarized by CMP to form LPC.

In this process, the LPC etching process is a self-aligned contact (hereinafter referred to as SAC) etching using a poly1 spacer nitride film as a barrier. In the modern process, the selection between the nitride film and the oxide film during the SAC process is performed. Inadequate rain can cause SAC fail.

Here, the SAC fail is when the LPC and the poly1 are shorted. As the LPC profile becomes sloped, the size of the lower part of the LPC is very small.

In addition, the current process does not perform poly1 spacer etching on the cell area, so the LPC etching requires contacting the impurity junction region through the nitride film at the interface with the active region. overetch) and there is a possibility of a lot of SAC failing.

In addition, in the LPC transient etching process, the LPC (landing plug poly) short circuit between the LPC upper CD is also generated a problem occurs.

That is, in the current process, there is a disadvantage in that the lower CD becomes smaller to secure the SAC yield, so that the contact resistance increases greatly, and if the lower LPC lower CD is increased to improve the contact resistance, the SAC fail and the LPP bridge are generated.

The present invention is to solve the above problems of the prior art, by forming an interlayer insulating film of two laminated structure to improve the characteristics of the LPC process and to facilitate the subsequent process of the semiconductor device that can improve the characteristics and reliability of the semiconductor device The purpose is to provide a manufacturing method.

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

1: semiconductor substrate 2: gate electrode

3: poly1 mask oxide film 4: poly1 spacer

5: lower first interlayer insulating film 6: upper first interlayer insulating film

7: photosensitive film pattern 8: first plug poly

9 second interlayer insulating film 10 bit line contact

11 bit line 12 poly2 mask nitride film

13 poly 2 spacer 14 lower third interlayer insulating film

15: upper third interlayer insulating film 16: the second plug poly

17: poly3, storage electrode 30, 40: contact hole

In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,

Forming a conductive wiring on the semiconductor substrate;

Forming a nitride film with a predetermined thickness on the entire surface including the conductive wiring;

Forming a lower first interlayer insulating film over the entire surface;

Etching back the lower first interlayer insulating film to leave only a predetermined thickness between the conductive wirings;

Stacking and planarizing an upper first interlayer insulating film on the entire surface;

Forming a contact hole by an LPC process exposing the semiconductor substrate, etching the first interlayer dielectric layer by a dry method, etching the first interlayer dielectric layer by a wet etching method, and then etching the nitride film on the surface of the semiconductor substrate Fair,

Forming a LPP connected to the semiconductor substrate;

The wet etching process is carried out using HF or BOE solution,

The nitride film etching process may be performed by a dry etching process or a wet etching process using a hot phosphoric acid solution.

On the other hand, the principle of the present invention for achieving the above object,

This is to maximize the CD size of the lower LPC while suppressing the SAC fail and LPP bridge during the LPC etching process. For this purpose, instead of using only one BPSG, the first interlayer insulating material was used simultaneously with the lower BPSG and the upper HDP oxide material, and the two-step etching of dry etching and wet etching was performed. Since the BPSG at the bottom of wet etching is much faster than the HDP oxide layer at the top, the LPS bridge can be suppressed by increasing the LPC upper CD while securing the lower LPC CD. On the other hand, in consideration of the amount of oxide etching in the lateral direction during the wet etching, the etching process is performed by reducing the CD in the LPC mask formation process, thus greatly increasing the probability of inducing SAC fail compared to the case where the LPC mask CD is large. Can be reduced.

In addition, the present invention adds a poly1 spacer nitride film etching process after the wet etching process and the dry etching process during the LPC etching process to minimize the active attack in the etching process and at the same time the transient etching process for the nitride film etching. This can greatly reduce the SAC failure that occurs at the time.

For reference, in the current process, since the nitride film is etched by the oxide film transient etching process without performing the poly1 spacer etching process in the cell area to secure the refresh characteristics, there are many SAC fail and active area attack.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and illustrate a bit line contact process as an example.

First, an isolation layer and a well are formed on the semiconductor substrate 1, and a gate 2 is formed on the semiconductor substrate 1.

At this time, the gate 2 is a deposition of the poly1 spacer (4).

The gate 2 is formed of a poly 1 and tungsten silicide stacked structure, and a poly 1 mask oxide layer 3 is formed on the upper portion of the gate 2 to be used as an etch barrier during the LPC SAC process.

In addition, the poly1 spacer 4 is also formed of a nitride film to serve as an SAC etch barrier, and the poly1 spacer 4 is not etched in the cell region.

Here, when the poly1 spacer 4 is etched in the cell region, the refresh characteristics may be degraded due to the damage of the substrate during the etching process, and the nitride film thickness of the gate sidewall may be reduced, which may cause the SAC fail. (FIG. 1A)

Then, the poly1 spacer 4 of the peripheral circuit portion is etched and the first interlayer insulating film 5 is deposited on the entire surface.

In this case, the first interlayer insulating layer 5 is formed of a material such as boro phospho silicate glass (PSP), phospho silicate glass (PSG), etc., which has a high etching selectivity with respect to an oxide film. (FIG. 1B)

Next, the first interlayer insulating film 5 is etched back.

At this time, if the thickness of the first interlayer insulating film 5 remaining after the etch back process is thick, there is a possibility that the lower interlayer insulating film is isotropically etched during the LPC wet etching process, thereby causing LPP.

Therefore, the first interlayer insulating film 5 remaining after the etch back process is kept as thin as possible so that the slanted etching proceeds during the LPC etching so that the lower interlayer insulating film exists only in the lower portion of the CD.

Through this method, even if the lower etch rate of the lower interlayer insulating film is rapidly etched to widen the CD, the CD of the lower interlayer insulating film portion is smaller than that of the upper interlayer insulating film portion during dry etching, thereby suppressing the LPP bridge generation. (FIG. 1C)

Next, a second interlayer insulating film 6, which is an upper interlayer insulating film, is deposited on the etched back first interlayer insulating film 4, and then planarized through a CMP process.

The upper interlayer insulating film 6 may be formed of HDP (high density plasma), PE-USG (plasma enhanced-undoped silicate glass), and LP-TEOS (low presure-terta). It is formed using ethyl ortho silicate) or HTO (high temperature oxide). (FIG. 1D)

Next, a photosensitive film pattern 7 for etching an LPC contact is formed on the second interlayer insulating film 6. In this case, the photoresist pattern 7 is formed by an exposure and development process using a bit line and a capacitor contact mask.

Then, the SAC process using the photosensitive film pattern 7 as a mask, that is, the LPC process, is performed dry.

At this time, in the LPC etching process, since the difference in etching selectivity between the nitride film and the oxide film is not perfect, the inclined etching is performed so that the lower CD is smaller than the upper CD.

On the other hand, in this process, the LPC mask, i.e., the CD of the photoresist pattern 7, is formed to a size smaller than a normal bit line contact mask.

The reason for this is that isotropic etching proceeds in the wet etching process performed after the dry etching process, and the CD increases in the lateral direction.

Keeping the LPC mask CD small like this greatly reduces the likelihood that a contact overlaps with poly1 in LPC misalignment, thus reducing the likelihood of a SAC fail. (FIG. 1E)

Then, wet etching is performed after the LPC dry etching process.

In this wet etching process, the lower interlayer insulating film 5 having a high etching rate for wet etching is rapidly etched to increase the lower LPC CD, while the upper LPC upper CD is largely made by the upper interlayer insulating film having a slow etching rate for wet etching. It will not increase.

Meanwhile, when the wet etching process is performed for a long time, the lower interlayer insulating film may be etched to cause the LPP bridge in the lower region. (FIG. 1F)

Next, after the wet etching process, the nitride film 4 under the contact region is dry etched to form the contact hole 30.

For reference, in the related art, the LPC etching process is performed in a dry manner, and the nitride film 4 is subjected to excessive etching during the etching process of the interlayer insulating film, which is an oxide film, thereby increasing damage to the semiconductor substrate.

The present invention can minimize the damage of the substrate caused by the transient etching process by adding a separate nitride film etching process without excessive etching, thereby improving the refresh characteristics of the semiconductor device. (Fig. 1g)

Next, the first plug poly 8 filling the contact hole 30 is formed. (FIG. 1H)

The first plug poly 8 is planarized by CMP or etch back. (FIG. 1i)

Next, a second interlayer insulating film 9 is deposited on the first plug poly 8 to insulate the plug poly of the poly 2 and poly 3 nodes, and then a poly 2 contact is formed to form a bit line. (FIG. 1J)

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and show capacitor contacts as an example.

First, as shown in FIG. 1J, the gate 2, the first interlayer dielectric layers 5 and 6, the bit lines, and the like are formed in the semiconductor device, and the lower third interlayer dielectric layer 14 is formed over the entire surface.

The lower third interlayer insulating film 14 is a lower interlayer insulating film of the third interlayer insulating film deposited in two steps, the lower interlayer insulating film and the upper interlayer insulating film. (FIG. 2A)

Next, the lower third interlayer insulating film 14 is etched back. At this time, the thickness of the lower third interlayer insulating film 14 remaining after the etch back process is as low as possible. (FIG. 2B)

Then, an upper third interlayer dielectric layer 15 is deposited on the etched back lower interlayer dielectric layer 14 and then planarized by a CMP process.

In this case, the lower third interlayer insulating film 14 is formed of an insulating material such as BPSG or PSG, and the upper third interlayer insulating film 15 is formed of HDP, PE-USG, LP-TEOS, and HTO oxide. (FIG. 2C)

Next, a capacitor contact hole 40 exposing the first plug poly 8 is formed by an LPC process using a capacitor contact mask.

Then, the second plug poly 16 for the capacitor filling the contact hole 40 is formed and the storage electrode 17 connected thereto is formed. (FIG. 2D, FIG. 2E, FIG. 2F)

As described above, the method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film having a lower interlayer insulating film made of a material having good wet etching with respect to an oxide film, and forming a material having poor etching as an upper interlayer insulating film. After the formation, the LPC process is performed as a subsequent process, but the dry slope and wet etching processes are sequentially used to reduce the bridge CD of the LPP by reducing the upper CD of the polyglycol poly and increasing the lower CD. To provide. In addition, the nitride film etching process on the surface of the substrate may be performed by adding a separate process without the excessive etching process, thereby minimizing damage to the substrate, thereby improving the refresh characteristics of the semiconductor device.

Claims (8)

Forming a conductive wiring on the semiconductor substrate; Forming a nitride film with a predetermined thickness on the entire surface including the conductive wiring; Forming a lower first interlayer insulating film over the entire surface; Etching back the lower first interlayer insulating film to leave only a predetermined thickness between the conductive wirings; Stacking and planarizing an upper first interlayer insulating film on the entire surface; Forming a contact hole by an LPC process exposing the semiconductor substrate, etching the first interlayer dielectric layer by a dry method, etching the first interlayer dielectric layer by a wet etching method, and then etching the nitride film on the surface of the semiconductor substrate Fair, A method of manufacturing a semiconductor device comprising the step of forming an LPP connected to the semiconductor substrate. The method of claim 1, And the conductive wiring is a gate or a bit line. The method of claim 1, The nitride film is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of the nitride film and the oxide film. The method of claim 1, The lower first interlayer dielectric layer is formed of an insulating material such as BPSG, PSG, etc., which has a high etching rate with respect to an oxide wet etching solution. The method of claim 1, The upper first interlayer insulating film is a semiconductor device manufacturing method, characterized in that formed of a slow HDP oxide film, PE-USG, PE-USG, PE-TEOS or HTO insulating film for the oxide wet etching solution. The method of claim 1, The LPC process is a semiconductor device manufacturing method characterized in that performed using a mask having a size smaller than the gap between the conductive wiring. The method of claim 1, The wet etching process is characterized in that carried out using HF or BOE solution. The method of claim 1, The nitride film etching process may be performed by a dry etching process or a wet etching process using a hot phosphoric acid solution.