KR20010058689A - Semiconductor pattern capable of measuring a resistance of contact and via holes - Google Patents

Semiconductor pattern capable of measuring a resistance of contact and via holes Download PDF

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Publication number
KR20010058689A
KR20010058689A KR1019990066045A KR19990066045A KR20010058689A KR 20010058689 A KR20010058689 A KR 20010058689A KR 1019990066045 A KR1019990066045 A KR 1019990066045A KR 19990066045 A KR19990066045 A KR 19990066045A KR 20010058689 A KR20010058689 A KR 20010058689A
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pattern
critical dimension
resistance
wafer alignment
contact
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KR1019990066045A
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Korean (ko)
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KR100356758B1 (en
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이경윤
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황인길
아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: A semiconductor pattern is provided to be capable of measuring resistance of a contact and a via hole by integrating a wafer alignment mark and a critical dimension measurement pattern. CONSTITUTION: A semiconductor pattern includes a wafer alignment mark formed for aligning wafers. A critical dimension measurement pattern is formed within the wafer alignment mark and confirms whether a predetermined critical dimension process target value is satisfied. Metal lines(L21,L22) and pad(21,22) are formed to measure the resistance of the contact and the via hole through a metal process after a hole process is performed for the critical dimension measurement pattern.

Description

콘택 및 비아 홀의 저항 측정용 반도체 패턴{SEMICONDUCTOR PATTERN CAPABLE OF MEASURING A RESISTANCE OF CONTACT AND VIA HOLES}Semiconductor pattern for resistance measurement of contacts and via holes {SEMICONDUCTOR PATTERN CAPABLE OF MEASURING A RESISTANCE OF CONTACT AND VIA HOLES}

본 발명은 반도체 제조 공정에서 형성되는 테스트 패턴에 관한 것으로, 더욱 상세하게는 웨이퍼 정렬 마크 및 크리티컬 디멘젼 측정용 테스트 패턴을 하나의 패턴으로 통합하여 콘택 홀(contact hole) 및 비아 홀(via hole)의 저항을 측정할 수 있도록 형성된 반도체 패턴에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern formed in a semiconductor manufacturing process, and more particularly, to integrate a wafer alignment mark and a test pattern for measuring critical dimensions into a single pattern to form contact holes and via holes. The present invention relates to a semiconductor pattern formed to measure resistance.

반도체 웨이퍼 제조 공정은 로트(lot) 단위의 매 반도체 웨이퍼의 표면에 여러 종류의 막을 형성하고, 패턴 마스크를 이용하여 반도체 웨이퍼의 특정 부분을 선택적으로 깎아 내는 작업을 되풀이함으로써 웨이퍼 전면의 각 칩에 동일한 패턴을 갖는 전자회로를 구성해 나가는 과정을 의미한다.In the semiconductor wafer manufacturing process, various kinds of films are formed on the surface of each semiconductor wafer in a lot unit, and a pattern mask is used to selectively scrape a specific portion of the semiconductor wafer, thereby repeating the same process for each chip on the front surface of the wafer. It refers to the process of constructing an electronic circuit having a pattern.

반도체 웨이퍼 가공 과정에서 광 리소그래피 공정(Optical lithography process)은 스텝퍼(Stepper)로부터 평행광을 발생시켜 패턴 마스크에 그려진 회로패턴을 반도체 웨이퍼 표면에 전사해 주는 공정을 말하는 것으로, 이러한 공정을 수회 내지 수십회 반복함으로써 반도체 소자의 회로가 완성된다.An optical lithography process in a semiconductor wafer processing process refers to a process of transferring parallel circuits drawn on a pattern mask onto a surface of a semiconductor wafer by generating parallel light from a stepper. By repeating, the circuit of a semiconductor element is completed.

광 리소그래피 공정에서는 크롬이나 산화철 등의 물질에 의해 투명 또는 불투명 패턴이 형성된 레티클(Reticle) 또는 마스크를 사용한다. 이를 위해서는 웨이퍼 위에 감광막을 얇게 입히고 미리 제작한 레티클을 웨이퍼 위에 올려놓고 빛을 투과시키면, 레티클 패턴에 따라 빛을 받은 부분과 받지 않는 부분이 생기고, 이를 현상액(Developer)으로 처리하면 현상액의 특성에 따라 양성(Positive-type)이면 감광된 부분이, 음성이면 감광되지 않은 부분이 제거된다. 이와 같은 과정으로 레티클의 패턴이 감광막으로 옮겨지면 이를 이용하여 식각이나 불순물 도핑을 선택적으로 할 수 있게 된다.In the photolithography process, a reticle or mask in which a transparent or opaque pattern is formed by a material such as chromium or iron oxide is used. To do this, apply a thin film of photoresist on the wafer, place the pre-made reticle on the wafer, and transmit the light. Then, depending on the reticle pattern, there is a part that receives and does not receive light. If it is positive-type, the photosensitive portion is removed. If it is negative, the photosensitive portion is removed. When the pattern of the reticle is transferred to the photoresist by this process, etching or impurity doping can be selectively used.

도 1은 일반적인 반도체 웨이퍼를 예시적으로 도시한 도면으로서, 웨이퍼(1)는 스크라이브 라인(2)에 의해 격자 형태로 구획되어 각각의 구획된 면에 칩을 형성하기 위한 메인 패턴(3)이 마스크를 통해 형성되고, 스크라이브 라인(2)이 위치한 각각의 메인 패턴(3) 사이에는 도 2a 및 도 2b에 도시된 바와 같은 웨이퍼 정렬 마크(4) 및 크리티컬 디멘젼 측정용 테스트 패턴(5) 등이 위치하게 된다.FIG. 1 is a diagram illustrating a typical semiconductor wafer by way of example, in which the wafer 1 is partitioned by a scribe line 2 into a lattice shape, and a main pattern 3 for forming chips on each partitioned surface is masked. A wafer alignment mark 4 and a test pattern 5 for critical dimension measurement, as shown in FIGS. 2A and 2B, are positioned between each main pattern 3 formed through the scribe line 2. Done.

웨이퍼 정렬 마크(4)는 후속 패턴(Contact & via patterns)과정에서 선행 패턴과의 웨이퍼 정렬을 위해 선행 패턴(Metal patterns)과정에서 형성되고, 크리티컬 디멘젼 측정용 테스트 패턴(5)은 주어진 크리티컬 디멘젼 프로세스 타겟(Critical dimension process target)값의 만족 여부를 확인할 수 있게 한다.The wafer alignment mark 4 is formed in a metal pattern process for wafer alignment with a preceding pattern in a subsequent pattern (Contact & via patterns) process, and the test pattern 5 for measuring a critical dimension is a given critical dimension process. It is possible to check whether the value of the critical dimension process target is satisfied.

이러한 웨이퍼 정렬 마크(4) 및 크리티컬 디멘젼 측정용 테스트 패턴(5)들은 현재 마스크 제작 과정에서 각각 분리되어 그려지고 있는데, 이 경우 마스크 상에 많은 공간을 차지하게 되어 필히 첨가되어야 할 테스트 패턴이 제외되는 경우가 발생되며, 텅스텐 CMP(Chemical and mechanical polishing) 공정시 웨이퍼 정렬 마크(4)의 손상이 심한 문제점이 있다.The wafer alignment marks 4 and the test patterns 5 for the critical dimension measurement are currently drawn separately in the mask fabrication process. In this case, a large amount of space is occupied on the mask to exclude the test patterns that must be added. In some cases, the damage of the wafer alignment mark 4 is severe during the tungsten chemical and mechanical polishing (CMP) process.

그리고, 이러한 반도체 장치 내의 저항 특성은 반도체 장치의 성능을 좌우하는 주요한 파라미터가 되는데, 만일 웨이퍼 정렬 마크 및 디멘젼 측정용 테스트 패턴을 하나의 테스트 패턴에 통합하고, 이 통합된 패턴을 이용하여 콘택 및 비아 홀의 저항을 측정할 수 있게 된다면 그 만큼 마스크를 효율적으로 활용할 수 있게 될것이다.In addition, the resistance characteristics in the semiconductor device become a major parameter that determines the performance of the semiconductor device. If the test pattern for measuring the wafer alignment mark and the dimension measurement is integrated into one test pattern, the integrated pattern is used for contact and vias. If the resistance of the hole can be measured, the mask can be used efficiently.

따라서 본 발명은 상기한 점에 착안하여 안출한 것으로, 웨이퍼 정렬을 위한 얼라인먼트 마크와 크리티컬 디멘젼 측정용 패턴을 통합하여 콘택 및 비아 홀의 저항을 측정할 수 있는 콘택 및 비아 홀 저항 측정이 가능한 반도체 패턴을 제공하는데 그 목적이 있다.Therefore, the present invention has been made in view of the above-mentioned point, and integrates an alignment mark for wafer alignment and a pattern for critical dimension measurement, thereby providing a semiconductor pattern capable of measuring contact and via hole resistance, which can measure resistance of contacts and via holes. The purpose is to provide.

상술한 목적을 달성하기 위한 본 발명은, 콘택 및 비아 홀 저항 측정용 패턴에 있어서, 웨이퍼 정렬을 위해 형성된 웨이퍼 정렬 마크; 상기 웨이퍼 정렬 마크 내에 형성되며, 기설정된 크리티컬 디멘젼 프로세스 타겟(Critical dimension process target)값의 만족 여부를 확인하기 위한 크리티컬 디멘젼 측정용 패턴; 상기 크리티컬 디멘젼 측정용 패턴에 홀(hole) 공정을 수행한 후, 메탈 공정을 통해 상기 콘택 및 비아 홀의 저항을 측정하기 위해 형성된 메탈 라인 및 패드를 포함하여 구성된 콘택 및 비아 홀의 저항 측정용 반도체 패턴을 제공한다.The present invention for achieving the above object, in the pattern for contact and via hole resistance measurement, the wafer alignment mark formed for wafer alignment; A pattern for measuring a critical dimension formed in the wafer alignment mark to check whether a predetermined value of a critical dimension process target is satisfied; After performing a hole process on the pattern for measuring the critical dimension, a semiconductor pattern for resistance measurement of the contact and via holes including metal lines and pads formed to measure the resistance of the contact and via holes through a metal process. to provide.

도 1은 일반적인 반도체 웨이퍼를 개략적으로 도시한 도면,1 schematically illustrates a general semiconductor wafer;

도 2a는 종래의 웨이퍼 정렬용 테스트 패턴을 도시한 도면,Figure 2a is a view showing a conventional test pattern for wafer alignment,

도 2b는 종래의 크리티컬 디멘젼 측정용 테스트 패턴을 도시한 도면,Figure 2b is a view showing a test pattern for a conventional critical dimension measurement,

도 3은 본 발명의 바람직한 실시예에 따라 웨이퍼 정렬 마크와 크리티컬 디멘젼 측정용 패턴이 통합된 마스크의 구조를 도시한 도면,3 is a view showing a structure of a mask incorporating a wafer alignment mark and a pattern for critical dimension measurement according to a preferred embodiment of the present invention;

도 4a는 도 3에 도시된 마스크 패턴을 이용하여 웨이퍼 상에 형성된 각 패턴을 도시한 도면,FIG. 4A illustrates each pattern formed on a wafer using the mask pattern shown in FIG. 3;

도 4b는 본 발명에 따라 콘택 및 비아 홀의 저항 측정을 위해 메탈 라인 및 패드가 형성된 패턴을 도시한 도면.4B illustrates a pattern in which metal lines and pads are formed for measuring resistance of contacts and via holes in accordance with the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

1 : 웨이퍼 2 : 스크라이브 라인1: wafer 2: scribe line

3 : 메인 패턴 10 : 웨이퍼 정렬 마크3: main pattern 10: wafer alignment mark

20 : 크리티컬 디멘젼 측정용 테스트 패턴20: Test pattern for critical dimension measurement

21, 22 : 패드21, 22: pad

이와 같은 본 발명의 특징적인 구성 및 이에 따른 작용 효과는 첨부된 도면을 참조한 실시예의 상세한 설명을 통해 더욱 명확해 질 것이다.Such a characteristic configuration and the effects of the present invention will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings.

도 3은 본 발명의 바람직한 실시예에 따라 웨이퍼 정렬 마크와 크리티컬 디멘젼 측정용 패턴이 통합된 마스크의 구조를 도시한 도면으로서, 웨이퍼 정렬을 위한 마크(10)와, 크리티컬 디멘젼 측정용 테스트 패턴(20)을 포함한다.3 is a view illustrating a structure of a mask in which a wafer alignment mark and a critical dimension measurement pattern are integrated according to a preferred embodiment of the present invention, wherein the mark 10 for wafer alignment and the test pattern 20 for critical dimension measurement are illustrated in FIG. ).

즉, 본 발명에 따른 콘택 및 비아 홀 저항 측정이 가능한 마스크 패턴은 바깥 부분의 웨이퍼 정렬 마크(10) 안쪽에 크리티컬 디멘젼 측정용 테스트 패턴(20)이 삽입된 하나의 패턴 모듈 형태로 이루어진다. 그리고, 그로 인해 정렬 마크(10)와 크리티컬 디멘젼 측정용 테스트 패턴(20)을 각각 분리시켜 그리는 종래와 비교하여 마스크의 활용 공간을 늘릴 수 있으며, 웨이퍼 공정이 이루어진 뒤에는 웨이퍼 정렬 마크(10)와 크리티컬 디멘젼 측정용 테스트 패턴(20)이 웨이퍼 상의 동일 공간 내에 구비되어 다단 형태를 이루게 됨으로써 패턴이 지니는 면적이 늘어나게 되어 텅스텐 CMP 공정시 웨이퍼 정렬 마크(10)가 받게 되는 손상을 줄일 수 있게 된다.That is, the mask pattern capable of measuring the contact and via hole resistance according to the present invention is formed in the form of one pattern module in which the test pattern 20 for measuring the critical dimension is inserted inside the wafer alignment mark 10 of the outer portion. As a result, the utilization space of the mask can be increased in comparison with the conventional drawing by separating the alignment mark 10 and the critical dimension measurement test pattern 20 separately, and after the wafer process is performed, the wafer alignment mark 10 and the critical Since the test pattern 20 for dimension measurement is provided in the same space on the wafer to form a multi-stage shape, the area of the pattern is increased, thereby reducing damage to the wafer alignment mark 10 during the tungsten CMP process.

이때, 웨이퍼 정렬 마크(10)는 후속 패턴(Contact & via patterns)과정에서 선행 패턴과의 웨이퍼 정렬을 위해 선행 패턴(Metal patterns)과정에서 형성되고, 웨이퍼 정렬 마크(10)의 길이, 폭 및 그 사이의 간격은 도시 생략된 스텝퍼 센서 시스템(Stepper sensor system)에서 인식 가능한 범위 내로 정해진다. 또한, 크리티컬 디멘젼 측정용 테스트 패턴(20)은 주어진 크리티컬 디멘젼 프로세스 타겟(Critical dimension process target)값의 만족 여부를 확인할 수 있게 한다.At this time, the wafer alignment mark 10 is formed in a metal pattern process for wafer alignment with the preceding pattern in a subsequent pattern (Contact & via patterns) process, the length, width and The interval between them is set within a range recognizable by a stepper sensor system (not shown). In addition, the test pattern 20 for measuring the critical dimension makes it possible to confirm whether or not a given value of the critical dimension process target is satisfied.

한편, 도 3에 도시된 바와 같이 웨이퍼 정렬 마크(10)와 크리티컬 디멘젼 측정용 테스트 패턴(20)을 하나의 패턴 모듈로 형성된 마스크 패턴을 이용하여 웨이퍼 상에 도 4a에 도시한 바와 같은 패턴이 형성되면, 크리티컬 디멘젼 측정용 테스트 패턴(20)에 홀 공정을 수행한 다음, 메탈 공정을 수행하여 도 4b에 도시된 바와 같은 메탈 라인(L21, L22) 및 패드(21, 22)를 형성하므로써, 콘택 및 비아 홀의 저항을 측정할 수 있도록 한다.Meanwhile, as shown in FIG. 3, a pattern as shown in FIG. 4A is formed on a wafer by using a mask pattern in which the wafer alignment mark 10 and the critical dimension measurement test pattern 20 are formed as one pattern module. When a hole process is performed on the critical dimension measurement test pattern 20 and then a metal process is performed to form the metal lines L21 and L22 and the pads 21 and 22 as shown in FIG. 4B, the contact is performed. And the resistance of the via hole can be measured.

결과적으로, 본 발명에서는 웨이퍼 정렬 마크(10)와 크리티컬 디멘젼 측정용 테스트 패턴(20)이 하나의 패턴으로 구현됨으로써 마스크 제작시 여유 공간을 확보할 수 있게 되고, 패턴 형성이 완료된 다음의 홀 공정 및 메탈 공정을 수행하여 콘택 및 비아 홀의 저항을 측정할 수 있게 된다.As a result, in the present invention, since the wafer alignment mark 10 and the critical dimension measurement test pattern 20 are implemented in one pattern, the free space can be secured during the fabrication of the mask, and the following hole process after the pattern formation is completed and The metal process may be performed to measure the resistance of the contacts and the via holes.

이상 설명한 바와 같이 본 발명에 따르면, 하나의 패턴 모듈에 웨이퍼 정렬 마크와 크리티컬 디멘젼 측정용 테스트 패턴을 모두 구현됨으로써 마스크 제작시 여유 공간을 확보하고 필요한 테스트 패턴을 추가할 수 있게 되며, 콘택 및 비아 홀의 저항을 측정할 수 있게 되므로써, 반도체 장치의 제조 공정중에 반도체 장치의 성능을 테스트할 수 있는 효과가 있다.As described above, according to the present invention, since both the wafer alignment mark and the critical dimension measurement test pattern are implemented in one pattern module, it is possible to secure a free space and add necessary test patterns when manufacturing a mask. Since the resistance can be measured, the performance of the semiconductor device can be tested during the manufacturing process of the semiconductor device.

Claims (2)

콘택 홀(contact) 및 비아 홀(via hole) 저항 측정용 반도체 패턴에 있어서,In the semiconductor pattern for measuring contact hole and via hole resistance, 웨이퍼 정렬을 위해 형성된 웨이퍼 정렬 마크;A wafer alignment mark formed for wafer alignment; 상기 웨이퍼 정렬 마크 내에 형성되며, 기설정된 크리티컬 디멘젼 프로세스 타겟(Critical dimension process target)값의 만족 여부를 확인하기 위한 크리티컬 디멘젼 측정용 패턴;A pattern for measuring a critical dimension formed in the wafer alignment mark to check whether a predetermined value of a critical dimension process target is satisfied; 상기 크리티컬 디멘젼 측정용 패턴에 홀(hole) 공정을 수행한 후, 메탈 공정을 통해 상기 콘택 및 비아 홀의 저항을 측정하기 위해 형성된 메탈 라인 및 패드를 포함하여 구성된 콘택 및 비아 홀의 저항 측정용 반도체 패턴.The semiconductor pattern for resistance measurement of the contact and via holes including a metal line and a pad formed to measure the resistance of the contact and via holes through a metal process after performing a hole process on the critical dimension measurement pattern. 제 1 항에 있어서, 상기 절렬 마크는 사각형으로 형성되며 규칙적인 배열로 형성된 것을 특징으로 하는 콘택 및 비아 홀의 저항 측정용 반도체 패턴.The semiconductor pattern for measuring resistance of contacts and via holes according to claim 1, wherein the cutting marks are formed in a rectangular shape and formed in a regular arrangement.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371147B1 (en) * 2001-03-15 2003-02-06 주식회사 하이닉스반도체 Method for measuring the contact resistance of semiconductor device
KR100436596B1 (en) * 2001-04-10 2004-06-16 (주)유영산업 A manufacturing method of padding for the use of upper
CN113611650A (en) * 2021-03-19 2021-11-05 联芯集成电路制造(厦门)有限公司 Method for aligning wafer pattern

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JP2862798B2 (en) * 1994-08-25 1999-03-03 日鉄セミコンダクター株式会社 Photomask for semiconductor device manufacturing
KR0137621Y1 (en) * 1996-02-27 1999-02-18 곽정소 Chip scent critical dimension mark pattern
KR100261164B1 (en) * 1998-02-25 2000-11-01 김영환 Eguipment for fabricating of semiconductor device
TW447078B (en) * 1998-05-19 2001-07-21 United Microelectronics Corp Monitor pattern of critical dimension control
KR20000026566A (en) * 1998-10-21 2000-05-15 윤종용 Semiconductor device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371147B1 (en) * 2001-03-15 2003-02-06 주식회사 하이닉스반도체 Method for measuring the contact resistance of semiconductor device
KR100436596B1 (en) * 2001-04-10 2004-06-16 (주)유영산업 A manufacturing method of padding for the use of upper
CN113611650A (en) * 2021-03-19 2021-11-05 联芯集成电路制造(厦门)有限公司 Method for aligning wafer pattern
US11692946B2 (en) 2021-03-19 2023-07-04 United Semiconductor (Xiamen) Co., Ltd. Method for aligning to a pattern on a wafer
CN113611650B (en) * 2021-03-19 2024-02-27 联芯集成电路制造(厦门)有限公司 Method for aligning wafer pattern

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