KR20010058448A - Method For Removing The Defect Of Semiconductor Device - Google Patents
Method For Removing The Defect Of Semiconductor Device Download PDFInfo
- Publication number
- KR20010058448A KR20010058448A KR1019990065780A KR19990065780A KR20010058448A KR 20010058448 A KR20010058448 A KR 20010058448A KR 1019990065780 A KR1019990065780 A KR 1019990065780A KR 19990065780 A KR19990065780 A KR 19990065780A KR 20010058448 A KR20010058448 A KR 20010058448A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- metal
- contact
- semiconductor substrate
- etching
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 기판에서 형성된 격자 결함을 해소하는 방법에 관한 것으로서, 특히, 절연막 상에 TiN막과 타타늄막을 적층한 후에 마스킹식각으로 콘택을 형성하여 그 콘택 내부에 메탈2를 매립하여 금속배선을 형성한 후, 질화막을 적층하여 블랭킷식각으로 스페이서를 형성하고, 그 결과물 상에 제1,제2보호막을 적층하여 열처리공정을 진행하면, 보호막내에 함유된 수소기가 반도체기판으로 유입하여 기판에 존재하는 격자 결함을 제거하도록 하는 반도체소자의 격자결함 제거방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of eliminating a lattice defect formed in a semiconductor substrate. In particular, a contact is formed by masking etching after stacking a TiN film and a titanium film on an insulating film to fill metal 2 in the contact to fill a metal wiring. After forming, the nitride film is laminated to form a spacer by blanket etching, and the first and second protective films are laminated on the resultant, and the heat treatment process is performed. Hydrogen groups contained in the protective film flow into the semiconductor substrate and exist in the substrate. The present invention relates to a lattice defect removal method of a semiconductor device for removing a lattice defect.
일반적으로, 반도체기판은 소자분리막 형성시 스트레스와 워드라인과 워드라인 스페이서 식각시에 데미지에 의하여 기판에 격자 결함이 발생되어진다. 이러한 반도체기판의 격자 결함은 전류 누설(Current Leakage)의 원인이 되어 반도체소자의 리프레쉬(Refresh)특성을 저하시키게 된다.In general, a lattice defect is generated in a semiconductor substrate due to stress in forming an isolation layer and damage in etching a word line and a word line spacer. The lattice defects of the semiconductor substrate cause current leakage, thereby lowering the refresh characteristics of the semiconductor device.
도 1은 종래의 반도체소자에서 금속배선이 형성된 상태를 보인 도면으로서, 반도체기판(1)에 소자분리막(2)을 형성한 후, 게이트트전극 및 커패시터를 형성하도록 한다. 그런 후에 계속하여 층간절연막(3)을 적층한다.FIG. 1 is a view showing a state in which a metal wiring is formed in a conventional semiconductor device. After forming an isolation layer 2 on a semiconductor substrate 1, a gate electrode and a capacitor are formed. Thereafter, the interlayer insulating film 3 is laminated.
그리고, 상기 층간절연막(3) 상에 메탈1(4)을 적층한 후에 식각하도록 하고, 그 위에 제1절연막(5)을 적층하도록 한다.Then, the metal 1 4 is laminated on the interlayer insulating film 3 and then etched, and the first insulating film 5 is laminated thereon.
계속하여 상기 제1절연막(5)을 식각으로 콘택을 형성하도록 하고, 그 콘택내부에 메탈2(7)를 매립시킨 후에 식각으로 금속배선을 형성하도록 한다.Subsequently, the first insulating layer 5 is etched to form a contact, and the metal 2 7 is buried in the contact and then metal wiring is formed by etching.
그 다음에 절연막 및 실리콘질화막으로 된 보호막(8)을 적층하여 수소기가 외부로 누출되는 것을 차단하 후에 열처리공정을 진행하여 수소기들이 반도체기판에 도달하여 소자분리막 형성시, 워드라인과 워드라인 스페이서 식각시 데미지 (Damage)에 의하여 발생된 격자 결함을 회복시켜 주게 된다.Then, a protective film 8 made of an insulating film and a silicon nitride film is laminated to block the leakage of hydrogen groups to the outside, and then a heat treatment process is performed so that the hydrogen groups reach the semiconductor substrate to form a device isolation film. It recovers lattice defects caused by damage during etching.
그러나 종래의 금속 배선구조에서는 메탈2 증착시에 콘택 매립 특성을 향상시키기 위하여 티타늄막을 증착한 후에 메탈2를 증착하게 되는 데, 이 때, 증착한 티타늄막은 수소기와 반응이 잘 되므로 수소기가 반도체기판에 도달하기 전에 티타늄막과 반응하여 소모되므로 반도체기판의 격자결함은 반도체 소자의 제조공정이 완료되어도 계속 존재하여 소자의 리프레쉬(Refresh) 특성을 저하시키는 문제를 지닌다.However, in the conventional metal wiring structure, the metal 2 is deposited after the titanium film is deposited to improve the contact buried property during the metal 2 deposition. In this case, since the deposited titanium film reacts well with the hydrogen group, the hydrogen group is deposited on the semiconductor substrate. Since it is consumed by reacting with the titanium film before reaching, the lattice defect of the semiconductor substrate continues to exist even after the manufacturing process of the semiconductor device has a problem of degrading the refresh characteristics of the device.
본 발명은 이러한 점을 가만하여 안출한 것으로서, 절연막 상에 TiN막과 타타늄막을 적층한 후에 마스킹식각으로 콘택을 형성하여 그 콘택 내부에 메탈2를 매립하여 금속배선을 형성한 후, 질화막을 적층하여 블랭킷식각으로 스페이서를 형성하고, 그 결과물 상에 제1,제2보호막을 적층하여 열처리공정을 진행하면, 보호막내에 함유된 수소기가 반도체기판으로 유입하여 기판에 존재하는 격자 결함을 제거하는 것이 목적이다.The present invention has been made in view of this point, and after the TiN film and the titanium film are laminated on the insulating film, a contact is formed by masking etching, metal 2 is embedded in the contact to form metal wiring, and then a nitride film is laminated. When the spacer is formed by blanket etching, and the first and second protective films are laminated on the resultant, and the heat treatment process is performed, the hydrogen group contained in the protective film flows into the semiconductor substrate to remove the lattice defects present in the substrate. Purpose.
도 1은 종래의 반도체소자에서 금속배선이 형성된 상태를 보인 도면이고,1 is a view showing a state in which metal wiring is formed in a conventional semiconductor device,
도 2(a) 내지 도 2(d)는 본 발명의 일실시예에 따른 반도체소자에서 격자결함을 제거하기 위하여 금속배선을 순차적으로 형성하는 상태를 보인 도면으로서,2 (a) to 2 (d) are views illustrating a state in which metal wirings are sequentially formed to remove lattice defects in a semiconductor device according to an embodiment of the present invention.
도 3(a) 내지 도3(c)는 본 발명의 다른 실시예에 따른 반도체소자에서 격자결함을 제거하기 위하여 금속배선을 순차적으로 형성하는 상태를 보인 도면이다.3 (a) to 3 (c) are views illustrating a state in which metal wirings are sequentially formed to remove lattice defects in a semiconductor device according to another exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10,110 : 반도체기판 15,115 : 소자분리막10,110 semiconductor substrate 15,115 device isolation film
20,120 : 층간절연막 25,125 : 메탈120,120: interlayer insulating film 25,125: metal 1
30,130 : 제1절연막 35 : TiN막30,130: first insulating film 35: TiN film
40,140 : 티타늄막 50,150 : 메탈240,140: titanium film 50,150: metal 2
60,160 : 질화막 70,170 : 제1보호막60,160: nitride film 70,170: first protective film
75,175 : 제2보호막75,175: Second protective film
이러한 목적은 소자분리막이 형성된 반도체기판 상에 소정의 소자구조를 형성한 후, 층간절연막을 적층하는 단계와; 상기 층간절연막을 식각하여 콘택을 형성하고 메탈1을 형성하는 단계와; 상기 메탈1 상에 제1절연막을 적층한 후, 식각으로 콘택을 형성하고 , 그 콘택내에 TiN막 및 티타늄막을 순차적으로 적층하는 단계와; 상기 결과물 상에 메탈2를 형성한 후, 질화막을 적층하는 단계와; 상기 질화막을 블랭킷 식각으로 메탈의 양측면에 스페이서를 형성하는 단계와; 상기 결과물 상에 제1,제1보호막를 적층한 후, 열처리공정을 수행하는 단계를 포함하여 이루어진 반도체소자의 격자결함제거방법에 따른 제일실시예를 제공함으로써 달성된다.This object is achieved by forming a predetermined device structure on a semiconductor substrate on which a device isolation film is formed, and then stacking an interlayer insulating film; Etching the interlayer insulating film to form a contact and to form a metal 1; Stacking a first insulating film on the metal 1, forming a contact by etching, and sequentially stacking a TiN film and a titanium film in the contact; Forming a metal 2 on the resultant, and then laminating a nitride film; Forming spacers on both sides of the metal by blanket etching the nitride film; It is achieved by providing a first embodiment according to the lattice defect removal method of a semiconductor device comprising the step of laminating a first, a first protective film on the resultant, and then performing a heat treatment process.
그리고, 본 고안의 목적은, 소자분리막이 형성된 반도체기판 상에 소정의 소자구조를 형성한 후, 층간절연막을 적층하는 단계와; 상기 층간절연막을 식각하여 콘택을 형성하고 메탈1을 형성하는 단계와; 상기 메탈1 상에 제1절연막, 질화박막 및 제2절연막을 적층한 후 콘택을 형성하는 단계와; 상기 콘택 내부에 메탈2를 적층한 후, 감광막을 적층하여 패턴을 형성하는 단계와; 상기 감광막으로 메탈2을 식각한 후, 콘택내에 질화막을 적층하는 단계와; 상기 질화막을 마스킹 식각하여 메탈2의 양측면에 스페이서를 형성하는 단계와; 상기 결과물 상에 제1,제2보호막을 적층하는 단계를 포함하여 이루어진 반도체소자의 격자결함 형성방법의 다른 실시예를 제공함으로써 달성된다.In addition, an object of the present invention, after forming a predetermined device structure on the semiconductor substrate on which the device isolation film is formed, the step of laminating an interlayer insulating film; Etching the interlayer insulating film to form a contact and to form a metal 1; Stacking a first insulating layer, a nitride thin film, and a second insulating layer on the metal 1 and forming a contact; Stacking a metal 2 inside the contact and then laminating a photoresist to form a pattern; Etching the metal 2 with the photosensitive film, and then depositing a nitride film in a contact; Masking and etching the nitride film to form spacers on both sides of the metal 2; It is achieved by providing another embodiment of a method for forming a lattice defect of a semiconductor device comprising the step of laminating a first, a second protective film on the resultant.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(d)는 본 발명의 일실시예에 따른 반도체소자에서 격자결함을 제거하기 위하여 금속배선을 순차적으로 형성하는 상태를 보인 도면이다.2 (a) to 2 (d) are views illustrating a state in which metal wirings are sequentially formed to remove lattice defects in a semiconductor device according to an embodiment of the present invention.
도 2(a)에 도시된 바와 같이, 소자분리막(15)이 형성된 반도체기판(10) 상에 소정의 소자구조를 형성한 후, 층간절연막(20)을 적층하도록 한다.As shown in FIG. 2A, after forming a predetermined device structure on the semiconductor substrate 10 on which the device isolation film 15 is formed, the interlayer insulating film 20 is laminated.
계속하여 상기 층간절연막(20)을 식각하여 콘택을 형성하고 메탈1(25)을 형성하도록 한다.Subsequently, the interlayer insulating layer 20 is etched to form a contact and to form the metal 1 25.
그리고, 상기 메탈1(25) 상에 제1절연막(30)을 적층한 후, 식각으로 콘택을 형성하고 , 그 콘택내에 TiN막(35) 및 티타늄막(40)을 순차적으로 적층하도록 한다.After the first insulating film 30 is stacked on the metal 1 25, a contact is formed by etching, and the TiN film 35 and the titanium film 40 are sequentially stacked in the contact.
그 다음에 상기 결과물 상에 메탈2(50)를 감광막(55)으로 식각한 후, 박막의 질화막(60)을 적층하도록 한다.Next, the metal 2 50 is etched with the photosensitive film 55 on the resultant, and then the nitride film 60 of the thin film is laminated.
도 2(b) 및 도2(c)에 도시된 바와 같이, 상기 질화막(60)을 블랭킷 식각 (Blanket Etch)으로 메탈(50)의 양측면에 스페이서(Spacer)(65)를 형성하도록 한다.As shown in FIGS. 2 (b) and 2 (c), spacers 65 are formed on both sides of the metal 50 by blanket etching.
도 2(d)에 도시된 바와 같이, 상기 결과물 상에 수소기를 다량으로 발생하는 제1보호막(절연막)(70)과, 수소기의 방출을 차단하는 제2보호막(75)를 적층한 후 열처리공정을 수행하도록 한다.As shown in FIG. 2 (d), the first protective film (insulating film) 70 that generates a large amount of hydrogen groups and the second protective film 75 that blocks the release of hydrogen groups are laminated on the resultant. Allow the process to run.
한편, 상기 열처리공정으로 제1보호막(70)내에 함유된 수소기가 도 2(d)에 도시된 화살표의 경로를 따라 이동하여 반도체기판(10)에서 발생된 격자 결함을 제거하게 된다.Meanwhile, the hydrogen group contained in the first passivation layer 70 is moved along the path of the arrow shown in FIG. 2 (d) by the heat treatment process to remove the lattice defects generated in the semiconductor substrate 10.
이 때, 수소기가 이동하는 경로에서 타타늄막(40) 저면에 TiN막(35)이 적층되어 있으므로 수소기가 티타늄막(40)과 반응하는 것을 방지하여 수소기의 이동을 돕게 된다.At this time, since the TiN film 35 is stacked on the bottom surface of the titanium film 40 in the path of the hydrogen group movement, the hydrogen group is prevented from reacting with the titanium film 40 to help the hydrogen group move.
한편, 도 3(a) 내지 도3(c)는 본 발명의 다른 실시예에 따른 반도체소자에서 격자결함을 제거하기 위하여 금속배선을 순차적으로 형성하는 상태를 보인 도면이다.3 (a) to 3 (c) are views illustrating a state in which metal wirings are sequentially formed in order to remove lattice defects in a semiconductor device according to another exemplary embodiment of the present invention.
도 3(a)에 도시된 바와 같이, 소자분리막(115)이 형성된 반도체기판(110) 상에 소정의 소자구조를 형성한 후, 층간절연막(120)을 적층하도록 한다.As shown in FIG. 3A, after forming a predetermined device structure on the semiconductor substrate 110 on which the device isolation film 115 is formed, the interlayer insulating film 120 is laminated.
계속하여, 상기 층간절연막(120)을 식각하여 콘택을 형성하고 메탈1(125)을 형성하도록 한다.Subsequently, the interlayer insulating layer 120 is etched to form a contact and to form the metal 1 125.
그리고, 상기 메탈1(125) 상에 제1절연막(130), 질화박막(132) 및 제2절연막(133)을 적층한 후, 메탈1(125)으로 연결되는 콘택을 형성하도록 한다.The first insulating layer 130, the nitride thin film 132, and the second insulating layer 133 are stacked on the metal 1 125 to form a contact connected to the metal 1 125.
상기 콘택 내부에 메탈2(150)를 적층한 후에 감광막(155)를 적층하여 패턴을 형성하도록 한다.After the metal 2 150 is stacked inside the contact, a photoresist layer 155 is stacked to form a pattern.
도 3(b)에 도시된 바와 같이, 상기 감광막(155)으로 메탈2(150)를 식각하여 콘택을 형성한 후, 콘택 내에 질화막(160)을 적층하도록 한다.As shown in FIG. 3B, after the metal 2 150 is etched with the photosensitive film 155 to form a contact, the nitride film 160 is stacked in the contact.
도 3(c)에 도시된 바와 같이, 상기 질화막(160)을 마스킹 식각하여 메탈2 (150)의 양측면에 스페이서(165)를 형성하도록 한다.As shown in FIG. 3 (c), the nitride film 160 is masked and etched to form spacers 165 on both sides of the metal 2 150.
계속하여, 상기 결과물 상에 수소기를 다량으로 함유한 제1보호막(170)을 적층한다. 그리고, 수소기가 외부로 누출되는 것을 차단하기 위하여 질화막을 된 제2보호막(175)을 적층하도록 한다. 그런 후에 열처리 공정을 진행 한다.Subsequently, a first protective film 170 containing a large amount of hydrogen groups is laminated on the resultant product. In addition, the second protective film 175 having the nitride film is stacked to block the hydrogen group from leaking to the outside. After that, the heat treatment process is performed.
상기 열처리공정으로 제1보호막(70)내에 함유된 수소기가 도 3(c)에 도시된 화살표의 경로를 따라 이동하여 반도체기판(110)에서 발생된 격자 결함을 제거하게 된다.In the heat treatment process, the hydrogen group contained in the first passivation layer 70 moves along the path of the arrow shown in FIG. 3C to remove the lattice defects generated in the semiconductor substrate 110.
이 때, 수소기가 이동하는 경로에서 타타늄막(40) 저면에 질화박막(132)이 적층되어 있으므로 수소기가 티타늄막(40)과 반응하는 것을 방지하여 수소기의 이동을 돕게 된다.At this time, since the nitride film 132 is stacked on the bottom surface of the titanium film 40 in the path where the hydrogen group moves, the hydrogen group is prevented from reacting with the titanium film 40 to help the hydrogen group move.
상기한 바와 같이, 본 발명에 따른 반도체소자의 격자결함제거방법을 이용하게 되면, 절연막 상에 TiN막과 타타늄막을 적층한 후에 마스킹식각으로 콘택을 형성하여 그 콘택 내부에 메탈2를 매립하여 금속배선을 형성한 후, 질화막을 적층하여 블랭킷식각으로 스페이서를 형성하고, 그 결과물 상에 제1,제2보호막을 적층하여 열처리공정을 진행하면, 보호막내에 함유된 수소기가 반도체기판으로 유입하여 기판에 존재하는 격자 결함을 제거하여 소자의 전시적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the lattice defect removal method of the semiconductor device according to the present invention is used, the TiN film and the titanium film are laminated on the insulating film, and then a contact is formed by masking etching to embed the metal 2 in the contact. After the wiring is formed, a nitride film is stacked to form a spacer by blanket etching, and the first and second protective films are laminated on the resultant to perform a heat treatment process. Then, hydrogen groups contained in the protective film flow into the semiconductor substrate to form a spacer. It is a very useful and effective invention to remove the lattice defects present in the to improve the display properties of the device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990065780A KR20010058448A (en) | 1999-12-30 | 1999-12-30 | Method For Removing The Defect Of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990065780A KR20010058448A (en) | 1999-12-30 | 1999-12-30 | Method For Removing The Defect Of Semiconductor Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010058448A true KR20010058448A (en) | 2001-07-06 |
Family
ID=19632949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990065780A KR20010058448A (en) | 1999-12-30 | 1999-12-30 | Method For Removing The Defect Of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010058448A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100880332B1 (en) | 2007-09-06 | 2009-01-28 | 주식회사 하이닉스반도체 | Method of manufacturing contact plug of semiconductor device |
| US11094882B2 (en) | 2018-09-10 | 2021-08-17 | Samsung Electronics Co., Ltd. | Method of manufacturing memory device |
-
1999
- 1999-12-30 KR KR1019990065780A patent/KR20010058448A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100880332B1 (en) | 2007-09-06 | 2009-01-28 | 주식회사 하이닉스반도체 | Method of manufacturing contact plug of semiconductor device |
| US8143160B2 (en) | 2007-09-06 | 2012-03-27 | Hynix Semiconductor Inc. | Method of forming a contact plug of a semiconductor device |
| US11094882B2 (en) | 2018-09-10 | 2021-08-17 | Samsung Electronics Co., Ltd. | Method of manufacturing memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100695513B1 (en) | Method for manufacturing a semiconductor device | |
| JP2000077625A5 (en) | ||
| CN101625985B (en) | Semiconductor structure and manufacturing method thereof | |
| US9275960B2 (en) | Integrated circuit formed using spacer-like copper deposition | |
| KR20010058448A (en) | Method For Removing The Defect Of Semiconductor Device | |
| KR100964116B1 (en) | Method for fabricating of semiconductor device | |
| KR20080001587A (en) | Method for fabricating semiconductor device | |
| KR100268809B1 (en) | Manufacturing method for via contact of semiconductor device | |
| KR101004526B1 (en) | Method for forming capacitor of semiconductor device | |
| US6673719B2 (en) | Method for etching using a multilevel hard mask | |
| KR100668221B1 (en) | Method for Manufacturing MIM Capacitor | |
| KR101167196B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100349692B1 (en) | Method for etching passivation in ferroelectric memory device | |
| KR100720262B1 (en) | Method of fabricating semiconductor device | |
| KR100808369B1 (en) | Method of manufacturing a semiconductor device | |
| KR100226217B1 (en) | Forming method for electric charge storage electrode of semiconductor device | |
| KR100328696B1 (en) | Method for manufacturing semiconductor device | |
| KR100532981B1 (en) | Etching method of semiconductor device | |
| KR19990004604A (en) | Planarization method of semiconductor device | |
| KR970024006A (en) | Method of forming multi-layer metal wiring of semiconductor device | |
| JP2008016852A (en) | Manufacturing method for flash memory element | |
| KR960002742A (en) | Manufacturing method of semiconductor device | |
| KR950030314A (en) | Semiconductor device connection device and manufacturing method | |
| KR970052493A (en) | Metal wiring film formation method of a semiconductor device | |
| KR20050002503A (en) | method for forming dummy landing plug contact in dummy cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |