KR20010058169A - Error data release circuit - Google Patents

Abstract

PURPOSE: A circuit for restoring error data is provided to compare previous data with next data in case that an error is generated, thereto restore the data by restoring data received through a low voltage differential switching, and by checking whether the data includes an error using a check bit. CONSTITUTION: A system unit(100) is composed of a parity check bit addition unit(10) which gives a 2-bit parity check bit in order to check an error, and an LVDS(Low Voltage Differential Switching) conversion unit(20) which converts an 8-bit digital data signal into a low voltage differential switching signal. A liquid display unit(200) is composed of an LVDS receiving unit(30) which converts an LVDS signal transmitted from the LVDS conversion unit(20) into a digital signal, the first to the third shift register unit(40¯60) which input a digital data signal from the LVDS receiving unit(30) and an error detection unit(70) which compares previous data with next data stored in the first and the third register unit(40,60).

Description

Error data recovery circuit {ERROR DATA RELEASE CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error data recovery circuit of a liquid crystal display, and more particularly to restoring data received through low voltage differencial switching (LVDS) in a system to check whether the data contains an error. The present invention relates to an error data recovery circuit which checks using (check bit) and compares data immediately before or immediately after and recovers the data to the next step.

In general, as the screen of a thin film transistor liquid crystal display (TFT-LCD) becomes higher resolution, an operating frequency is higher than before. In addition, it adopts a method of reducing electromagnetic interference by using LVDS, etc. on the transmission line between the system and the liquid crystal display (LCD), and transmits data at a frequency much higher than the actual frequency. At this time, red (R), green, and other reasons such as data loss due to flexible printer circuit or wire method, data loss due to connector of connection part, data loss due to impedance mismatch, etc. (Green: G), Blue: B Some bits of each 6 to 8 bits of data may be lost. This causes abnormalities in the picture display.

As described above, in the conventional liquid crystal display device, each of the red (R), green (G), and blue (B) data modulated by the LVDS converter is sent in series through four or five pairs of data pair lines to receive an LVDS receiver. The LVDS receiver code embedded in the control IC converts it back into digital data. In this case, even if some or all of the data bits are damaged and misrecognized, they cannot be recovered, thereby causing an error in the image display.

Accordingly, the present invention has been made to solve the above problem. The present invention recovers data received through Low Voltage Differential Switching (LVDS) in a system and checks whether the data contains an error using a check bit. Therefore, it is an object of the present invention to provide an error data recovery circuit which compares the data immediately before or immediately after the error and restores the data to the next step.

1 is a block diagram of an error data recovery circuit according to the present invention.

2A to 2C are circuit diagrams showing an embodiment of the parity check bit adder 10 shown in FIG.

3 is a block diagram of the error detector 70 shown in FIG.

Explanation of symbols on the main parts of the drawings

10: parity check bit adder 20: LVDS converter

30: LVDS receiver 40: first shift register

50: second shift register section 60: third shift register section

70: error detection unit 72: error check stage

74: comparison 76: selection

100: system unit 200: liquid crystal display unit

In order to achieve the above object, the error data recovery circuit according to the present invention,

Parity check bit adding means for giving M bit parity check bits for error checking by inputting N bit digital data, and converting the digital data signal from the parity check bit adding means into a low voltage differential switching signal. A system unit comprising signal conversion means for outputting the

Signal receiving means for receiving the low voltage differential switching signal transmitted from the signal converting means and converting the digital signal back into a digital signal, a plurality of register means for receiving and sequentially storing digital data signals from the signal receiving means; After checking the error by inputting digital data signals from the plurality of register means, the data having an error is compared with the previous data and the subsequent data stored in the plurality of register means, and outputs the most similar data of the two data. If not, it characterized in that it comprises a liquid crystal display unit composed of error detection means for directly outputting the input data.

In this case, the N-bit digital data is characterized in that 6 bits.

The N bit digital data is 8 bits.

The parity check bit of the M bit is at least 1 bit or more.

And the parity check bit adding means comprises a plurality of exclusive OR gates which generate the M bit parity check bits as the input of the N bit digital data.

The plurality of register means is composed of three shift registers.

The error detecting means includes an error check unit for inputting digital data signals from the plurality of register means to detect whether there is an error by the parity bits, and the data output from the error check unit. If a signal has an error, a comparator for outputting the most similar data signal compared to the previous and subsequent data stored in the plurality of register means, and data input by inputting the data signals from the error checker and the comparator respectively, respectively. And a selection unit for selectively outputting an output signal of the error check unit or the comparison unit according to whether or not an error occurs.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

1 is a block diagram of an error data recovery circuit according to an embodiment of the present invention, wherein a parity check bit adder 10 and a parity check bit adder 10 which gives a 2-bit parity check bit for error checking by inputting 6-bit digital data as inputs are shown. And a system unit 100 composed of an LVDS conversion unit 20 for converting an 8-bit digital data signal from the check bit addition unit 10 into a low voltage differential switching (LVDS) signal.

In addition, the LVDS receiver 30 which receives the LVDS signal transmitted from the LVDS converter 20 and converts the signal back into a digital signal, and 3 which receives and sequentially stores the digital data signal from the LVDS receiver 30 After checking the error by inputting the digital data signals from the first to third shift registers 40 to 60 and the first to third shift registers 40 to 60, the data with errors is described above. Compared to the previous and subsequent data stored in the first and third shift registers 40 and 60, the error detection unit 70 outputs the most similar data among the two data and directly outputs the input data when there is no error. The configured liquid crystal display unit 200 is provided.

Red (R), Green (G), and Blue (B) often use 6 or 8 bits respectively, which determines the reproducible range of colors. If red (R), green (G), and blue (B) are 6 bits each, each combination of red (R), green (G), and blue (B) has 64 cases. It can express 262,144 kinds of colors, and in case of 8 bits, each red (R), green (G), and blue (B) expresses 256 colors, and when combined, it can express 16,777,216 kinds of colors. do.

The present invention will be described taking 6-bit red (R), green (G), and blue (B) as an example. In the transmission mode, the LVDS transmission method is used since the LVDS interface is adopted in the XGA class or higher.

LVDS logic is either embedded within the control IC or separated as a separate IC, which is becoming increasingly embedded.

Since the present invention is a method of detecting and restoring an error between an output of an LVDS logic and an input of a control IC, when the LVDS and the control IC are separated, the error data recovery circuit of the present invention is included in either of the LVDS and the control IC. You may be.

In FIG. 1, 6-bit digital data is coded using a method of adding a parity check bit to perform an error check. The parity bit checks the number of 1s in the unit data and outputs 1 if the number is odd and 0 if the even number is odd.Odd parity check if the even number is even parity check. 1 if the even number is 1 and 0 if the odd number is odd. do. The parity check logic is shown in FIGS. 2A-2C.

2A to 2C are circuit diagrams showing an embodiment of the parity check bit adder 10 shown in FIG.

First, FIG. 2A is a circuit diagram of the parity check bit adding unit 10 when one parity bit is used for 6-bit data. In this case, since there is only one parity bit, the exact location of the error in the entire data cannot be known, but only whether there is an error bit can be determined.

2B is a circuit diagram of the parity check bit adder 10 when two parity bits are used for 6-bit data. In this case, by using two parity bits, it is possible to determine which of the upper 3 bits and the lower 3 bits.

2C is a circuit diagram of the parity check bit adder 10 when three parity bits are used for 6-bit data. In this case, if three parity bits are used, it is possible to know in detail where the error bit exists among the upper 2 bits, the middle 2 bits, and the lower 2 bits.

The more the parity bit is used, the higher the error checking accuracy is, and it becomes an important factor in selecting the data immediately before or immediately after the error recovery logic. If there is only one parity bit and only the presence or absence of an error can be selected, any one of the data before and after the error data can be selected. This is because it can be converted closer to the next higher bit and lower bit. However, the more you use the parity bits, the more you need to increase the transmission speed when sending data serially. Therefore, it is better to use an appropriate number of parity bits in consideration of transmission speed and detection efficiency.

The 8-bit digital data signal to which the parity bit is added by the parity check bit adder 10 is input to the LVDS converter 20.

The LVDS conversion unit 20 converts the 8-bit digital data signal added with the parity bit output from the parity check bit adder 10 into an LVDS signal and transmits the 8-bit digital data signal to the LCD unit 200 through a transmission line FPC or WIRE.

The LVDS receiver 30 of the LCD unit 200 converts the LVDS signal transmitted from the LVDS converter 20 back into a digital signal. The converted digital signal is input to and stored in the three stages of shift registers 40 to 60.

The three shift register sections 40 to 60 store the previous data and the subsequent data of the data to be examined in the registers, respectively.

Fig. 3 is a block diagram showing the configuration of the error detection unit 70 used in the present invention. The digital data signals from the plurality of register means are inputted to determine whether there is an error due to the parity bit. The error check stage 72 to detect and the comparison stage outputting the most similar data signal compared to the previous and subsequent data stored in the plurality of register means when the data signal outputted from the error check stage 72 has an error The error check stage 72 or the comparison stage 74 depends on whether or not the data inputted from the error check stage 72 and the comparison stage 74 is input respectively. And a selector 76 for selectively outputting the output signal.

In the error detection unit 70, the data having an error is compared with the previous and subsequent data stored therein, so that the data enters the first register unit 40 and enters the second register unit 50 so as to be exported. The unit 60 has the data immediately before it, and the first register unit 60 has the next data after the data to be checked.

When the data to be checked passes from the first register section 40 to the second register section 50, the data is also checked for an input error at the error check stage 72 of the error detection section 70 at the same time. If there is an error, the next data and the previous data stored in the first register 40 and the second register 50 are compared with each other, and converted into more similar data and output in the next step. If there is no error, the data is output from the error detection unit 70 as it is.

If it is confirmed that there is an error, the most similar data of the two compared data should be exported. If there is one parity bit, one of them can be selected at random.

The reason for doing this is to take advantage of the fact that due to the nature of the screen, it is very likely to be the same as either the previous data or the immediate data.

As described above, according to the error data recovery circuit according to the present invention, after restoring data received through low voltage differential switching (LVDS) in the system, a check bit is used to check whether the data contains an error. If there is an error, there is an effect that can be restored by comparing the previous data or the subsequent data.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (7)

In the liquid crystal display device, Parity check bit adding means for giving M bit parity check bits for error checking by inputting N bit digital data, and converting the digital data signal from the parity check bit adding means into a low voltage differential switching signal. A system unit comprising signal conversion means for outputting the Signal receiving means for receiving the low voltage differential switching signal transmitted from the signal converting means and converting the digital signal back into a digital signal, a plurality of register means for receiving and sequentially storing digital data signals from the signal receiving means; After checking the error by inputting digital data signals from the plurality of register means, the data having an error is compared with the previous data and the subsequent data stored in the plurality of register means, and outputs the most similar data of the two data. And a liquid crystal display unit comprising error detection means for immediately outputting the input data when there is no error. The method of claim 1, And the N bit digital data is 6 bits. The method of claim 1, And the N bit digital data is 8 bits. The method of claim 1, And the parity check bit of the M bit is at least one bit or more. The method of claim 1, The parity check bit addition means, And a plurality of exclusive OR gates generating the M bit of the parity check bit as the input of the N bit digital data. The method of claim 1, And said plurality of register means comprises three shift registers. The method of claim 1, The error detection means, An error check unit which inputs digital data signals from the plurality of register means and detects whether there is an error by parity bits; A comparator for outputting the most similar data signal by comparing the previous and subsequent data stored in the plurality of register means when the data signal outputted from the error check part has an error, An error data recovery circuit comprising a selection unit for selectively outputting the output signal of the error check unit or the comparison unit according to whether or not the data inputted from the error check unit and the comparison unit is input as an error; .