KR20010056940A - Method for forming metal interconnection line of semiconductor device - Google Patents
Method for forming metal interconnection line of semiconductor device Download PDFInfo
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- KR20010056940A KR20010056940A KR1019990058626A KR19990058626A KR20010056940A KR 20010056940 A KR20010056940 A KR 20010056940A KR 1019990058626 A KR1019990058626 A KR 1019990058626A KR 19990058626 A KR19990058626 A KR 19990058626A KR 20010056940 A KR20010056940 A KR 20010056940A
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- film
- interlayer insulating
- forming
- contact hole
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 85
- 239000002184 metal Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 69
- 239000010410 layer Substances 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 99
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 abstract description 5
- 239000010937 tungsten Substances 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, 다마신(damascene) 공정을 이용하여, 구리 금속막으로 금속 배선을 형성하는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices in which metal wirings are formed from a copper metal film using a damascene process.
반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.
도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.
도 1을 참조하여, 도전 영역을 포함하는 반도체 기판 상부에 층간 절연막(2)을 형성한다. 도전 영역의 소정 부분이 노출될 수 있도록, 층간 절연막(2)을 식각하여, 콘택홀(3)을 형성한다. 이때, 콘택홀(3)의 사이즈는, 현재 고집적화 추세를 고려하여 0.5㎛ 이하로 형성한다. 그리고나서, 층간 절연막(2) 표면 및 콘택홀(3)의 저부 표면에 베리어 금속막(4)을 형성한다. 그 다음, 베리어 금속막(4) 상부에 알루미늄 합금막(5)을 증착한다. 그후, 알루미늄 합금막(5) 및 베리어 금속막(4)을 공지의 포토리소그라피 공정을 이용하여 소정 부분 패터닝하여, 금속 배선을 형성한다.Referring to FIG. 1, an interlayer insulating film 2 is formed on a semiconductor substrate including a conductive region. The interlayer insulating film 2 is etched to form a contact hole 3 so that a predetermined portion of the conductive region is exposed. At this time, the size of the contact hole 3 is formed to 0.5㎛ or less in consideration of the current high integration trend. Then, the barrier metal film 4 is formed on the surface of the interlayer insulating film 2 and the bottom surface of the contact hole 3. Next, an aluminum alloy film 5 is deposited on the barrier metal film 4. Thereafter, the aluminum alloy film 5 and the barrier metal film 4 are partially patterned using a known photolithography process to form a metal wiring.
그러나, 금속막을 직접 패터닝하여, 금속 배선을 형성하는 종래의 방법은 다음과 같은 문제점을 갖는다.However, the conventional method of directly patterning a metal film to form a metal wiring has the following problems.
먼저, 현재의 반도체 소자의 디자인 룰이 0.2㎛ 대임에 따라, 콘택홀의 사이즈 역시 매우 미세해지므로, 콘택홀의 어스펙트비가 커지게 된다.First, as the current design rules of semiconductor devices are about 0.2 μm, the size of the contact hole becomes very fine, and the aspect ratio of the contact hole becomes large.
이에따라, 금속 배선의 임계 치수(critical dimension)가 감소되어야 하므로, 종래의 노광 장비로는 원하는 형태로 패터닝하기 어려울 뿐만 아니라, 금속 배선의 사이즈가 감소되기 때문에 그 전기적 특성의 확보하기 어렵다.Accordingly, since the critical dimension of the metal wiring must be reduced, it is difficult not only to pattern the desired shape with conventional exposure equipment, but also to secure its electrical characteristics because the size of the metal wiring is reduced.
또한, 현재 금속 배선 공정에서 주 금속막으로 이용되는 알루미늄 합금막은 스텝 커버리지 특성이 열악하여, 어스펙트 비가 큰 현재의 콘택홀 내부에 고르게 증착되기 매우 어렵다. 이로 인하여, 심할 경우, 콘택홀내에서 금속 배선이 단선되는 경우가 빈번히 발생된다.In addition, the aluminum alloy film used as the main metal film in the current metal wiring process is poor in step coverage characteristics, and thus it is very difficult to be evenly deposited inside the current contact hole having a large aspect ratio. For this reason, in severe cases, the metal wires are frequently disconnected in the contact holes.
따라서, 본 발명은 어스펙트비가 큰 콘택홀내에 금속 배선을 용이하게 형성할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor element which can easily form a metal wiring in a contact hole having a large aspect ratio.
도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도2A through 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 - 반도체 기판 11 - 베리어 금속막10-semiconductor substrate 11-barrier metal film
12 - 제 1 층간 절연막 13 - 제 2 층간 절연막12-first interlayer insulating film 13-second interlayer insulating film
14 - 제 1 콘택홀 15 - 플러그14-1st contact hole 15-Plug
16 - 포토레지스트 패턴 17 - 제 2 콘택홀16-photoresist pattern 17-second contact hole
18 - 구리 금속 배선 19 - 절연박막18-Copper Metal Wiring 19-Insulated Thin Film
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상부의 소정 부분에 베리어 금속막을 형성하는 단계; 상기 베리어 금속막이 형성된 반도체 기판 상부에 제 1 층간 절연막을 형성하는 단계; 상기 제 1 층간 절연막 상부에 상기 제 1 층간 절연막과 식각 속도가 상이한 제 2 층간 절연막을 형성하는 단계; 상기 베리어 금속막의 소정 부분이 노출되도록, 제 2 층간 절연막은 비등방성으로 식각하고, 제 1 층간 절연막을 등방성으로 식각하여, 상하 사이즈가 상이한 콘택홀을 형성하는 단계; 상기 노출된 베리어 금속막 상부에 금속 배선을 형성하는 단계; 및 상기 콘택홀이 매립되도록 금속 배선 상부에 절연 박막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, forming a barrier metal film on a predetermined portion of the semiconductor substrate; Forming a first interlayer insulating film on the semiconductor substrate on which the barrier metal film is formed; Forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having an etching rate different from that of the first interlayer insulating layer; Etching the second interlayer insulating film anisotropically and etching the first interlayer insulating film isotropically so that a predetermined portion of the barrier metal film is exposed to form contact holes having different top and bottom sizes; Forming a metal wire on the exposed barrier metal film; And forming an insulating thin film on an upper portion of the metal wiring to fill the contact hole.
또한, 본 발명은, 반도체 기판 상부의 소정 부분에 베리어 금속막을 형성하는 단계; 상기 베리어 금속막이 형성된 반도체 기판 상부에 제 1 층간 절연막을 형성하는 단계; 상기 제 1 층간 절연막 상부에 상기 제 1 층간 절연막과 식각 속도가상이한 제 2 층간 절연막을 형성하는 단계; 제 1 및 제 2 층간 절연막의 소정 부분을 비등방성으로 식각하여, 제 1 콘택홀을 형성하는 단계; 상기 제 1 콘택홀내에 콘택 플러그를 형성하는 단계; 상기 베리어 금속막의 소정 부분이 노출되도록, 제 2 층간 절연막은 비등방성으로 식각하고, 제 1 층간 절연막을 등방성으로 식각하여, 상하 사이즈가 상이한 제 2 콘택홀을 형성하는 단계; 상기 제 2 콘택홀내 노출된 베리어 금속막 상부에 구리 금속 배선을 형성하는 단계; 및 상기 제 2 콘택홀이 매립되도록 구리 금속 배선 상부에 절연 박막을 형성하는 단계를 포함하며, 상기 구리 금속 배선은 제 1 층간 절연막 두께의 80% 이하의 두께로 형성하는 것을 특징으로 한다.In addition, the present invention, forming a barrier metal film on a predetermined portion of the semiconductor substrate; Forming a first interlayer insulating film on the semiconductor substrate on which the barrier metal film is formed; Forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having an etching rate different from that of the first interlayer insulating layer; Anisotropically etching certain portions of the first and second interlayer insulating films to form a first contact hole; Forming a contact plug in the first contact hole; Etching the second interlayer insulating film anisotropically and etching the first interlayer insulating film isotropically so as to expose a predetermined portion of the barrier metal film, thereby forming second contact holes having different vertical sizes; Forming a copper metal wire on the barrier metal film exposed in the second contact hole; And forming an insulating thin film on an upper portion of the copper metal wiring to fill the second contact hole, wherein the copper metal wiring is formed to a thickness of 80% or less of the thickness of the first interlayer insulating film.
본 발명에 따르면, 층간 절연막을 두 층으로 형성하고, 비등방성 및 등방성 식각을 이용하여 층간 절연막내에 콘택홀을 형성한다음, 콜리미네이트 물리적 증착 방식으로 구리 금속 배선을 형성한다. 이어서, 구리 금속 배선의 표면을 덮도록 콘택홀내에 절연박막을 증착한다.According to the present invention, an interlayer insulating film is formed of two layers, contact holes are formed in the interlayer insulating film using anisotropic and isotropic etching, and then copper metal wiring is formed by collimated physical vapor deposition. Next, an insulating thin film is deposited in the contact hole so as to cover the surface of the copper metal wiring.
이에따라, 미세한 콘택홀내에 금속 배선을 형성하기 용이하며, 콜리미네이트 물리적 증착 방식으로 구리 금속 배선을 형성하므로써, 제조 비용을 절감할 수 있다.Accordingly, it is easy to form the metal wiring in the fine contact hole, and by forming the copper metal wiring by the collimated physical vapor deposition method, it is possible to reduce the manufacturing cost.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 도전 영역(도시되지 않음)을 구비한 반도체 기판(10) 상부에 베리어 금속막(11)을 증착한다. 그 다음, 도전 영역 상부에만 존재하도록 베리어 금속막(11)을 소정 부분 패터닝한다. 그리고 난다음, 제 1 층간 절연막(12) 및 제 2 층간 절연막(13)을 순차적으로 증착한다. 이때, 제 1 층간 절연막(12)은 평탄화막으로서, 예를들어 BPSG, PSG와 같은 막이 이용된다. 제 2 층간 절연막(13)은 제 1 층간 절연막(12)과는 식각 속도가 상이한 물질로, 예를들어 플라즈마 산화막, 플라즈마 질화막 또는 알루미늄 산화막이 사용된다. 그후, 국부 배선(local interconnection line)을 형성하기 위하여, 제 1 및 제 2 층간 절연막(12,13)의 소정 부분을 비등방성 건식식각하여, 제 1 콘택홀(14)을 형성한다.Referring to FIG. 2A, a barrier metal film 11 is deposited on a semiconductor substrate 10 having a conductive region (not shown). Next, the barrier metal film 11 is partially patterned so as to exist only on the conductive region. Then, the first interlayer insulating film 12 and the second interlayer insulating film 13 are sequentially deposited. At this time, the first interlayer insulating film 12 is a planarization film, for example, a film such as BPSG or PSG is used. The second interlayer insulating film 13 is formed of a material having an etching rate different from that of the first interlayer insulating film 12. For example, a plasma oxide film, a plasma nitride film, or an aluminum oxide film is used. Thereafter, in order to form a local interconnection line, predetermined portions of the first and second interlayer insulating films 12 and 13 are anisotropically dry etched to form the first contact holes 14.
그 다음, 도 2b에 도시된 바와 같이, 제 1 콘택홀(14)이 충분히 매립되도록 제 2 층간 절연막(14) 상부에 텅스텐 금속막을 화학기상증착법에 의하여 증착한다. 그 다음, 텅스텐 금속막을 제 2 층간 절연막(14) 표면이 노출되도록 에치백하여, 제 1 콘택홀(14)내에 텅스텐 플러그(15)를 형성한다.Next, as shown in FIG. 2B, a tungsten metal film is deposited on the second interlayer insulating film 14 by chemical vapor deposition so that the first contact hole 14 is sufficiently filled. Next, the tungsten metal film is etched back so that the surface of the second interlayer insulating film 14 is exposed to form the tungsten plug 15 in the first contact hole 14.
도 2c를 참조하여, 텅스텐 플러그(15) 및 제 2 층간 절연막(13) 상부에 포토레지스트막을 도포하고, 베리어 금속막(11)이 매립된 제 2 층간 절연막(13) 부분이 오픈될 수 있도록 노광 및 현상하여 포토레지스트 패턴(16)을 형성한다. 그후, 포토레지스트 패턴(16)을 마스크로 하여, 베리어 금속막(11)이 노출되도록 제 1 및 제 2 층간 절연막(12,13)을 식각한다. 이때, 제 2 층간 절연막(13)은 비등방성으로 식각하고, 제 1 층간 절연막(12)은 언더컷이 발생될 수 있도록 등방성으로 식각하여, 주 금속 배선(global interconnection line)을 형성하기 위한 제 2 콘택홀(17)을 형성한다.Referring to FIG. 2C, a photoresist film is coated on the tungsten plug 15 and the second interlayer insulating layer 13, and the second interlayer insulating layer 13 having the barrier metal layer 11 embedded therein is exposed to be exposed. And developing to form the photoresist pattern 16. Thereafter, using the photoresist pattern 16 as a mask, the first and second interlayer insulating films 12 and 13 are etched to expose the barrier metal film 11. At this time, the second interlayer insulating film 13 is anisotropically etched, and the first interlayer insulating film 12 is isotropically etched to generate an undercut, thereby forming a second interconnection line for forming a global interconnection line. The hole 17 is formed.
다음으로, 도 2d에 도시된 바와 같이, 제 2 콘택홀(17)내에 구리 금속 배선(18)을 형성한다. 이때, 구리 금속 배선(18)은 베리어 금속막(11) 상부에 형성되고, 콜리미네이트-물리증착법(colliminated physical vapor deposition)에 의하여 형성된다. 여기서, 상기 콜리미네이트 물리증착법으로 금속 배선을 형성하면, 기존의 MOCVD(metal ogarnic chemical vapor deposition) 방식으로 구리 금속 배선을 형성할때보다 낮은 비용으로 형성할 수 있다는 장점이 있다.Next, as shown in FIG. 2D, a copper metal wiring 18 is formed in the second contact hole 17. At this time, the copper metal wiring 18 is formed on the barrier metal film 11 and formed by collimated physical vapor deposition. Here, if the metal wiring is formed by the collimated physical vapor deposition method, there is an advantage that can be formed at a lower cost than when forming a copper metal wiring by the conventional metal ogarnic chemical vapor deposition (MOCVD) method.
구리 금속 배선(18)의 두께(b)는 제 1 층간 절연막(12) 두께(a)의 80% 이하로 형성함이 바람직하다. 이는 이후, 구리 금속 배선(18) 표면에 절연박막을 고르게 덮기 위함이다.The thickness b of the copper metal wiring 18 is preferably formed to be 80% or less of the thickness a of the first interlayer insulating film 12. This is for the purpose of evenly covering the insulating thin film on the surface of the copper metal wiring 18.
그후, 도 2e에 도시된 바와 같이, 제 2 콘택홀(17) 내부에 구리 금속 배선(18)을 보호하도록 절연박막(19)을 형성한다. 여기서, 절연박막(19)으로는 실리콘 질산화막(SiON), 실리콘 불산화막(SiOF) 또는 유기 절연막이 선택적으로 이용될 수 있다.Thereafter, as shown in FIG. 2E, an insulating thin film 19 is formed in the second contact hole 17 to protect the copper metal wiring 18. Here, as the insulating thin film 19, a silicon nitride oxide film (SiON), a silicon fluoride film (SiOF), or an organic insulating film may be selectively used.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 층간 절연막을 두 층으로 형성하고, 비등방성 및 등방성 식각을 이용하여 층간 절연막내에 콘택홀을 형성한다음, 콜리미네이트 물리적 증착 방식으로 구리 금속 배선을 형성한다. 이어서, 구리 금속 배선의 표면을 덮도록 콘택홀내에 절연박막을 증착한다.As described in detail above, according to the present invention, an interlayer insulating film is formed into two layers, contact holes are formed in the interlayer insulating film by using anisotropic and isotropic etching, and copper metal wiring is formed by collimated physical vapor deposition. Form. Next, an insulating thin film is deposited in the contact hole so as to cover the surface of the copper metal wiring.
이에따라, 미세한 콘택홀내에 금속 배선을 형성하기 용이하며, 콜리미네이트 물리적 증착 방식으로 구리 금속 배선을 형성하므로써, 제조 비용을 절감할 수 있다.Accordingly, it is easy to form the metal wiring in the fine contact hole, and by forming the copper metal wiring by the collimated physical vapor deposition method, it is possible to reduce the manufacturing cost.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (13)
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