KR20010056391A - A Method for Manufacturing Metal-BGA Package Substrate - Google Patents

A Method for Manufacturing Metal-BGA Package Substrate Download PDF

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KR20010056391A
KR20010056391A KR1019990057841A KR19990057841A KR20010056391A KR 20010056391 A KR20010056391 A KR 20010056391A KR 1019990057841 A KR1019990057841 A KR 1019990057841A KR 19990057841 A KR19990057841 A KR 19990057841A KR 20010056391 A KR20010056391 A KR 20010056391A
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circuit
forming
bga
circuits
heat sink
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KR1019990057841A
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Korean (ko)
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KR100344618B1 (en
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윤경로
강명삼
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이형도
삼성전기주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A method for manufacturing a substrate of a metal ball grid array package is provided with a simplified process and a reduced cost while maintaining required thermal characteristics. CONSTITUTION: The method includes forming circuits in a build-up manner. In the method, after a basic hole and an inner circuit are formed in a heat dissipating plate of copper or aluminum, the heat dissipating plate is plated for buffering and finished in black. Next, an insulating layer is formed for formation of the circuits, and then a via hole is formed, textured and plated. Next, the circuits are formed and inspected. Then, the formation of the insulating layer, the via hole and the circuits is repeated to make required layers of the circuits. Next, a solder resist is printed on an uppermost layer, then typically finished and inspected.

Description

M-BGA 패키지 기판의 제조방법{A Method for Manufacturing Metal-BGA Package Substrate}A Method for Manufacturing Metal-BGA Package Substrate

본 발명은 방열판을 갖는 패키지 기판의 제조방법에 관한 것으로, 보다 상세하게는 방열판위에 빌드업 방식으로 적층하여 패키지 기판을 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a package substrate having a heat sink, and more particularly, to a method for manufacturing a package substrate by laminating on a heat sink in a buildup manner.

전자산업이 점점 더 고도화되고 있는 추세에 발맞추어 전자제품이 소형화, 대용량화하기 시작하였고, 이에 따른 IC칩(Chip)의 발달로 I/O 카운트(Count)가 증가하게 되었다. 반도체의 I/O 카운트가 증가하게 되면 이를 구동시킬 때에 I/C칩에서 많은 열이 발생하게 된다. 이를 해결하기 위하여 기존에는 냉각 팬을 부착시켰는데 이는 전자제품의 소형화에 걸림돌이 되기 때문에 새로운 패키지(package)찾게 되었다. 이를 위하여 고안된 패키지가 일반 패키지에 방열판(Heatsink) 역할을 하는 구리금속(Copper Metal)을 부착시킨 S-BGA(Super-Ball Grid Array) 및 E-BGA(Enhanced-BGA) 기판인데, I/C칩에 직접 금속이 부착되어 발생하는 열을 외부로 방출시키는 것이다.As the electronic industry is becoming more and more advanced, electronic products have begun to be miniaturized and large-capacity. Accordingly, the development of IC chips has led to an increase in the I / O count. When the I / O count of a semiconductor increases, a lot of heat is generated in an I / C chip when driving it. In order to solve this problem, a conventional cooling fan is attached, which is an obstacle to the miniaturization of electronic products, so a new package is found. Packages designed for this purpose are S-BGA (Super-Ball Grid Array) and E-BGA (Enhanced-BGA) substrates with copper metal attached to a heatsink. It is to release heat generated by metal attached directly to the outside.

기존의 S-BGA 제조공정을 살펴보면, 방열판을 2메탈(metal)로 사용하였고 방열판이 공정중간에 레이업이 되는 프로세스를 사용하고, 방열판이 중간공정에 추가되기 위하여 별도의 공정을 거치게 된다. 이같은 S-BGA 제조의 일반적인 공정을 도 1에 나타내었다.Looking at the existing S-BGA manufacturing process, the heat sink is used as 2 metal (metal), the heat sink is used to lay up in the middle of the process, the heat sink is subjected to a separate process to add to the intermediate process. A general process of such S-BGA preparation is shown in FIG. 1.

도 1에서 보는 바와 같이, 방열판이 2층으로 들어가야하기 때문에 2차, 3차 적층으로 이를 진행하는데, 이때 본 공정과는 별도로 방열판을 "2"공정과 "3"공정으로 진행한후, 이를 본 공정의 적층시에 적용하여 진행한다. 즉, 2차 적층시에는 "2"공정으로 미리 제작된 Cu금속과 프리플랙(Prepreg)을 사용하여 CCL과 방열판을 부착시킨다. 이때, 일반 V-프레스(Press)를 사용한다. 또한, 3차 적층시에는 금도금이 완료되어 있는 제품을 "3"공정으로 제작된 방열판을 프리플랙을 사용하여 부착시킨다. 이때에도 일반 V-프레스를 사용한다.As shown in Fig. 1, since the heat sink must enter the second layer, it proceeds to the second and third lamination, in which the heat sink is proceeded to the "2" process and the "3" process separately from this process, It applies and progresses at the time of lamination | stacking of a process. That is, in the second lamination, the CCL and the heat sink are attached to each other using Cu metal and prepreg prepared in the "2" process. In this case, a general V-press is used. In addition, during the third lamination, the heat sink manufactured by the “3” process is attached to the product having the gold plating completed by using the preflag. Again use the normal V-press.

그러나, 이 같은 S-BGA기판은 열방출 성능 및 신뢰성은 아주 우수하나 제조공정이 복잡하고, 파인패턴(Fine Pattern) 회로형성이 어렵웠다. 이러한 문제는 E-BGA기판에서도 동일하게 내포하고 있는 것이다. 이로 인해, S-BGA 및 E-BGA와 같은 기판의 제조시에는 비용이 상승하기 때문에, 부품조립(Assembly)업체에서는 우수한열적성능과 신뢰성을 방탕으로 하고 비용이 저렴한 기판을 필요로 하게 되었다.However, the S-BGA substrate has excellent heat dissipation performance and reliability, but the manufacturing process is complicated and it is difficult to form a fine pattern circuit. This problem is also included in the E-BGA substrate. As a result, the cost of manufacturing substrates such as S-BGA and E-BGA increases, and therefore, assembly companies need substrates with excellent thermal performance and reliability and low cost.

이에, 본 발명자들은 우수한 열적성능 및 신뢰성을 보이면서도 간단한 공정을 적용할 수 있는 패기지 기판를 얻기 위해 연구와 실험을 거듭하고 그 결과에 근거하여 본 발명을 제안하게 된 것으로, 본 발명은 방열판 위에 완충층을 형성하고 빌드업방식으로 회로를 형성함으로서, 기존에 요구되던 열적특성을 보이면서도 제조공정이 간단하여 보다 저렴하게 제조할 수 있는 새로운 BGA패키지를 제공하고자 하는데, 그 목적이 있다.Accordingly, the present inventors have repeatedly studied and experimented to obtain a package substrate to which a simple process can be applied while showing excellent thermal performance and reliability, and proposed the present invention based on the results. By forming a circuit and forming a circuit in a build-up manner, it is intended to provide a new BGA package that can be manufactured at a lower cost because the manufacturing process is simple while showing the thermal characteristics required in the past.

도 1은 S-BGA의 일반 제조프로세스를 보이는 공정도1 is a process diagram showing a general manufacturing process of S-BGA

상기 목적을 달성하기 위한 본 발명은 방열판에 기준홀 및 내층회로를 형성하는 1단계; 상기 방열판 위에 완충작용을 위한 플래이팅(Plating)처리를 행하고 흑화처리를 행하는 2단계; 회로 형성을 위한 절연층을 형성하는 3단계; 비어홀을 형성하고 조화처리(Texturing)를 행하는 4단계; 도통을 위한 도금을 행하는 5단계; 회로를 형성하고 형성된 회로를 검사하는 6단계; 목적하는 층수에 맞게 상기 3단계에서 6단계까지의 과정을 반복하는 7단계; 목적하는 층수에 맞게 회로를 형성한 후 최상층에 솔더레지스트를 인쇄하고 통상 공정으로 가공 및 검사하는 8단계;를 포함하는 것을 특징으로 하는 M-BGA패키지 기판의 제조방법에 관한 것이다.The present invention for achieving the above object is a step of forming a reference hole and the inner layer circuit in the heat sink; Performing a plating process for buffering on the heat sink and performing a blackening process; Forming an insulating layer for forming a circuit; Four steps of forming a via hole and performing texturing; 5 steps of plating for conduction; Forming a circuit and inspecting the formed circuit; 7 steps of repeating the process from step 3 to step 6 according to the desired number of floors; It relates to a method of manufacturing an M-BGA package substrate comprising a; 8 steps of forming a circuit to the desired number of layers and then printing the solder resist on the top layer and processing and inspection in a normal process.

이하, 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.

본 발명에 의한 패키지 기판은 적층공정이 없이 빌드업(Build-up)공법으로 제조하는 Metal-Ball Grid Array(간단히, "M-BGA"라 한다)이며, 빌드업공법을 적용함으로서 많은 공정이 줄어든다. 따라서, 기존의 S-BGA 및 E-BGA기판의 제조공정, 예를 들어 4층 기준으로 하는 경우는 적층을 3회 또는 1회 진행하지만, 본 발명에 의한 M-BGA기판은 적층공정을 행하지 않기 때문에 보다 간단한 공정으로 제조할 수 있는 것이다. 다음에서는 빌드업 방식에 의한 본 발명을 공정별로 설명한다.The package substrate according to the present invention is a metal-ball grid array (hereinafter, simply referred to as "M-BGA") manufactured by a build-up method without a lamination process, and many processes are reduced by applying the build-up method. . Therefore, the conventional S-BGA and E-BGA substrate manufacturing process, for example, four-layer lamination proceeds three or once lamination, the M-BGA substrate according to the present invention does not perform the lamination process Therefore, it can be manufactured by a simpler process. Next, the present invention by the build-up method will be described step by step.

먼저, 본 발명에서는 방열판에 기준홀 및 내층회로를 형성하는 과정을 거친다.First, in the present invention, the process of forming the reference hole and the inner layer circuit in the heat sink.

상기 방열판은 Cu, Al 등과 같은 재질을 적용할 수 있으며, 상기 방열판에는 기준홀을 형성한 후에 내층회로를 형성하는 것이다.The heat sink may be made of a material such as Cu, Al, and the like, and an inner layer circuit is formed after the reference hole is formed in the heat sink.

또한, 본 발명에서는 상기 방열판 위에 완충작용을 위한 플래이팅(Plating)처리를 행하고 흑화처리를 행하는 과정을 거친다.In addition, in the present invention, a plating process for a buffering action is performed on the heat sink and a blackening process is performed.

상기 플래이팅 처리는 회로의 상처를 방지하기 위해 행하는 것으로, Ni 등에 의해 처리하는 것이다. 상기 흑화처리는 표면조도를 확보하기 위해 행해진다.The plating process is performed to prevent damage to the circuit and is performed by Ni or the like. The blackening process is performed to secure surface roughness.

또한, 본 발명에서는 회로 형성을 위한 절연층을 형성하는 과정을 거치며, 또한 비어홀을 형성하고 조화처리(Texturing)를 행하는 과정을 거치며, 또한 도통을 위한도금을 행하는 과정을 거치고, 회로를 형성하고 형성된 회로를 검사하는 과정을 거친다.Further, in the present invention, a process of forming an insulating layer for forming a circuit is performed, a process of forming a via hole and a texturing process, and a process of plating for conduction, and a circuit is formed and formed. Inspect the circuit.

상기 절연층은 수지코팅(Resin Coating), 즉 감광성/열경화성 잉크를 사용하여 형성하는 것으로, 층을 형성할 때 마다 형성한다.The insulating layer is formed using a resin coating, that is, a photosensitive / thermosetting ink, and is formed every time a layer is formed.

상기 비어홀은 레이저(Laser)나 포토레지스트 등의 방법을 적용하여 행할 수 있으며, 상기 조화처리(Texturing)는 통상의 방법을 적용하여 행할 수 있다. 상기 조화처리후에는 도통을 위해 Cu 등에 의해 도금을 행한다.The via hole may be performed by applying a laser, photoresist, or the like, and the roughening may be performed by applying a conventional method. After the roughening treatment, plating is performed by Cu or the like for conduction.

상기 회로형성은 목적하는 패턴으로 형성하고, 이를 검사하는 과정을 거친다.The circuit formation is formed in a desired pattern and undergoes a process of inspecting it.

또한, 본 발명에서는 목적하는 층수에 맞게 상기 "절연층형성"과정에서 "회로검사"과정을 반복한다.In addition, in the present invention, the "circuit test" process is repeated in the "insulation layer formation" process according to the desired number of layers.

상기 절연층형성 과정에서 회로검사과정을 거침으로서 1개의 층이 형성되는데, 본 발명은 이러한 층 형성을 방열판위에 빌드업방식에 의해 직접 행하는 것이다. 이같은 층형성은 목적하는 층수에 맞게 반복적을 행한다.One layer is formed by a circuit inspection process in the insulating layer forming process, and the present invention is directly performed by a build-up method on the heat sink. Such layering is repeated according to the desired number of layers.

또한, 본 발명에서는 목적하는 층수에 맞게 회로를 형성한 후 최상층에 솔더레지스트(S/R)를 인쇄하고 통상 공정으로 가공 및 검사하는 과정을 거친다.In addition, in the present invention, after forming a circuit in accordance with the desired number of layers, the solder resist (S / R) is printed on the uppermost layer and subjected to a process of processing and inspection in a normal process.

상기 솔더레지스트의 인쇄후에는 도금, V-컷(Cut), 수세, 검사, 건조 등의 통상 공정을 거친다.After the printing of the solder resist is subjected to the usual processes such as plating, V-cut, water washing, inspection, drying.

이상 설명한 바와 같이, 본 발명은 기존의 공법인 방열판을 나중에 붙이는 것에 반하여, 방열판 위에 빌드업 방식인 RCC(Resin Coated Copper foil), 열경화성 잉크를 코팅하여 레이저 비어(Laser Via)방식 및 기계적(Mechanical)방식으로 홀을 형성하거나, 포토비어(Photo Via)형성용 수지잉크(Resin Ink)코팅을 행한 후, 열경화성 잉크 및 포토비아 잉크위에 에디티브 방식으로 도금을 진행할 수 있다. 이로 인해 회로 형성시 파인패턴으로의 형성이 가능한 것이다.As described above, the present invention is to attach a heat sink, which is a conventional method, later, the build-up method Resin Coated Copper foil (RCC), a thermosetting ink is coated on the laser via (Laser Via) and mechanical (Mechanical) method After the hole is formed or the resin ink coating for forming the photo via is performed, plating may be performed on the thermosetting ink and the photo via ink in an additive manner. Therefore, it is possible to form a fine pattern when forming a circuit.

즉, 기존 표면 Cu두께가 25-30μm정도인 것에 반하여, 본 발명에서는 에디티브법의 적용으로 표면 Cu두께를 20-25μm로 낮게 유지할 수 있어, 파인페턴회로 형성이 가능한 것이다.That is, while the existing surface Cu thickness is about 25-30 μm, the surface Cu thickness can be kept low at 20-25 μm by the application of the additive method, and thus the fine pattern circuit can be formed.

이하, 실시예를 통하여 본 발명을 보다 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.

실시예Example

하기와 같은 제조프로세스를 통하여 빌드업방식으로 4층의 M-BGA를 제조한 후, 이를 기존 방식에 의한 4층의 S-BGA와 E-BGA와 비교하였다.After manufacturing the four-layer M-BGA by the build-up method through the manufacturing process as follows, it was compared with the four-layer S-BGA and E-BGA by the conventional method.

[Cu 금속(방열판)에 기준홀 형성]→ [내층회로형성(방열판)]→ [Ni플래이팅]→ [흑화처리(Oxide)]→ [1층레진코팅(열경화성잉크)]→ [비어홀형성(레이져)]→ [조화처리(Texturing)]→ [도통용 Cu플래이팅]→ [회로형성]→ [회로검사]→ [2층레진코팅(열경화성잉크)]→ [비어홀형성(레이져)]→ [조화처리(Texturing)]→ [도통용 Cu플래이팅]→ [회로형성]→ [회로검사]→ [3층레진코팅(열경화성잉크)]→ [비어홀형성(레이져)]→ [조화처리(Texturing)]→ [도통용 Cu플래이팅]→ [회로형성]→ [회로검사]→ [4층레진코팅(열경화성잉크)]→ [비어홀형성(레이져)]→ [조화처리(Texturing)]→ [도통용 Cu플래이팅]→ [회로형성]→ [회로검사]→ [S/R인쇄]→ [금도금]→ [V-컷]→ [단 피스(Piece)수세]→ [최종검사]→ [건조][Reference hole formation in Cu metal (heat sink)] → [Inner circuit formation (heat sink)] → [Ni plating] → [Blackening (Oxide)] → [ 1 layer resin coating (thermosetting ink)] → [Beer hole formation ( Laser)] [Texturing] → [Conducting Cu Plating] → [Circuit Formation] → [Circuit Inspection] → [ 2 Layer Resin Coating (Thermosetting Ink)] → [Beer Hole Formation (Laser)] → [ [Texturing] → [Conducting Cu Plating] → [Circuit Formation] → [Circuit Inspection] → [ 3 Layer Resin Coating (Thermosetting Ink)] → [Beer Hole Formation (Laser)] → [Texturing] ] → [Conducting Cu Plating] → [Circuit Forming] → [Circuit Inspection] → [ 4 Layer Resin Coating (Thermosetting Ink)] → [Beer Hole Formation (Laser)] → [Texturing] → [Conducting] Cu Plating] → [Circuit Formation] → [Circuit Inspection] → [S / R Printing] → [Gold Plating] → [V-Cut] → [Single Piece Wash] → [Final Inspection] → [Drying]

상기한 바와 같은 프로세스를 통하여 제조된 M-BGA와 기존의 방법에 의해 제조된 S-BGA와 E-BGA를 비교하였다. 비교결과 열적특성은 유사하였다.The M-BGA produced through the process as described above was compared with the S-BGA produced by the conventional method and the E-BGA. In comparison, the thermal characteristics were similar.

하지만, 상기 프로세스에서도 알 수 있는 바와 같이, 제조공정이 기존의 S-BGA나 E-BGA와 비교하여 매우 간단하여 제조비용이 20-30%정도 저렴하였다.However, as can be seen from the above process, the manufacturing process is very simple compared to the existing S-BGA or E-BGA and the manufacturing cost is about 20-30% cheaper.

또한, 상기 본 발명의 제조프로세스를 적용하여 표면 Cu두께를 20μm로 하여 M-BGA를 제조하여 보았다. 제조후 특성을 평가한 결과 우수하였는데, 이는 본 발명의 방법을 적용하면 보다 파인패턴으로의 회로 형성이 가능함을 보이는 것이다.In addition, M-BGA was prepared by applying the manufacturing process of the present invention to a surface Cu thickness of 20 μm. Evaluation of the post-fabrication characteristics was excellent, which shows that the circuit of the fine pattern can be formed by applying the method of the present invention.

상술한 바와 같은 본 발명에 의하면, BGA패키지기판의 제조시 빌드업공법을 적용함으로서, 열적특성이 기존의 S-BGA 및 E-BGA에 뒤떨어지지 않으면서도 적층하는 공정이 생략되어 전체적인 제조공정이 간단해져 소요되는 비용이 절감되는 효과가 제공될 뿐만아니라, 파인패턴 회로형성이 가능한 효과가 제공된다.According to the present invention as described above, by applying the build-up method for manufacturing the BGA package substrate, the overall manufacturing process is simplified because the lamination process is omitted without the thermal characteristics are inferior to the existing S-BGA and E-BGA In addition to reducing the cost required, it is possible to provide a fine pattern circuit.

Claims (2)

방열판에 기준홀 및 내층회로를 형성하는 1단계; 상기 방열판 위에 완충작용을 위한 플래이팅(Plating)처리를 행하고 흑화처리를 행하는 2단계; 회로 형성을 위한 절연층을 형성하는 3단계; 비어홀을 형성하고 조화처리(Texturing)를 행하는 4단계; 도통을 위한 도금을 행하는 5단계; 회로를 형성하고 형성된 회로를 검사하는 6단계; 목적하는 층수에 맞게 상기 3단계에서 6단계까지의 과정을 반복하는 7단계; 목적하는 층수에 맞게 회로를 형성한 후 최상층에 솔더레지스트를 인쇄하고 통상 공정으로 가공 및 검사하는 8단계;를 포함하는 것을 특징으로 하는 M-BGA패키지 기판의 제조방법Forming a reference hole and an inner layer circuit in the heat sink; Performing a plating process for buffering on the heat sink and performing a blackening process; Forming an insulating layer for forming a circuit; Four steps of forming a via hole and performing texturing; 5 steps of plating for conduction; Forming a circuit and inspecting the formed circuit; 7 steps of repeating the process from step 3 to step 6 according to the desired number of floors; Forming a circuit in accordance with the desired number of layers after the step of printing a solder resist on the top layer and processing and inspection in a normal process; manufacturing method of M-BGA package substrate comprising a 제 1 항에 있어서,The method of claim 1, 상기 방열판은 재질이 Cu 또는 Al인 것임을 특징으로 하는 M-BGA패키지 기판의 제조방법The heat sink is a manufacturing method of the M-BGA package substrate, characterized in that the material is Cu or Al
KR1019990057841A 1999-12-15 1999-12-15 A Method for Manufacturing Metal-BGA Package Substrate KR100344618B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7408261B2 (en) 2004-07-26 2008-08-05 Samsung Electro-Mechanics Co., Ltd. BGA package board and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7408261B2 (en) 2004-07-26 2008-08-05 Samsung Electro-Mechanics Co., Ltd. BGA package board and method for manufacturing the same

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