KR20010055548A - Apparatus for UTOPIA management interface in ADSL PCI card - Google Patents

Abstract

PURPOSE: A utopia management interface apparatus of an ADSL(Asymmetric Digital Subscribe Line) PCI(Peripheral Component Interconnect bus) card is provided to realize logic and timing of UTOPIA management bus of an ADSL chip set and a utility bus of a micro SAR(Segmentation And Reassembly). CONSTITUTION: A PCI(Peripheral Component Interconnect bus) interface(10) performs interface with a PCI bus. A micro SAR(Segmentation And Reassembly)(20) is connected with the PCI interface(10), controls run-time motion of an AAL(ATM Application Layer) SAR and an ATM layer, and transmits data as a host system and a PCI bus master of a PC. A plurality of memories(30-50) are connected with the micro SAR(20) for storing data. A control conversion part(60) connects the micro SAR(20) with an ADSL PHY(70) without voltage conversion, and performs data transmission between the micro SAR(20) and the ADSL PHY(70). The ADSL PHY(70) is connected with the control conversion part(60) for performing ADSL PHY function.

Description

Apparatus for UTOPIA management interface in ADSL PCI card

The present invention relates to a Utopia management interface device for an Asymmetric Digital Subscriber Line (ADSL) Peripheral Component Interconnect bus (PCI) card. In particular, the present invention provides a connection to a PCI interface in an implementation of an ADSL PCI modem card. The present invention relates to a utopia management interface device of an ADSL PCI card, which is suitable for implementing a PCI card using a connected micro segment (Segmentation And Reassembly).

The present invention can be applied to an xDSL system such as an ADSL system, a very high-speed digital subscriber line (VDSL), and a high-speed digital subscriber line (HDSL).

Conventional PCI cards often implement PCI cards using the physical layer and micro SAR. In addition, in order to implement micro SAR using ADSL chipset with IDMA (Internal Direct Memory Access) port, it is not possible to use the existing commercially available micro SAR directly but by designing a complex function and implementing it as an ASIC (Applicable Specific Integrated Circuit). .

1 is a block diagram of a conventional ADSL PCI card.

Where 1 is a PCI interface, 2 is a controller and UTOPIA block, 3 is Static Random Access Memory (SRAM), 4 is Programmable ReadOnly Memory (PROM), and 5 is Electrically Erasable and Programmable Read Only Memory (EEPROM). And 6 is an ADSL PHY.

As a result, commercially available micro-SARs have an 8-bit address / data utility bus that cannot be directly connected to the IDMA 16-bit address / data bus that currently uses the IDMA port to control between the ADSL chipset and the controller (2). By implementing the micro SAR function, a 16-bit address / data bus can be created to implement glueless logic, or switched to 3.3V logic to create an ADSL PCI modem card.

However, this conventional technology has a problem that must be unconditionally ASIC, it is difficult to implement easily, if not mass production can not only bear a large price burden, and also has a problem that can not lower the PCI card price.

Therefore, the present invention has been proposed to solve the conventional problems as described above, an object of the present invention is to implement a PCI card using a micro SAR connected to the PCI interface and connected to the ADSL physical layer in the implementation of the ADSL PCI modem card To provide a Utopia management interface device of the ADSL PCI card can be implemented.

In order to achieve the above object, the Utopia management interface device of the ADSL PCI card according to the present invention,

A PCI interface that interfaces with the PCI bus; A micro SAR connected to the PCI interface, controlling run time operations of the AAL SAR and the ATM layer, and performing data transmission to the host system of the PC and the PCI bus master; A memory coupled to the micro SAR to perform a data storage function; A control conversion unit for allowing the micro SAR and the ADSL PHY to be connected without voltage conversion and performing data transmission between the micro SAR and the ADSL PHY; It is characterized in that the technical configuration consisting of the ADSL PHY connected to the control conversion unit performs an ADSL PHY function.

1 is a block diagram of a conventional ADSL PCI card,

Figure 2 is a block diagram of a utopia management interface device of the ADSL PCI card according to an embodiment of the present invention,

3 is a detailed block diagram of a control conversion unit and an ADSL PHY in FIG.

4 is a table of timing diagrams and input / output parameter values of FIG.

FIG. 5 is a timing diagram for receiving an output according to FIG. 2 from an ADSL chipset. FIG.

FIG. 6 is a detailed block diagram of the control conversion unit in FIG. 2;

7 is a detailed circuit diagram of FIG. 6;

8 is a timing diagram of FIG. 6.

<Explanation of symbols for main parts of the drawings>

10: PCI interface 20: micro SAR

30: SRAM 40: PROM

50: EEPROM 60: control converter

70: ADSL PHY

Hereinafter, an embodiment according to the technical idea of the utopia management interface device of the present invention ADSL PCI card as follows.

First, micro SAR is used as PCI ATM controller in ATM (Asynchronous Transfer Mode) network. Micro SAR is used for PCI card because it implements ATM Application Layer (AAL) SAR function, and it is used as PCI card in connection with ATM physical layer.

Connecting these micro SARs to the ADSL physical layer creates an ADSL PCI card.

In case of ADSL modem system based on general ATM, not only ATM-based ADSL modem is required but also ATM card that needs to be embedded in PC has a problem that it is expensive. You do not need a card. Ethernet-based ADSL modems are less expensive than ATM cards, but also have the inconvenience of buying or using with modems. Therefore, there are many attempts to implement a PC built-in ADSL card.

2 is a block diagram of a utopia management interface device of an ADSL PCI card according to an embodiment of the present invention.

As shown therein, the PCI interface 10 performing an interface with the PCI bus; A micro SAR (20) connected to the PCI interface (10) for controlling the run-time operation of the AAL SAR and the ATM layer and performing data transmission to the host system of the PC and the PCI bus master; A memory 30 to 50 connected to the micro SAR 20 to perform a data storage function; A control conversion unit (60) for allowing the micro SAR (20) and the ADSL PHY (70) to be connected without voltage conversion and performing data transmission between the micro SAR (20) and the ADSL PHY (70); The ADSL PHY 70 is connected to the control converter 60 to perform an ADSL PHY function.

FIG. 6 is a detailed block diagram of the control converter of FIG. 2.

As shown therein, a latch converting unit (61) for performing a latch conversion between the micro SAR (20) and the ADSL PHY (70); A write conversion unit (62) for performing a write conversion between the micro SAR (20) and the ADSL PHY (70); A read conversion unit (63) for performing read conversion between the micro SAR (20) and the ADSL PHY (70); A delay unit (64) for performing a signal delay between the micro SAR (20) and the ADSL PHY (70); And an address / data conversion unit 65 that performs address / data conversion between the micro SAR 20 and the ADSL PHY 70.

The control conversion unit 70 interfaces with the utility bus and the IDMA bus of the ADSL PHY 70.

The operation of the utopia management interface device of the ADSL PCI card according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the logic and timing for connecting a micro SAR having a 5V drive and an 8-bit address / data utility bus to an ADSL DSP drive block having a 16-bit address / data IDMA bus is a control programmable logic unit CPLD (Complex Programmable Logic Device). ) Using the 3.3V CPLD is used to connect between 5V and 3.3V. When the output is 5V, pull-up is available to drive 5V, eliminating the need for separate 5V and 3.3V connection logic in the modem card. It became.

The micro SAR address and data coming in by 8 bits are latched until they become 16 bits, and when they become 16 bits, they are sent to the IDMA interface at the same time for timing using a buffer.

In the case of UTOPIA (Universal Test and Operations Physical Interface for ATM) interface, transmission data (TXDATA) sent from 3.3V to 5V is transmitted through EPLD (Electrically Programmable Logic Devices) so that a separate voltage conversion circuit is not required.

A reset of the micro SAR is used to drive an ADSL chipset reset.

On the PCI interface of the micro SAR, 32-bit addresses / data are connected directly and connected to the SRAM for receive access cables and receive buffers.

Referring to the operation of the present invention in more detail as follows.

The present invention is a modem technology for delivering a communication service through a high speed broadband network to a subscriber as a technology for a subscriber modem PCI card in an ADSL modem broadband network access system.

An important feature of the ADSL system is that it can provide high-speed digital services simultaneously without interfering with analog telephone service (POTS) over existing twisted pair copper networks.

This is a technology that increases bandwidth to simultaneously transmit multimedia information such as voice, graphics, and video while using existing telephone lines. Therefore, it is gaining attention as a service network that can deliver multimedia information to subscribers without incurring network installation costs.

As a result, new services can be created that can be provided to telephone subscribers such as high-speed Internet, online and telecommuting, and Video on Demand (VOD). In addition, there is no need to install a new line, so it is possible to implement the service more economically and faster than using other systems.

2 is a block diagram of a utopia management interface device of an ADSL PCI card according to an embodiment of the present invention.

Therefore, ADSL PCI modem card has advantages such as flexibility of bandwidth used and ATM service based on various traffic characteristics.

The micro SAR controls the run-time operation of all AAL SAR and ATM layers, and performs all data transfers with the PC's host system and the PCI bus master. The device driver provides the micro SARs with buffers and control descriptors during runtime. Upon receiving the cell, the micro SAR performs a table lookup using the connection number received from the cell header to determine the storage location of the cell payload in host memory. The ATM cell payload received from the network is stored in the host memory to form a Convergence Sublayer-Protocol Data Unit (CS-PDU).

When transmitting a cell, the micro SAR proceeds with a schedule table entry and determines a service class and an access number to proceed. It segments one ATM cell and sends it to the UTOPIA bus.

Micro SAR supports Constant Bit Rate (CBR), Variable Bit Rate (VBR), Available Bit Rate (ABR), Unspecified Bit Rate (UBR) in hardware, and provides a full Quality of Service (QOS).

The micro-SAR features full-duplex SAR support up to 155Mbps wire speeds, ATM layer protocol functionality, and stand-alone SAR. It supports AAL5 and AAL3 / 4 ATM cell formats, AAL0 and RAW cell formats, and plugs directly into 32-bit / 33 MHz PCI buses and UTOPIA-compliant PCI-TC.

Micro SAR operates on systems with large host local Dynamic Random Access Memory (DRAM) memory and high-speed buses to perform SAR with the CPU local memory model.

When using a PCI bus such as a desktop PC or workstation, the access speed between the CPU and local DRAM is much faster than the speed between the CPU and peripherals, so the micro SAR ensures that all data and large control structures are moved to the PCI bus master block whenever possible. It is.

FIG. 3 is a detailed block diagram of the control conversion unit and the ADSL PHY in FIG. 2, showing a UTOPIA management bus and a UTOPIA bus.

In case of reception, it works as follows.

Before reassembly begins, the device driver must provide the micro SAR with host memory locations (buffers) used for reassembling ATM cell payloads as CS-PDUs.

The starting address of each buffer (free buffer) used for reassembly must be stored in the free buffer queue in SRAM. All other data is initialized during reassembly. Next, the device driver enables reception of the micro SAR, and the micro SAR stores the ATM cell arriving on the UTOPIA bus of the micro SAR as an RX FIFO in the SRAM. Here the HEC byte is controlled and only 52 bytes are passed to the RX FIFO.

The micro SAR forms a connection with reference to the contents of the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) fields of the ATM cell header. The VPI / VCI field of the ATM cell is used to index the receive access cable.

The micro SAR loads the pre-buffer descriptor into the receive connection table.

The micro SAR patches the prebuffer descriptor from the prebuffer queue and then moves the buffer descriptor to the connection cable. The free buffer descriptor points to the host memory location to reassemble the receive payload.

The micro SAR moves the 48-byte ATM cell payload to a specific free buffer location via PCI bus master data transfer.

In the case of transmission, it operates as follows.

When sending a cell, the micro SAR fetches the cell payload from the host memory. Once the cell payload is fetched and formed into a complete ATM cell, it is stored in the transmit queue to provide a buffer for PCI latency. Once the CS-PDU is transmitted, a transmission status is generated.

The first step in the segmentation cycle is the device driver initializes the transmit data structure. The device driver then turns on the transmitter, and once the transmitter is turned on, the micro SAR starts the segmentation process as it proceeds through the transmission schedule table entry.

The micro-SAR exports the address / data utility bus by 8 bits and accepts 16 bits on the ADSL chipset. Therefore, the micro SAR reads data once from the ADSL for two write cycles, and the micro SAR is divided into two times to receive data once written to the ADSL. At this time, the address and the data are latched in the middle so that data transfer occurs without collision.

The timing diagrams for this are FIGS. 4A and 4B, and FIGS. 4C to 4E are table values thereof. So in the write cycle, the micro SAR is addressed and the data is given back. In the case of read cycles, data is received after the address is given.

FIG. 5 is a timing diagram of receiving the output according to FIG. 2 from the ADSL chipset, FIG. 5A is a timing diagram of an IDMA address latch, FIG. 5B is a timing diagram of IDMA read and short read cycles, and FIG. 5A is an IDMA write and short. A timing diagram of write cycles.

In the IDMA address latch cycle, IACK * drops, the IAL signal goes high, and the IS * signal goes low. IAL and IS * are created through simple logic from the ALE and CS * signals of the micro SAR.

When data is sent out during the write cycle in the micro SAR, the data is read in the read cycle in IDMA. When the IS * and IRD * signals go low, the read cycle begins. IRD * signals are made from the RD of the micro SAR.

When a micro SAR enters a read cycle, it writes data out of the write cycle, and the write cycle begins when the IS * and IWR * signals go low. The IWR * signal is made from the WR signal.

6B is a detailed block diagram of the input / output signal of the control converter in FIG. 2, FIG. 6B is a detailed block diagram of FIG. 6A, FIG. 7 is a detailed circuit diagram of FIG. 6B, and FIG. 8 is a timing diagram of FIG.

So the address / data coming from the micro SAR and the address / data signals of the IDMA port are once latched to an edge triggered D flip-flop. This prevents address and data conflicts that can occur in order to achieve one 16-bit cycle every two cycles.

In the read and write cycles, the data paths were set aside and the buffer was opened to allow data to exit when the read and write signals came in.

Referring to the timing chart of Fig. 8, the timing that satisfies both the read cycle and the write cycle from the micro SAR is shown. And we can see that we are satisfied with the light and lead cycle of IDMA port. Thus, a simple CPLD can be used to interface a 16-bit data / address IDMA bus using a commercially available micro SAR.

As described above, the present invention implements the PCI card using the micro SAR connected to the ADSL physical layer by connecting to the PCI interface in the implementation of the ADSL PCI modem card.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. In other words, in the present invention, the present invention is applied to the ADSL broadband subscriber PCI modem card system, but in addition to the VDSL and HDSL network access systems, a system having one broadband access link such as subscriber modem such as digital subscriber access equipment such as xDSL, etc. It is a technology that can be applied and implemented, and it is applied to a system that wants to configure a modem economically, simply and flexibly. And the utility bus can be easily implemented in any circuit connecting 8 and 16 bits. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the Utopia management interface device of the ADSL PCI card according to the present invention is formed by considering the efficiency and economic efficiency of the system configuration as much as possible, and uses an IDMA port using a micro-SAR which is widely used in a commercially available PCI card. The logic implementation and timing of the UTOPIA management bus of the ADSL chipset and the utility bus of the micro SAR are realized.

In addition, the present invention realizes the interface with the chipset using the IDMA port among the ADSL chipset by using the micro SAR, which is easily available and is widely used as a PCI card, and enables an additional complicated micro SAR function and 16-bit address / data IDMA port address. It also has the effect of lowering the price, which is an important factor in PCI cards.

Therefore, not only the functionality and the economic effect are very large, but also there is an industrial use effect that can be applied to the xDSL network subscriber modem card that the demand and service are rapidly being created in recent years.

Claims (3)

A PCI interface that interfaces with the PCI bus; A micro SAR connected to the PCI interface, controlling run time operations of the AAL SAR and the ATM layer, and performing data transmission to the host system of the PC and the PCI bus master; A memory coupled to the micro SAR to perform a data storage function; A control conversion unit for allowing the micro SAR and the ADSL PHY to be connected without voltage conversion and performing data transmission between the micro SAR and the ADSL PHY; Utopia management interface device of the ADSL PCI card, characterized in that the ADSL PHY connected to the control conversion unit configured to perform the ADSL PHY function. The method of claim 1, wherein the control conversion unit, A latch conversion unit for performing a latch conversion between the micro SAR and the ADSL PHY; A write conversion unit performing a write conversion between the micro SAR and the ADSL PHY; A read conversion unit performing read conversion between the micro SAR and the ADSL PHY; A delay unit for performing a signal delay between the micro SAR and the ADSL PHY; Utopia management interface device of the ADSL PCI card, characterized in that the address / data conversion unit for performing the address / data conversion between the micro SAR and the ADSL PHY. The method of claim 1, wherein the control conversion unit, Utopia management interface device of the ADSL PCI card, characterized in that the interface using the utility bus and IDMA bus of the ADSL PHY.