KR20010055219A - Full detection and management method of message buffer using DPRAM - Google Patents

Abstract

PURPOSE: A method for sensing and managing message buffer pull using a dual port ram is provided to instantly sense buffer full by transmitting and receiving control information between a master board and a slaver board via a DPRAM and reduce load of a processor by reporting buffer full or termination mutually. CONSTITUTION: Functions of a master board and a slaver board are initialized(S310). The master board is operated as master basic functions of sensing obstacles and managing the slaver board, transmitting a message to the slaver board, and receiving the message from the slaver board(S320-S323). The master board confirms the method for sensing buffer full in methods 1 and 2 before transmitting the message(S330). If method 1 is set up, the master board reads current transmission buffer write pointer(TXWP) in a control information area for confirming whether buffer flag of the corresponding write pointer is empty(S340). If empty, the master board stores the message in a transmission buffer indicated by the TXWP and changes the flag from empty to use(S390). The master board increases the value of the TXWP and changes the TXWP value with a transmission starting address(TXSA)(S391). If not empty, the master board generates transmission buffer full interrupt to the slaver board(S370) and waits in idle state(S371). If the master board receives buffer full termination interrupt(S380), the master board reopens message transmission. If method 2 is set up, the master board reads transmission buffer and read and write pointers and calculates the number of the empty buffers for calculating buffer full degree(S350). The master board compares the set reference value with the buffer full degree for judging buffer full(S360).

Description

Full detection and management method of message buffer using DPRAM}

In the present invention, a board dedicated to message communication between processors performing call processing and operation functions of an ATM switch and two boards using dual port random access memory (hereinafter referred to as DPRAM) as between main processors. In the case of operating a message buffer, the present invention relates to the full detection and management of the message buffer.

Conventionally, when using dual port memory as a message buffer between two boards, the full buffer of the message buffer is detected when the message is not processed in the buffer of the current buffer pointer and the buffer is not empty. The processor must wait until the buffer is available. Therefore, since the processor detects the buffer pool and needs to periodically poll the state of whether the buffer is empty until the buffer is available, the processor is overloaded. While the processor is polling for the status of the buffer, no applications can be run that are not related to sending messages, which degrades the overall performance of the system. In addition, since the buffer pool can be detected only when the buffer is a full pool (100%), even when the buffer pool is released, the message buffer pool may be continuously generated when multiple messages are transmitted. Therefore, even if it is not a full pool, when it is close to the buffer pool, it should be informed that it is close to the buffer pool to adjust the transmission rate of the message.

An object of the present invention to solve the above-mentioned problems is to reduce the idle time of the processor by reporting the instantaneous detection of the buffer pool and reporting the buffer pool's cancellation status without the processor load, when the two boards deliver messages through the DPRAM. It provides a method for detecting and managing the pool of message buffers using dual port memory.

1 is a configuration diagram of two boards having a DPRAM interface

2 is a data structure diagram of a DPRAM

3 is a flowchart illustrating a method of detecting and releasing a transmission buffer pool of a DPRAM according to the present invention.

4 is a flowchart illustrating a method of detecting and releasing a receiving buffer pool of a PRAM according to the present invention.

In order to achieve the above object, the present invention utilizes hardware resources such as DPRAM and interrupts to operate a software-efficient message buffer.

To this end, DPRAM not only transfers messages between the two boards, but also transmits and receives control information, and operates the DPRAM structure for transmitting and receiving buffer areas and buffers so that the buffer pool can be detected only by DPRAM information in the message sending / receiving routines. It consists of a control information area that stores a pointer and an address, and each buffer includes a flag area indicating the status of the message buffer.

In addition, the interrupt is used to immediately notify the other board of the buffer pool generation and the buffer pool cancellation status, thereby disconnecting or resuming message communication. Thus, the master and slaver boards do not constantly check the buffer pool and revocation status, reducing the CPU load.

In addition, the present invention provides two methods for detecting the buffer pool. One is to detect as a buffer pool only when the buffer is full, and the other is to detect as a buffer pool if the buffer pool is above a certain value (eg 70 ~ 90%).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a hardware configuration according to an embodiment of the present invention.

As shown in the figure, it consists of a master board (110) for call processing and operation of the ATM switching system and a slaver board (120) dedicated to communication between processors, and the two boards are PCI (Peripheral). Component Interconnect) connected to the bus interface 131 to transfer messages using the DPRAM 123 and the interrupt 113 and 124 resources in the slave board 120.

In addition, the DPRAM 123 may be accessed (112, 122) by the master board CPU 111 and the slave board CPU 121.

FIG. 2 is a structural diagram of a DPRAM proposed in the present invention to reduce the load of a processor according to buffer pool sensing in message communication between two boards configured as shown in FIG. 1.

As shown in the figure, the DPRAM is composed of three control information areas 210, 220 and 230 and two message circular buffers 211 and 221. The control information area-1 210 is an area for storing control information of the message transmission buffer 240, and the control information area-2 220 is an area for storing control information of the message receiving buffer 250, and the control information. Area-3 230 is an area for storing control information related to interrupts.

The message circular transmission buffer 240 is composed of N buffer entries, and the message circular reception buffer 250 is composed of M buffer entries, and operates circularly. Each entry of the message prototype transmit / receive buffers 240 and 250 is composed of a head information area, a message data area and a flag area.

The head information area has control information of the message, the data area is the content of the message to be delivered, and the flag area is indicated by the state of the send / receive buffer, that is, use (empty) or empty (empty). Therefore, if the buffer flag is empty, copy the message and then use it. If the buffer flag is use, read the message from the buffer and change it to empty.

Each buffer has a base address, an end address, a read pointer, and a write pointer for use in the master and slaver boards. Have

TXBA, TXRP, TXWP and TXEA are the start address, read pointer, write pointer, and end address of the transmission buffer 240, respectively, and are stored in the control information area-1 210. RXBA, RXRP, RXWP, and RXEA are the start address, read pointer, write pointer, and end address of the reception buffer 250, respectively, and are stored in the control information area-2 (220).

The start address (RXBA, TXBA) and end address (RXEA, TXEA) are set at initialization and do not change. They are needed to calculate the start and end of the buffer when operating in a circular fashion. Read pointers (RXRP, TXRP) are buffer pointers used by master and slaver boards to take messages from buffers, and write pointers (RXWP and TXWP) are buffer pointers used to copy messages to buffers.

TXRP and RXWP are buffer pointers used / managed by the CPU 121 of the slaver board. TXWP and RXRP are buffer pointers used / managed by the CPU 111 of the master board.

For example, in the case of the transmission buffer 240, in the transmission buffer 240, a message to be transmitted by the slave board 120 from transmission buffer entry 3 to entry N-2 is stored, and transmission buffer entry N -1), N, 1, 2 are empty buffers. In the case of the receiving buffer 250, a message to be received by the master board 110 is stored from the receiving buffer entry 2 to the entry M-2, and the receiving buffer entries M-1, M, and 1 are buffers. Is empty.

In the master board 110, the current message transmission pointer is TXWP, and the message reception pointer is RXRP. On the slaver board, the current message send pointer is TXRP and the message receive pointer is RXWP.

3 shows the operation flow of the master board side mainly on the mesh transmission to the slaver board.

First, the master board operation is started to initialize the function of the master board, and initializes the function of the slaver board to start the operation of the slaver board (S310).

After initialization, the master board 110 operates as a master basic function (S320), and the master board 110 sends a message to the failure detection and status management function of the slaver board 120 (S321) and the slaver board 120. It has three master basic functions: a transmission function (S322) and a message reception function (S323) from the slaver board (120).

Here, only the message transmission function to the slaver board 120 according to the present invention will be described.

In order for the master board 110 to transmit a message, first, it is necessary to check whether the transmission buffer 240 is full.

In the present invention, there are two methods for detecting the buffer pool.

Both methods use the control information of the transmission buffer stored in the control information area-1210. Method 1 checks whether the buffer flag indicated by the write buffer (RXWP) of the send buffer is empty, and method 2 calculates the number of free buffers in the read and write pointers (RXRP, RXWP) of the send buffer and pulls the buffer. The degree is calculated and compared with the set reference buffer pool to determine whether or not the buffer pool.

Method 1 detects only when the buffer is a full pool, and method 2 determines whether or not the buffer pool is based on the buffer pool set (for example, 80% or 90% buffer pool). The choice of methods 1 and 2 and the degree of buffer pool in method 2 can be set by the user.

Therefore, before transmitting the message, the master board 110 checks whether the buffer pool sensing method is set to one of methods 1 and 2 (S330).

If the result of the check is set to the method 1, the current transmission buffer write pointer RXWP is read from the control information area-1 210 to check whether the buffer flag of the write pointer is empty (S340).

As a result, if it is empty, it is not a buffer pool, so the message is stored in the transmission buffer indicated by the transmission buffer write pointer TXWP, and the flag is changed from empty to use (S390). If the value of the transmit buffer write pointer TXWP is increased and larger than the end address TXEA, the value of the write pointer TXWP is changed to the value of the start address TXSA (S391).

However, if the result of checking the buffer flag in step S340 is not empty, that is, it is in the current buffer pool state, the message cannot be transmitted until the buffer is empty. Therefore, the master board generates a transmit buffer full interrupt to the slaver board (S370), and waits in the idle state (S371).

On the other hand, the slaver board 120 receiving the transmit buffer full interrupt generated in step S370 reads the message of the transmit buffer (this is seen from the master board side, and from the slave board side, it is the receive buffer) and reads the buffer. After emptying, the buffer pool cancellation interrupt is generated to the master board 110.

Accordingly, when the master board 110 receives the buffer pool canceling interrupt from the slave board 120 (S380), as described above, steps S390 and S391 are performed to resume message transmission.

On the other hand, as a result of checking the buffer pool detection method in step S300, if the method 2 is set, the read and write pointers (RXRP, RXWP) of the transmission buffer are read from the control information area-1 210, and the number of empty buffers is calculated and buffered. Calculate the degree of pooling. After that, it is determined whether or not the buffer pool is compared by setting the reference value and the buffer pool degree (S360). For example, if the reference value is 90%, if the calculated buffer pool is over 90%, it is detected as a buffer pool.

As a result of the determination, the operation in the case of the buffer pool and the case of the non-buffer pool is the same as in the case where the method for detecting the buffer pool described above is Method 1.

Figure 4 shows the operation flow of the slaver board centered on the message transmission to the master board.

Operation of the slaver board is started to initialize the slaver board 120 and notify the master board of the completion of initialization (S410).

After initialization, the slaver board 120 operates as a slave function (S320), and the slaver board 120 receives control information from the master board, the slaver board state management and fault detection function (S421), and the master board. Low message reception function (S422), Slave basic function of the message transmission function from the master board (S423).

Here, only the message transmission function to the master board 110 according to the present invention will be described.

The slaver board 110 checks whether the message receiving buffer of DPRAM (which is seen from the master board side and the transmission buffer from the slaver board side) is empty to transfer the received message to the master board 120. You need to check if it is a buffer pool.

Like the send buffer, the receive buffer has two ways to detect the buffer pool. Method 1 detects the buffer pool only when the receiving buffer is completely full, and Method 2 calculates the buffer pool of the receiving buffer and detects it as the buffer pool if it is above the reference value.

Therefore, the slave board 120 checks whether the buffer pool sensing method is one of methods 1 and 2 before transmitting the message (S430).

If the result of the check is the method 1, it is checked whether the flag of the buffer indicated by the current reception buffer write pointer RXWP of the control information area-2 220 is empty (S440). When the buffer pool detection method is Method 2, when the buffer pool detection method is the method 2, the buffer pool is calculated by calculating the number of empty buffers with the reception buffer write pointer (RXWP) and the read pointer (RXRP). After (S450), it is determined whether or not the buffer pool by comparing the calculated value and the reference value (S460).

When the buffer flag is not empty in step S440, when the value of the buffer pool calculated in step S460 is greater than or equal to the reference value, each of the buffer pools is detected.

When the buffer pool is detected in step S440 or step S460, the slaver board 120 generates a receive buffer pool interrupt to the master board 110 (S470) and waits in an idle (sleep) state (S471).

After receiving the receive buffer pool interrupt, the master board 110 receives the message and makes the buffer empty, and then generates a buffer pool cancellation interrupt to the slaver board 120.

If the result of the check in step S440 or step S460 is not a buffer pool or a buffer pool release interrupt occurs from the master board 110 (S480), the message is stored in the reception buffer indicated by the reception buffer write pointer (RXWP) and the flag is empty. Change to use (S490). When the value of the write pointer RXWP is increased and greater than the end address RXEA, the value of the write pointer RXWP is changed to the value of the start address RXSA to terminate message transmission (S491).

As described above, the present invention immediately detects a pool of buffers by interrupting buffer pool and revocation by sending and receiving control information as well as transfer of messages between two boards through DPRAM without additional hardware circuitry or buffer pool detection process. By reporting to each other, the processor load can be reduced. In the case of the buffer pool, it also provides flexible message communication by disconnecting the message transmission and resuming the message transmission when the buffer pool state is released. Therefore, the present invention can be effectively applied to a method of managing a message buffer between two boards having a DPRAM interface.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (5)

In case of operating message buffer between two boards using dual port memory, The dual port memory used as the message buffer is composed of an area for storing control information of a transmission buffer, an area for storing control information of a reception buffer, an area for storing interrupt control information, a message transmission buffer, and a message reception buffer. Each buffer entry in the transmit / receive buffer contains a flag area indicating the buffer's state (use / empty), Messages using dual port memory, characterized by transmitting and receiving control information as well as messages through the dual port memory, detecting a buffer pool using only the control information of the dual port memory, and managing the message transmission / reception buffer by processing the buffer pool. How pools are detected and managed. The method of claim 1, The message send / receive buffer of the dual port memory is managed in a circle, and as the control information for managing the message send / receive buffers on both boards, the start address, the end address, the read pointer and the write pointer of the send / receive buffer are stored. Method for detecting and managing a pool of message buffers using dual port memory. The method of claim 2, The buffer pool detection of the message send / receive buffer is a method of detecting and managing a pool of message buffers using a double fork memory, characterized in that by detecting the flag of the buffer pointed to by the current write pointer to detect the buffer pool if not empty. The method of claim 2, The buffer pool detection of the message send / receive buffer calculates the number of empty buffers at the current read pointer and the write pointer, calculates the buffer pool degree, and detects the buffer pool if the calculated buffer pool degree is greater than or equal to a set reference value. How to detect and manage the pool of message buffers using dual fork memory. The method according to any one of claims 1 to 4, When the buffer pool is detected, it stops transmitting and informs the other board of the buffer pool by using an interrupt and switches to the idle state. A method for detecting and managing a pool of message buffers using dual fork memory, characterized by waking from idle state and resuming message transmission by an interrupt signal indicating a buffer pool release of a counterpart board.