KR20010051242A - Thin film transistor and fabrication method thereof - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 170
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000005499 laser crystallization Methods 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 68
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 32
- 230000005855 radiation Effects 0.000 claims description 29
- 239000011521 glass Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 239000004033 plastic Substances 0.000 claims description 16
- 229920003023 plastic Polymers 0.000 claims description 16
- 239000004642 Polyimide Substances 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 239000002245 particle Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 33
- 239000011651 chromium Substances 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 238000002474 experimental method Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000007715 excimer laser crystallization Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 108010053481 Antifreeze Proteins Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000027455 binding Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009149 molecular binding Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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Abstract
Description
본 발명은 박막트랜지스터 및 그 제조방법에 관한 것으로, 특히, 액정표시장치에 사용되고 다결정실리콘박막을 활성층으로서 사용하는 박막트랜지스터와 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor and a method for manufacturing the same, which are used in a liquid crystal display device and using a polysilicon thin film as an active layer.
박막트랜지스터(TFT)는 주로 액정표시장치(LCD)의 화소에 인가되는 전압을 제어하는 소자로서 사용되고 화소들에 상당하는 수의 복수의 그러한 TFT들은 하나의 공통기판 위에 형성된다.The thin film transistor TFT is mainly used as an element for controlling a voltage applied to a pixel of a liquid crystal display (LCD) and a plurality of such TFTs corresponding to the pixels are formed on one common substrate.
비정질실리콘(a-Si)박막 또는 다결정실리콘(poly-Si)박막은 활성층으로서의 TFT 채널로 사용될 수 있다.An amorphous silicon (a-Si) thin film or a polycrystalline silicon (poly-Si) thin film can be used as the TFT channel as the active layer.
poly-Si박막을 활성층으로서 갖는 poly-Si TFT에서, poly-Si박막은 기판 위에 증착된 a-Si박막의 레이저결정화에 의하여 형성된다.In a poly-Si TFT having a poly-Si thin film as an active layer, the poly-Si thin film is formed by laser crystallization of an a-Si thin film deposited on a substrate.
저공정온도와 높은 처리량의 관점에서 엑시머레이저를 사용한 엑시머레이저결정화법이 사용되고 있다.Excimer laser crystallization method using excimer laser has been used in view of low process temperature and high throughput.
poly-Si TFT는 캐리어이동도가 높고 캐리어들로서 정공들을 갖는 p형 트랜지스터를 형성할 수 있는 반면, 활성층으로서 a-Si박막을 갖는 a-Si TFT는 캐리어들이 자유전자들인 n형 트랜지스터 만을 형성할 수 있다는 점에서 poly-Si TFT는 a-Si TFT에 비하여 장점들을 가지고 있다.Poly-Si TFTs can form p-type transistors with high carrier mobility and holes as carriers, whereas a-Si TFTs with a-Si thin film as active layer can form only n-type transistors whose carriers are free electrons. Poly-Si TFT has advantages over a-Si TFT in that it is.
그러므로, poly-Si TFT들을 사용하여 CMOS회로를 제조할 수 있기 때문에, CMOS회로로 구성되는 LCD의 구동회로들은 poly-Si TFT들에 의하여 형성될 수 있다.Therefore, since a CMOS circuit can be manufactured using poly-Si TFTs, the driving circuits of the LCD composed of the CMOS circuit can be formed by the poly-Si TFTs.
최근, 화소들의 액정전위들을 제어하는 소자들을 형성하는 poly-Si TFT들과 구동회로들을 형성하는 poly-Si TFT들을 동일 기판 위에, 일체 형성하는 것이 개발되어 있다. 이 기술에 의하여, 구동회로의 실장기술에 제약이 없어지기 때문에, 표시화면의 고세밀화가 가능해진다. 그러므로, 전기접속수를 감소시킬 수 있고, 액정표시장치의 기계적 신뢰성이 향상될 수 있다.Recently, it has been developed to integrally form poly-Si TFTs forming elements for controlling liquid crystal potentials of pixels and poly-Si TFTs forming drive circuits on the same substrate. This technique eliminates limitations on the mounting technology of the driving circuit, thereby enabling high definition of the display screen. Therefore, the number of electrical connections can be reduced, and the mechanical reliability of the liquid crystal display device can be improved.
전술한 바와 같이, poly-Si TFT는 고성능 TFT이다. poly-Si TFT의 동작성능 중 동작속도를 나타내는 파라미터인 캐리어이동도는, 활성층으로 사용되는 poly-Si박막의 결정입경과 관련되며, 결정입경이 클수록 캐리어이동도는 커진다고 알려져 있다.As described above, the poly-Si TFT is a high performance TFT. The carrier mobility, which is a parameter representing the operating speed of the poly-Si TFT, is related to the grain size of the poly-Si thin film used as the active layer, and it is known that the larger the grain size, the greater the carrier mobility.
큰 결정입경을 갖는 poly-Si박막을 형성하기 위하여, 상술한 레이저결정화에서의 레이저광의 세기를 증가시켜 Si박막을 결정화하는데 사용되는 처리온도를 높이는 것이 효과적이다.In order to form a poly-Si thin film having a large crystal grain size, it is effective to increase the intensity of the laser light in the above-described laser crystallization to increase the processing temperature used for crystallizing the Si thin film.
레이저결정화에 있어 중요한 것은 기판이 레이저결정화 도중 용융된 Si박막으로부터 전도된 열에 의하여 영향을 받는다는 것이다. 용융된 Si박막으로부터 기판으로의 열전도 영향을 줄이기 위하여, 일본공개특허공보 평2-130914호는 레이저결정화 동안 열을 차단하기 위하여 내열유리막이 기판 위에 설치되는 기술을 개시한다.Important for laser crystallization is that the substrate is affected by heat conducted from the molten Si thin film during laser crystallization. In order to reduce the heat conduction effect from the molten Si thin film to the substrate, Japanese Laid-Open Patent Publication No. Hei 2-130914 discloses a technique in which a heat-resistant glass film is provided on a substrate to block heat during laser crystallization.
그러나, 상기 공보에서, 방열막의 두께에 관하여 개시도 시사도 되어있지 않다. 그러므로, 높은 세기의 레이저광이 큰 입경을 갖는 poly-Si막을 형성하기 위하여 a-Si박막에 조사될 때 유리나 플라스틱 등의 저융점을 갖는 기판들은 손상된다. 그 이유는 방열막의 두께가 너무 얇아서 기판온도의 증가를 억제할 수 없기 때문이다.However, in the above publication, neither disclosure nor suggestion is made regarding the thickness of the heat radiation film. Therefore, substrates having low melting point, such as glass or plastic, are damaged when a high intensity laser light is irradiated to the a-Si thin film to form a poly-Si film having a large particle size. This is because the thickness of the heat dissipation film is too thin to suppress an increase in substrate temperature.
한편, 엑시머레이저결정화의 결점은 레이저광이 수십 나노초의 주기를 갖는 펄스레이저광이므로, 용융된 Si박막의 온도가 레이저결정화 도중 열평형상태에 도달하지 못한다는 것이다. 따라서, 엑시머레이저결정화 도중 Si박막에서 깊이에 따른 온도분포가 Si박막의 기층구조의 열전도특성에 의하여 영향을 받는다. 즉, 레이저결정화 공정 중의 기층구조를 무시할 수 없다.On the other hand, a drawback of the excimer laser crystallization is that since the laser light is pulsed laser light having a period of several tens of nanoseconds, the temperature of the molten Si thin film does not reach thermal equilibrium during laser crystallization. Therefore, the temperature distribution according to the depth in the Si thin film during the excimer laser crystallization is affected by the thermal conductivity of the substrate structure of the Si thin film. That is, the substrate structure during the laser crystallization process cannot be ignored.
Si박막 아래의 기층구조가 균일하지 않다면 레이저결정화 도중 레이저조사영역에서 깊이에 따른 온도분포는 균일해지지 않는다. 이러한 기층구조의 경우, 결과로서 생긴 poly-Si박막의 입경이 균일해지지 않는다. 따라서, 활성층으로서 poly-Si박막을 갖는 TFT의 캐리어이동도가 불균일해진다.If the substrate structure under the Si thin film is not uniform, the temperature distribution with depth in the laser irradiation area during the laser crystallization is not uniform. In the case of such a base structure, the particle size of the resulting poly-Si thin film is not uniform. Thus, the carrier mobility of the TFT having the poly-Si thin film as the active layer becomes uneven.
본 발명은 종래기술의 결함을 개선하기 위하여 만들어졌고 본 발명의 목적은 레이저광의 세기가 증가되더라도 열에 의하여 거의 영향받지 않는 기판과 poly-Si박막의 기층주조가 평탄하지 않더라도 균일한 입경을 갖는 poly-Si박막을 포함하는 박막트랜지스터와, 이 박막트랜지스터의 제조방법을 제공함에 있다.The present invention has been made to improve the deficiencies of the prior art, and an object of the present invention is to poly- having a uniform particle size even if the substrate casting of the poly-Si thin film and the substrate which is hardly affected by heat even if the laser light intensity is increased. A thin film transistor comprising a Si thin film and a method of manufacturing the thin film transistor are provided.
도 1a는 본 발명의 제1 실시예에 따른, 플라스틱기판, 플라스틱기판 위에 형성된 기층 및 기층 위에 형성된 비정질실리콘박막을 포함하는 웨이퍼의 단면도;1A is a cross-sectional view of a wafer including a plastic substrate, a substrate formed on the plastic substrate, and an amorphous silicon thin film formed on the substrate according to the first embodiment of the present invention;
도 1b는 도 1a에 나타낸 비정질실리콘박막이 레이저결정화에 의하여 다결정실리콘박막으로 변환된 웨이퍼의 단면도;1B is a cross-sectional view of the wafer in which the amorphous silicon thin film shown in FIG. 1A is converted into a polysilicon thin film by laser crystallization;
도 1c는 활성층으로서 도 1b에 나타낸 다결정실리콘박막을 갖는 박막트랜지스터의 개략단면도;1C is a schematic cross-sectional view of a thin film transistor having the polysilicon thin film shown in FIG. 1B as an active layer;
도 2a는 본 발명의 제2 실시예에 따른, 유리기판, 유리기판 위에 형성된 기층 및 기층 위에 형성된 비정질실리콘박막을 포함하는 웨이퍼의 단면도;2A is a cross-sectional view of a wafer including a glass substrate, a substrate formed on the glass substrate, and an amorphous silicon thin film formed on the substrate, according to a second embodiment of the present invention;
도 2b는 도 2a에서 나타낸 비정질실리콘박막이 레이저결정화에 의하여 다결정실리콘박막으로 변환된 웨이퍼의 단면도; 및FIG. 2B is a cross-sectional view of the wafer in which the amorphous silicon thin film shown in FIG. 2A is converted into a polysilicon thin film by laser crystallization; And
도 2c는 도 2b에서 나타낸 다결정실리콘박막을 그 활성층으로서 갖는 박막트랜지스터의 개략단면도.FIG. 2C is a schematic cross-sectional view of a thin film transistor having the polysilicon thin film shown in FIG. 2B as its active layer; FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 폴리이미드플라스틱기판 12 : 이산화실리콘(SiO2)박막11: polyimide plastic substrate 12: silicon dioxide (SiO 2 ) thin film
13, 23 : 비정질실리콘박막 14, 24 : 다결정실리콘박막13, 23: amorphous silicon thin film 14, 24: polycrystalline silicon thin film
20 : 크롬(Cr)박막 21 : 유리기판20: chromium (Cr) thin film 21: glass substrate
22 : 절연막으로서의 SiON박막 30 : 게이트절연막22 SiON thin film as insulating film 30 Gate insulating film
31 : 게이트전극 32 : 소스전극배선31: gate electrode 32: source electrode wiring
33 : 드레인전극배선 34 : 층간절연막33: drain electrode wiring 34: interlayer insulating film
140， 240 : 채널영역 141，241 : 소스영역140, 240: channel area 141, 241: source area
142， 242 : 드레인영역142, 242: drain region
상기 목적을 달성하기 위하여, 본 발명에 따르면, 박막트랜지스터는 기판에 형성된 방열막 위에 제조되며 활성층으로서 사용되는 다결정실리콘박막을 구비하고, 방열막의 두께 d(㎝)가 하기식을 만족하고,In order to achieve the above object, according to the present invention, the thin film transistor is provided on the heat radiation film formed on the substrate and has a polysilicon thin film used as an active layer, the thickness d (cm) of the heat radiation film satisfies the following equation,
d5.0 ×10-4×k1/2 d 5.0 × 10 -4 × k 1/2
여기서 k(W/㎝ㆍK)는 방열막의 열전도율인 poly-Si박막을 포함한다.Here k (W / cm · K) includes a poly-Si thin film which is a thermal conductivity of a heat radiation film.
본 발명에서, 상기 조건을 만족하는 두께를 갖는 방열막은 큰 입경을 갖는 poly-Si박막을 형성하기에 충분한 높은 강도의 레이저광으로 레이저결정화 동안 열전도를 차단시킨다. 따라서, 낮은 내열성을 갖는 유리나 플라스틱 등의 재료로 형성된 기판이 열에 의하여 영향을 받지 않고, 변형없이 정상상태에서 유지될 수 있다. 이 사실은 실험으로 확인되었다.In the present invention, the heat radiation film having a thickness that satisfies the above condition blocks heat conduction during laser crystallization with a laser beam of high intensity sufficient to form a poly-Si thin film having a large particle diameter. Therefore, the substrate formed of a material such as glass or plastic having low heat resistance can be maintained in a steady state without deformation by heat. This fact was confirmed by experiment.
본 발명에서, 금속막이 절연막과 기판 사이의 기설정된 부분에 형성된 구성을 채용할 수 있다. 이러한 금속막은 박막트랜지스터(TFT)의 활성층이 광선으로 조사되는 것을 막는 차광막으로서 기능을 한다. 더욱이, 방열막이 레이저결정화 동안 열전도를 차단하기 때문에, Si박막에서 깊이에 따른 온도분포가 Si박막의 기층구조에 금속막이 존재하는지에 무관하게 균일해진다. 따라서, 레이저결정화에 의하여 형성된 poly-Si박막의 입경이 균일하게 되어, 그 활성층으로서 poly-Si박막을 갖는 박막트랜지스터의 캐리어이동도가 Si박막의 기층구조에 존재하는 금속막에 의하여 영향받지 않는다. 이 사실은 실험으로 확인되었다.In the present invention, a structure in which a metal film is formed in a predetermined portion between the insulating film and the substrate can be adopted. This metal film functions as a light shielding film which prevents the active layer of the TFT from being irradiated with light. Furthermore, since the heat dissipation film blocks heat conduction during laser crystallization, the temperature distribution with depth in the Si thin film becomes uniform regardless of whether a metal film exists in the base structure of the Si thin film. Therefore, the particle diameter of the poly-Si thin film formed by laser crystallization becomes uniform, and the carrier mobility of the thin film transistor having the poly-Si thin film as its active layer is not affected by the metal film present in the base layer structure of the Si thin film. This fact was confirmed by experiment.
본 발명에서, 기판은 폴리이미드와 같은 플라스틱재료로 형성된다. 플라스틱이 유리보다 가볍기 때문에, 플라스틱기판을 사용하는 것이 액정표시장치(LCD)의 무게를 줄이는데 효과적이다.In the present invention, the substrate is formed of a plastic material such as polyimide. Since plastic is lighter than glass, using a plastic substrate is effective to reduce the weight of a liquid crystal display (LCD).
본 발명에 따른 박막트랜지스터의 제조방법은 방열막을 기판 위에 형성하는 제1 단계, 그 방열막 위에 a-Si박막을 형성하는 제2 단계, a-Si박막의 레이저결정화에 의하여 poly-Si박막을 형성하는 제3 단계, 및 poly-Si박막을 박막트랜지스터의 활성층으로서 만들고 미리 설정된, 게이트에 대응하는 활성층에서 소스와 드레인을 제공하는 제4 단계를 포함하고, 제1 단계에서 형성된 방열막의 두께 d(㎝)는 k(W/㎝ㆍK)가 방열막을 형성하는 재료의 열전도율인 식 d5.0 ×10-4×k1/2를 만족한다. 그러므로, 레이저결정화가 제3 단계에서 큰 입경을 갖는 poly-Si박막을 형성하는데 필요한 레이저전력으로 수행될 때, 제1 단계에서 형성되고 전술한 조건을 만족하는 두께를 갖는 방열막이 레이저결정화 동안 열전도를 차단한다. 따라서, 낮은 내열성을 갖는 유리나 플라스틱 등의 재료로 형성된 기판이 열에 의하여 변형되는 경우가 없고 기판은 정상상태에서 유지된다. 이 사실은 실험으로 확인되었다.In the method of manufacturing a thin film transistor according to the present invention, a poly-Si thin film is formed by a first step of forming a heat radiation film on a substrate, a second step of forming an a-Si thin film on the heat radiation film, and laser crystallization of the a-Si thin film. And a fourth step of making the poly-Si thin film as an active layer of the thin film transistor and providing a source and a drain in an active layer corresponding to the gate, which is preset, d (cm) of the heat radiation film formed in the first step. ) Is the formula d, where k (W / cm · K) is the thermal conductivity of the material forming the heat radiation film It satisfies 5.0 x 10 -4 x k 1/2 . Therefore, when laser crystallization is performed with the laser power required to form a poly-Si thin film having a large particle diameter in the third step, a heat radiation film formed in the first step and having a thickness that satisfies the above-described conditions is subjected to thermal conduction during laser crystallization. Block it. Therefore, a substrate formed of a material such as glass or plastic having low heat resistance is not deformed by heat and the substrate is maintained in a steady state. This fact was confirmed by experiment.
제1 단계에서 방열막을 형성할 때, 금속막을 기판의 기설정된 부분에 미리 형성할 수 있다. 이러한 금속막은 박막트랜지스터(TFT)의 활성층이 광으로 조사되는 것을 방지하는 차광막으로서 기능을 한다.When the heat radiation film is formed in the first step, the metal film may be previously formed on a predetermined portion of the substrate. Such a metal film functions as a light shielding film for preventing the active layer of the thin film transistor (TFT) from being irradiated with light.
더욱이, 전술한 바와 같이 방열막이 레이저결정화 동안 열전도를 차단하기 때문에, Si박막에서 깊이에 따른 온도분포가 레이저결정화 동안 Si박막 기층구조의 금속막 유무에 관계없이 균일해진다. 그러므로, 레이저결정화에 의하여 형성된 poly-Si박막의 입경이 균일하게 되어, poly-Si박막을 활성층으로서 사용하는 TFT의 캐리어이동도가 Si박막 기층구조의 금속막 유무에 관계없이 균일해진다. 이 사실은 실험으로 확인되었다.Furthermore, as described above, since the heat dissipation film blocks heat conduction during laser crystallization, the temperature distribution according to depth in the Si thin film becomes uniform regardless of the presence or absence of the metal film of the Si thin film base structure during laser crystallization. Therefore, the particle diameter of the poly-Si thin film formed by laser crystallization becomes uniform, and the carrier mobility of the TFT using the poly-Si thin film as the active layer becomes uniform regardless of the presence or absence of the metal film of the Si thin film base structure. This fact was confirmed by experiment.
또한, 제3 단계에서 사용된 레이저는 엑시머레이저이다. 엑시머레이저는 그 광자에너지가 분자의 결합에너지정도로 크고 유도방출에 기인한 증폭율이 두드러지게 높다는 점에서 다른 어떤 레이저보다도 우수하다.Also, the laser used in the third step is an excimer laser. Excimer lasers are superior to any other laser in that the photon energy is as large as the binding energy of the molecule and the amplification rate due to the induced emission is significantly higher.
본 발명의 전술한 및 다른 목적들, 특징들 및 이점들은 첨부도면들에 관련한 하기의 상세한 설명을 참조하여 더욱 명백해질 것이다.The above and other objects, features and advantages of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings.
도 1a 내지 도 1c를 참조하여 본 발명의 바람직한 제1 실시예를 상세히 설명한다.1A to 1C, a first preferred embodiment of the present invention will be described in detail.
도 1a에서, 참조번호 11은 폴리이미드플라스틱기판을 나타낸다. 이 폴리이미드플라스틱기판(11) 위에, 이산화실리콘(SiO2)박막(12)이 층간방열막으로서 형성된다. 도 1a는 비정질실리콘박막(13)이 SiO2박막(12) 위에 형성된 상태를 나타낸다.In Fig. 1A, reference numeral 11 denotes a polyimide plastic substrate. On this polyimide plastic substrate 11, a silicon dioxide (SiO 2 ) thin film 12 is formed as an interlayer heat dissipation film. FIG. 1A illustrates a state in which an amorphous silicon thin film 13 is formed on the SiO 2 thin film 12.
도 1b는 도 1a에 나타낸 비정질실리콘박막(Si박막)이 엑시머레이저를 사용한 레이저결정화에 의하여 poly-Si박막(14)으로 변형된 상태를 나타낸다. poly-Si박막(14)은 박막트랜지스터(TFT)의 활성층으로서 기능을 한다.FIG. 1B shows a state in which the amorphous silicon thin film (Si thin film) shown in FIG. 1A is transformed into a poly-Si thin film 14 by laser crystallization using an excimer laser. The poly-Si thin film 14 functions as an active layer of a thin film transistor (TFT).
본 발명에서, 방열막(12)의 두께 d(㎝)는 k(W/㎝ㆍK)가 방열막(12) 재료의 열전도율인 식 d5.0 ×10-4×k1/2를 만족하도록 설정된다.In the present invention, the thickness d (cm) of the heat dissipation film 12 is expressed by the formula d where k (W / cm · K) is the thermal conductivity of the material of the heat dissipation film 12. 5.0 x 10 -4 x k 1/2 is set to be satisfied.
도 1c에 나타낸 바와 같이, 박막트랜지스터(TFT)는 알려진 방법에 의하여 활성층으로서의 poly-Si박막(14)으로 형성된다. 즉, poly-Si박막(14)은 채널영역(140), 소스영역(141) 및 드레인영역(142)을 형성하도록 패터닝된다. 다음으로 각각의 영역들에 전기적으로 접속되는 소스전극배선(32) 및 드레인전극배선(33)이 층간방열막(34)을 통하여 배열된다. poly-Si TFT는 게이트방열막(30) 위에 게이트전극(31)을 포함한다.As shown in Fig. 1C, a thin film transistor (TFT) is formed of a poly-Si thin film 14 as an active layer by a known method. That is, the poly-Si thin film 14 is patterned to form the channel region 140, the source region 141, and the drain region 142. Next, the source electrode wiring 32 and the drain electrode wiring 33 electrically connected to the respective regions are arranged through the interlayer heat insulating film 34. The poly-Si TFT includes a gate electrode 31 on the gate heat radiation film 30.
poly-Si박막(활성층)(14)의 제조방법 및 방열막(12) 두께에 관하여 상세히 설명한다.The manufacturing method of the poly-Si thin film (active layer) 14 and the thickness of the heat radiation film 12 are demonstrated in detail.
도 1a 및 도 1b에 나타낸 바와 같이, poly-Si박막(활성층)이 다음 단계를 통하여 형성된다.As shown in Figs. 1A and 1B, a poly-Si thin film (active layer) is formed through the following steps.
우선, 방열용 SiO2박막(12)이 100℃의 기판온도에서 SiO2의 스퍼터링에 의하여 폴리이미드기판(11) 위에 퇴적되고(제1 단계), 방열막(12)의 두께(d)는 600(㎚)으로 설정된다.First, the heat dissipating SiO 2 thin film 12 is deposited on the polyimide substrate 11 by sputtering SiO 2 at a substrate temperature of 100 ° C. (first step), and the thickness d of the heat dissipating film 12 is 600. (Nm) is set.
다음으로, 비정질실리콘박막(13)이 100℃의 기판온도에서 Si의 스퍼터링에 의하여 방열용 SiO2박막(12) 위에 퇴적되고(제2 단계), 비정질실리콘박막(13)의 두께(d)는 60(㎚)으로 된다.Next, the amorphous silicon thin film 13 is deposited on the heat dissipating SiO 2 thin film 12 by the sputtering of Si at a substrate temperature of 100 ° C. (second step), and the thickness d of the amorphous silicon thin film 13 is 60 nm.
그 후, a-Si박막(13)은 레이저광으로 조사되어, poly-Si박막으로 된다(제3 단계). 본 실시예에서, a-Si박막(13)의 표면은 150 ×0.4(㎟)의 레이저빔단면적, 430(mJ/㎠)의 에너지밀도 및 90%의 빔중첩율의 조건 하에서 XeCl 엑시머레이저의 레이저빔으로 스캔된다.Thereafter, the a-Si thin film 13 is irradiated with a laser light to form a poly-Si thin film (third step). In this embodiment, the surface of the a-Si thin film 13 has a laser beam cross-sectional area of 150 x 0.4 (mm 2), an energy density of 430 (mJ / cm 2) and a laser overlap of the XeCl excimer laser under conditions of 90% beam overlap ratio. Scanned by the beam
그 결과, 박막트랜지스터의 활성층으로 사용하기에 적합한 poly-Si박막(14)이 도 1b에 나타낸 바와 같이 형성된다.As a result, a poly-Si thin film 14 suitable for use as the active layer of the thin film transistor is formed as shown in Fig. 1B.
전술한 조건하에 형성된 TFT의 활성층(14)이 평가되었다. 1.3(㎛)정도의 비교적 큰 평균입경을 갖는 poly-Si박막이 폴리이미드기판(11)의 변형 및 흐려짐없이 얻어졌다. poly-Si박막을 활성층(14)으로서 갖는 트랜지스터는 200℃ 이하의 공정온도를 사용하여 형성되었다. 트랜지스터는 약 100(㎠/Vㆍs)의 이동도를 가졌다.The active layer 14 of the TFT formed under the conditions described above was evaluated. A poly-Si thin film having a relatively large average particle diameter of about 1.3 (µm) was obtained without deformation and clouding of the polyimide substrate 11. The transistor having the poly-Si thin film as the active layer 14 was formed using a process temperature of 200 deg. The transistor had a mobility of about 100 (cm 2 / V · s).
이 경우, 층간방열막(12)의 두께(d)는 다음의 수학식 1을 만족한다.In this case, the thickness d of the interlayer thermal barrier film 12 satisfies the following expression (1).
여기서 k(W/㎝ㆍK)는 방열막 재료의 열전도율이다. 수학식 1은 방열막(12)의 두께(d)의 하한을 나타내며, 이 하한 내에서 기판(11)이 그 재료와 관계없이, 열 등에 의하여 영향을 받지 않는다. 두께(d)의 하한의 유효성은 실험으로 확인되었다.Where k (W / cm · K) is the thermal conductivity of the heat radiation film material. Equation 1 shows the lower limit of the thickness d of the heat dissipation film 12, and within this lower limit, the substrate 11 is not affected by heat or the like irrespective of its material. The effectiveness of the lower limit of the thickness d was confirmed experimentally.
즉, 상기 실험에서, 방열막(12)의 두께(d)는 600(㎚)으로 특정화된다. 이 수치는 다음의 이유로 선택되었다:That is, in the above experiment, the thickness d of the heat radiation film 12 is specified to be 600 (nm). This figure was chosen for the following reasons:
방열막(12)이 이산화실리콘으로 형성될 때, 그 열전도율(k)은 k = 0.014(W/㎝ㆍK)이다. 따라서, 수학식 1은 다음과 같이 된다.When the heat radiation film 12 is formed of silicon dioxide, the thermal conductivity k is k = 0.014 (W / cm · K). Therefore, Equation 1 is as follows.
d5.0 ×10-4×k1/2 600(㎚).d 5.0 × 10 -4 × k 1/2 600 nm.
한편, 도 1a 내지 도 1c에 나타낸 것과 비슷한 구성에서 방열막(SiO2박막)(12)의 두께(d)가 500(㎚)이었고 a-Si박막(13)이 430(mJ/㎠)의 에너지밀도를 갖는 레이저로 조사되었을 때, 폴리이미드기판(11)은 흐려지고 변형되어 poly-Si박막(14)의 일부분이 박리되었다. 레이저에너지밀도가 290(mJ/㎠)으로 감소되었을 때, 기판의 변형이나 흐려짐은 관측되지 않았었다. 그러나, 후자의 경우에, poly-Si박막의 평균입경이 약 50(㎚)으로 감소되었고 활성층과 동일한 poly-Si박막을 사용한 박막트랜지스터의 캐리어이동도는 30(㎠/Vㆍs)으로 감소되었다. 캐리어이동도의 감소는 레이저조사로 발생된 열에 기인한 폴리이미드기판(11)의 변형이나 흐려짐에 그 원인이 있음이 분명하다.On the other hand, in the configuration similar to that shown in FIGS. 1A to 1C, the heat radiation film (SiO 2 thin film) 12 had a thickness d of 500 nm and the a-Si thin film 13 had an energy of 430 (mJ / cm 2). When irradiated with a laser having a density, the polyimide substrate 11 was clouded and deformed so that a part of the poly-Si thin film 14 was peeled off. When the laser energy density was reduced to 290 (mJ / cm 2), no deformation or blur of the substrate was observed. In the latter case, however, the average particle diameter of the poly-Si thin film was reduced to about 50 nm and the carrier mobility of the thin film transistor using the same poly-Si thin film as the active layer was reduced to 30 (cm 2 / V · s). . It is apparent that the decrease in carrier mobility is caused by the deformation or blur of the polyimide substrate 11 due to heat generated by laser irradiation.
이제, 방열막(12)의 두께(d)를 특정하는 상기 수학식 1의 이론적 타당성에 관해 검토한다.Now, the theoretical validity of Equation 1 for specifying the thickness d of the heat radiation film 12 will be examined.
방열막(12) 두께방향(= x)에서 1차원 열전도를 고려한다면, 열전도방정식은 다음의 수학식 2로 주어진다:Considering the one-dimensional heat conduction in the thickness direction (= x) of the heat radiation film 12, the heat conduction equation is given by the following equation:
여기서 k는 방열막 재료의 열전도율, T는 온도, x는 방열막두께방향의 거리, t는 시간, ρ는 밀도, C는 방열막의 비열이고 D는 편미분기호이다. 수학식 2로부터, x가 k1/2에 비례하는 관계가 얻어진다.Where k is the thermal conductivity of the heat radiation film material, T is the temperature, x is the distance in the heat radiation film thickness direction, t is the time, ρ is the density, C is the specific heat of the heat radiation film, and D is the partial differential arc. From equation (2), a relationship in which x is proportional to k 1/2 is obtained.
한편, 레이저결정화 도중 용융상태에서 Si박막의 최대온도가 특정화될 수는 없지만, 최대온도가 약 2000℃인 실리콘의 융점(1412℃) 및 비점(약 2500℃)에 근거하여 고려될 수 있다. 그러므로, 방열막(12)이 약 2000℃의 온도차를 단열할 수 있다면, Si박막의 기층구조(기층재료)에 대한 레이저결정화공정의 의존이 제거될 수 있다.On the other hand, the maximum temperature of the Si thin film in the molten state during the laser crystallization cannot be specified, but may be considered based on the melting point (1412 ° C.) and boiling point (about 2500 ° C.) of silicon having a maximum temperature of about 2000 ° C. Therefore, if the heat radiating film 12 can insulate a temperature difference of about 2000 DEG C, the dependence of the laser crystallization process on the base layer structure (base material) of the Si thin film can be eliminated.
이 실험들에 의하여 얻어진 막두께에 따르면, 수학식 2의 해와 정량적으로 유사한 경향을 나타내는 수학식이 얻어지고, 이 수학식에서 d (= x)는 k1/2에 비례한다.According to the film thicknesses obtained by these experiments, an equation showing a tendency quantitatively similar to the solution of Equation 2 is obtained, where d (= x) is proportional to k 1/2 .
전술한 바와 같이, 레이저결정화가 제1 실시예의 제3 단계에서 큰 입경을 갖는 poly-Si박막을 형성하는데 필요한 430(mJ/㎠)의 레이저에너지밀도로 수행될 때, 제1 단계에서 형성되고 수학식 1을 만족하는 600(㎚)의 두께를 갖는 방열막(SiO2박막)이 레이저결정화 열을 차단하여, 내열성이 낮은 폴리이미드로 형성된 기판이 열에 의하여 변형되지 않고, 그 정상상태를 유지할 수 있다.As described above, when the laser crystallization is performed at a laser energy density of 430 (mJ / cm 2) necessary to form a poly-Si thin film having a large particle diameter in the third step of the first embodiment, A heat radiation film (SiO 2 thin film) having a thickness of 600 (nm) satisfying Equation 1 blocks laser crystallization heat, so that a substrate formed of polyimide having low heat resistance is not deformed by heat and can maintain its steady state. .
이렇게 형성된 poly-Si 박막을 활성층으로서 갖는 박막트랜지스터(TFT)는 100(㎠/Vㆍs)의 높은 캐리어이동도를 가질 수 있다.The thin film transistor (TFT) having the poly-Si thin film thus formed as an active layer may have a high carrier mobility of 100 (cm 2 / V · s).
이제, 본 발명의 제2 실시예를 도 2a∼2b를 참조하여 상세히 설명한다.Now, a second embodiment of the present invention will be described in detail with reference to Figs. 2A to 2B.
제2 실시예에 따른 TFT는 프로젝터형액정라이트밸브에 사용되기에 적합한 구성을 가진다.The TFT according to the second embodiment has a configuration suitable for use in a projector type liquid crystal light valve.
우선, 도 2a에서, 참조번호 21은 유리기판을 나타낸다. 크롬(Cr)으로 된 박막(20)이 금속막으로서 유리기판(21)의 기설정된 일부분에 마련된다. Cr박막(20)은 유리기판(21) 위에 형성된 Cr박막을 통상의 포토레지스트를 사용한 건식식각에 의하여 원하는 형상으로 패터닝함으로써 형성된다.First, in Fig. 2A, reference numeral 21 denotes a glass substrate. A thin film 20 made of chromium (Cr) is provided on a predetermined portion of the glass substrate 21 as a metal film. The Cr thin film 20 is formed by patterning a Cr thin film formed on the glass substrate 21 into a desired shape by dry etching using a conventional photoresist.
실리콘질화산화물(SiON)로 된 절연막(22)이 Cr박막(20)을 갖는 유리기판(21) 위에 형성된다. 도 2a는 Cr박막(20)을 갖는 유리기판(21), SiON박막(22) 및 SiON박막(22) 위에 형성된 비정질실리콘박막(a-Si박막)(23)을 포함하는 웨이퍼를 나타낸다.An insulating film 22 made of silicon nitride oxide (SiON) is formed on the glass substrate 21 having the Cr thin film 20. 2A shows a wafer including a glass substrate 21 having a Cr thin film 20, a SiON thin film 22, and an amorphous silicon thin film (a-Si thin film) 23 formed on the SiON thin film 22.
도 2b는 a-Si박막(23)이 제1 실시예에서와 같이 엑시머레이저를 사용한 결정화에 의하여 poly-Si박막(24)으로 변환되는 웨이퍼를 나타낸다. 다음으로, 도 2c에서 나타낸 활성층으로서의 poly-Si박막을 갖는 박막트랜지스터(TFT)가 알려진 방법에 의하여 형성된다. 즉, poly-Si박막(24)이 패터닝되어 채널영역(240), 소스영역(241) 및 드레인영역(242)이 형성된다. 그 후에 소스영역(241)과 드레인영역(242)에 각각 전기접속되는 소스전극배선(32) 및 드레인전극배선(33)이 절연막(34)을 통하여 형성된다. 도 2c에서, 한쌍의 소위 가볍게 도핑된 드레인(LDD)영역들(245)이 채널영역(240)의 양끝에 형성된다. 게이트전극(31)이 게이트절연막(30) 위에 마련되어, 잘 알려진 poly-Si TFT 구조를 갖는 TFT를 완성한다.2B shows a wafer in which the a-Si thin film 23 is converted into a poly-Si thin film 24 by crystallization using an excimer laser as in the first embodiment. Next, a thin film transistor (TFT) having a poly-Si thin film as the active layer shown in Fig. 2C is formed by a known method. That is, the poly-Si thin film 24 is patterned to form the channel region 240, the source region 241, and the drain region 242. Thereafter, a source electrode wiring 32 and a drain electrode wiring 33 electrically connected to the source region 241 and the drain region 242 are formed through the insulating film 34. In FIG. 2C, a pair of so-called lightly doped drain (LDD) regions 245 are formed at both ends of the channel region 240. A gate electrode 31 is provided on the gate insulating film 30 to complete a TFT having a well-known poly-Si TFT structure.
실리콘질화산화물(SiON)의 열전도율이 0.041(W/㎝ㆍK)이므로, SiON박막(22)의 두께(d)는 제1 실시예에서의 수학식 1로부터 이끌어낸 d1.01(㎛)을 만족하도록 설정된다.Since the thermal conductivity of silicon nitride oxide (SiON) is 0.041 (W / cm · K), the thickness d of the SiON thin film 22 is d derived from Equation 1 in the first embodiment. It is set to satisfy 1.01 (µm).
이하, poly-Si박막(활성층)(24)의 제조방법을 상세히 설명한다.Hereinafter, the manufacturing method of the poly-Si thin film (active layer) 24 is demonstrated in detail.
도 2a 및 도 2b에서 나타낸 바와 같이, poly-Si박막은 하기 단계들을 통해 형성된다.As shown in Figs. 2A and 2B, a poly-Si thin film is formed through the following steps.
100(㎚)의 두께를 갖는 Cr박막(20)이 기판(유리기판)(21) 위에 금속막으로서 형성된다. 다음으로, Cr박막(20)이 포토레지스트를 사용한 통상의 건식식각에 의하여 원하는 형태로 패터닝된다. 금속막(20)의 너비는 TFT의 설계에 의존하지만, 금속막(20)이 TFT의 차광막으로서 기능을 하도록 본 실시예에서 4(㎛)로 설정되었다.A Cr thin film 20 having a thickness of 100 nm is formed on the substrate (glass substrate) 21 as a metal film. Next, the Cr thin film 20 is patterned into a desired shape by ordinary dry etching using a photoresist. The width of the metal film 20 depends on the design of the TFT, but was set to 4 (µm) in this embodiment so that the metal film 20 functions as a light shielding film of the TFT.
다음으로, 1.1㎛의 두께를 갖는 SiON박막(22)이 300℃의 기판온도로 플라즈마CVD법(PECVD)에 의하여 웨이퍼 위에 절연막으로서 형성된다(제1 단계).Next, a SiON thin film 22 having a thickness of 1.1 mu m is formed as an insulating film on the wafer by plasma CVD (PECVD) at a substrate temperature of 300 deg. C (first step).
SiON박막의 두께(1.1㎛)는 전술하였듯이 1.01㎛ 이상이어야 하기 때문에 선택된다.The thickness (1.1 mu m) of the SiON thin film is selected because it must be 1.01 mu m or more as described above.
계속해서, a-Si박막(23)이 SiON박막(22) 위에 형성된다(제2 단계). a-Si박막(23)은 저압화학기상증착(LPCVD)에 의하여 450℃에서 75㎚의 두께로 형성된다. 도 2a는 이 상태를 나타낸다.Subsequently, an a-Si thin film 23 is formed on the SiON thin film 22 (second step). The a-Si thin film 23 is formed to a thickness of 75 nm at 450 ° C. by low pressure chemical vapor deposition (LPCVD). 2A shows this state.
도 2b는 a-Si박막(23)이 XeCl 엑시머레이저로부터의 레이저빔으로 a-Si박막(23)을 결정화하여 poly-Si박막(24)으로 변환되는 웨이퍼를 나타낸다.2B shows a wafer in which the a-Si thin film 23 crystallizes the a-Si thin film 23 with a laser beam from an XeCl excimer laser and is converted into a poly-Si thin film 24.
poly-Si박막(24)이 제1 실시예에서와 같이 박막트랜지스터(TFT)의 활성층으로서 기능을 한다.The poly-Si thin film 24 functions as an active layer of a thin film transistor (TFT) as in the first embodiment.
XeCl 엑시머레이저빔의 조사조건들은 150 ×0.4(㎠)의 레이저빔단면적, 520(mJ/㎠)의 에너지밀도 및 90%의 빔중첩율이다.The irradiation conditions of the XeCl excimer laser beam are a laser beam cross section of 150 x 0.4 (cm 2), an energy density of 520 (mJ / cm 2) and a beam overlap ratio of 90%.
이렇게 형성된 poly-Si 박막(24)을 활성층으로서 갖는 박막트랜지스터가 제조되었고 그 캐리어이동도가 측정되었다. 170(㎠/Vㆍs)의 캐리어이동도를 갖는 박막트랜지스터는 Cr박막(20)의 영향없이 실현되었다.A thin film transistor having the poly-Si thin film 24 thus formed as an active layer was fabricated and its carrier mobility was measured. A thin film transistor having a carrier mobility of 170 (cm 2 / V · s) was realized without the influence of the Cr thin film 20.
비교예로서, SiON의 두께가 1㎛인 것을 제외하고는 전술한 것과 동일한 구성을 갖는 박막트랜지스터가 마련되고 그 캐리어이동도가 측정되었다. 금속막을 갖는 비교 박막트랜지스터의 이동도는 60(㎠/Vㆍs)으로 감소되었다. 이동도의 감소는 레이저결정화 도중 열이 SiON막을 통하여 금속막으로 전도한 것에 의한 냉각효과 때문이다.As a comparative example, except that the thickness of SiON was 1 µm, a thin film transistor having the same configuration as described above was provided and its carrier mobility was measured. The mobility of the comparative thin film transistor with a metal film was reduced to 60 (cm 2 / V · s). The decrease in mobility is due to the cooling effect due to conduction of heat to the metal film through the SiON film during laser crystallization.
제2 실시예에서, 레이저결정화가 큰 입경을 갖는 poly-Si박막을 형성하는데 필요한 520(mJ/㎠)의 레이저에너지밀도로 제3 단계에서 수행될 때, 제1 단계에서 형성되고 1.1㎛의 두께를 갖는 방열막(SiON막)이 수학식 1을 만족하여, 레이저결정화 동안 열전도를 차단한다. 따라서, 내열성이 낮은 유리재료로 구성된 기판이 열에 의해 손상되지 않고 정상상태를 유지한다.In the second embodiment, when laser crystallization is carried out in the third step with a laser energy density of 520 (mJ / cm 2) necessary to form a poly-Si thin film having a large particle size, it is formed in the first step and has a thickness of 1.1 μm. The heat dissipation film (SiON film) having the following satisfies Equation 1 to block heat conduction during laser crystallization. Therefore, the substrate made of glass material having low heat resistance is not damaged by heat and maintains a steady state.
방열막이 레이저결정화 동안 열전도를 차단하기 때문에, 결정화에서의 열히스테리시스가 Si박막(활성층)의 기층구조에서는 금속막(Cr막)의 존재에 관계없이 Si박막의 조사된 영역에서 일정해진다. 따라서, TFT의 캐리어이동도는 170(㎠/Vㆍs)만큼 큰 일정값이 된다.Since the heat dissipation film blocks heat conduction during laser crystallization, the thermal hysteresis in crystallization becomes constant in the irradiated region of the Si thin film regardless of the presence of the metal film (Cr film) in the base structure of the Si thin film (active layer). Therefore, the carrier mobility of the TFT becomes a constant value as large as 170 (cm 2 / V · s).
본 발명이 특정한 실시예들을 참조하여 설명되었지만, 이 설명이 제한하는 의미로 해석되도록 의도된 것은 아니다. 개시된 실시예들의 다양한 변형들은 본 발명의 설명을 참조하여 이 기술(분야)의 숙련자들에게 명백해질 것이다. 그러므로, 청구항들이 진정한 발명의 범위 내에서 모든 변경 또는 실시예들을 포함하고 있다고 간주된다.Although the present invention has been described with reference to specific embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications of the disclosed embodiments will become apparent to those skilled in the art with reference to the description of the invention. Therefore, it is considered that the claims encompass all changes or embodiments within the scope of the true invention.
전술한 바와 같이, 본 발명에 따르면, 상기 조건을 만족하는 두께를 갖는 방열막이 큰 입경을 갖는 poly-Si 박막을 형성하는 레이저전력으로 레이저결정화하는 동안의 열전도를 차단하여, 내열성이 낮은 유리 및 플라스틱기판이 손상되지 않고 그 정상상태를 유지할 수 있다.As described above, according to the present invention, glass and plastics having low heat resistance by blocking heat conduction during laser crystallization with laser power to form a poly-Si thin film having a large particle size with a heat radiation film having a thickness satisfying the above conditions. The substrate can be kept intact without being damaged.
따라서, 큰 캐리어이동도를 갖는 고성능 박막트랜지스터를 제조할 수 있고 결함이 있는 기판에 기인한 박막트랜지스터의 폐기 가능성을 줄일 수 있기 때문에, 제조공정에서의 신뢰성을 향상시킬 수 있고 수율을 향상시킬 수 있다.Therefore, since a high performance thin film transistor having a large carrier mobility can be manufactured and the possibility of discarding the thin film transistor due to a defective substrate can be reduced, the reliability in the manufacturing process can be improved and the yield can be improved. .
또한, 제2 실시예에서 금속막은 박막트랜지스터의 활성층이 광선으로 조사되는 것을 차단하는 차광막으로서 기능을 하여, 활성층에 입사하는 광선으로 인해 야기되는, 박막트랜지스터의 누설전류를 방지할 수 있다. 그러므로, 이 박막트랜지스터가 액정표시장치 및 프로젝터에 적용되면, 누설전류에 기인한 표시장치 및 투사된 스크린의 화질저하가 방지될 수 있다. 따라서, 고품질의 액정표시장치 및 프로젝터를 얻을 수 있다.Further, in the second embodiment, the metal film functions as a light shielding film to block the active layer of the thin film transistor from being irradiated with light rays, thereby preventing leakage current of the thin film transistors caused by light rays incident on the active layer. Therefore, if this thin film transistor is applied to a liquid crystal display device and a projector, deterioration in image quality of the display device and the projected screen due to leakage current can be prevented. Therefore, a high quality liquid crystal display device and a projector can be obtained.
더욱이, 기판이 제1 실시예와 같이, 유리소재보다 가벼운, 플라스틱소재로 구성될 때, 액정표시장치의 무게가 감소될 수 있다. 그러므로, 본 발명에 따른 박막트랜지스터들을 사용한 액정표시장치가 사용되면 경량의, 휴대형정보단말을 얻을 수 있다.Furthermore, when the substrate is made of a plastic material, which is lighter than the glass material, as in the first embodiment, the weight of the liquid crystal display device can be reduced. Therefore, when the liquid crystal display device using the thin film transistors according to the present invention is used, a lightweight, portable information terminal can be obtained.
게다가, 본 발명의 제조방법에 따르면, 레이저결정화 단계에서, 결정화가 큰 입경을 갖는 poly-Si박막을 형성하는데 필요한 레이저전력으로 수행될 때, 하부막 위에 형성되고 상술한 조건을 만족하는 두께를 갖는 방열막은 레이저결정화 동안 열전도를 차단한다. 그러므로, 내열성이 낮은 유리 및 플라스틱 등의 재료로 형성된 기판은 열에 의하여 영향을 받지 않고 그 정상상태를 유지할 수 있다.Furthermore, according to the manufacturing method of the present invention, in the laser crystallization step, when the crystallization is carried out with the laser power required to form a poly-Si thin film having a large particle size, it has a thickness formed on the lower film and satisfies the conditions described above. The heat radiation film blocks heat conduction during laser crystallization. Therefore, the substrate formed of materials such as glass and plastic having low heat resistance can be maintained in its steady state without being affected by heat.
그러므로, 큰 캐리어이동도를 갖는 고성능 박막트랜지스터를 제조할 수 있고 결함이 있는 기판에 기인한 불량소자의 생산을 방지할 수 있기 때문에, 제조공정에 있어서의 신뢰성이 향상되고 수율이 향상될 수 있다.Therefore, since a high performance thin film transistor having a large carrier mobility can be manufactured and production of defective devices due to a defective substrate can be prevented, reliability in the manufacturing process can be improved and yield can be improved.
본 발명에 따른 제조방법에서, 엑시머레이저는 광자에너지가 분자결합에너지만큼 크고 유도방출에 기인한 증폭효율이 다른 레이저에 비하여 두드러지게 높다는 점에서 이점이 있다. 그러므로, 레이저결정화를 효율적으로 수행할 수 있어 높은 처리율로 고품질의 poly-Si박막을 형성할 수 있다.In the manufacturing method according to the present invention, the excimer laser is advantageous in that the photon energy is as large as the molecular binding energy, and the amplification efficiency due to the induced emission is significantly higher than that of other lasers. Therefore, laser crystallization can be performed efficiently, and a high quality poly-Si thin film can be formed with high throughput.
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| JP30222599A JP3636949B2 (en) | 1999-10-25 | 1999-10-25 | Thin film transistor manufacturing method |
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| WO2014011607A1 (en) * | 2012-07-12 | 2014-01-16 | Carestream Health, Inc | Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count |
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| JPH06163401A (en) * | 1992-09-11 | 1994-06-10 | A G Technol Kk | Formation of polycrystalline silicon layer and polycrystalline silicon thin film transistor using same |
| JP3361670B2 (en) * | 1995-11-13 | 2003-01-07 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| GB9613065D0 (en) * | 1996-06-21 | 1996-08-28 | Philips Electronics Nv | Electronic device manufacture |
| JP3777706B2 (en) * | 1997-02-21 | 2006-05-24 | ソニー株式会社 | Display device |
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| WO2014011607A1 (en) * | 2012-07-12 | 2014-01-16 | Carestream Health, Inc | Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count |
| US9048160B2 (en) | 2012-07-12 | 2015-06-02 | Carestream Health, Inc. | Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count |
| US9911771B2 (en) | 2012-07-12 | 2018-03-06 | Carestream Health, Inc. | Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count |
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