KR20010046342A - Method and circuit for driving plasma display panel - Google Patents

Abstract

PURPOSE: A method and a circuit for driving a plasma display panel are provided to remove a screen quality degradation due to a mis-discharge by maintaining a sustain discharge more stably in a sustain period by maintaining the discharge state of the overall discharge cells equally before the sustain period. CONSTITUTION: A logic control part(100) outputs a level control signal of a digital data value to control a level of a data pulse voltage, by being synchronized to a detected address period after detecting the address period of a sub-field. A digital-analog converter(110) converts the level control signal of the digital data value from the logic control part into an analog signal. And, a DC/DC converter supplies a data pulse voltage needed in a plasma discharge of the data electrode by receiving a power supply voltage from a main AC/DC converter. And, an address driver(130) drives the data pulse voltage from the DC/DC converter with M data electrodes(D1-Dm).

Description

TECHNICAL AND CIRCUIT FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gas discharge display panel widely used for a display device, and the like, and more particularly, in accordance with an address time change in an address period of a plasma display panel (hereinafter referred to as a PDP) driven by an address display separation (ADS) method. A driving method and a driving circuit of a PDP for adjusting the addressing discharge voltage at a constant ratio.

Recently, with the development and spread of information processing systems, the importance of displays has increased, and research and development of various flat displays having a matrix structure have been actively performed. Among them, PDP is being spotlighted as the next generation of large screen displays. The PDP has a large screen and a small thickness, and has been applied to wall-mounted TVs, home theater displays, and various monitors.

In addition, the PDP is classified into an alternating current (AC) type and a direct current (DC) type according to the type of driving voltage. The AC type PDP is driven by a sine wave AC voltage or a pulse voltage, and the DC type PDP is It is driven by DC voltage.

1 is an electrode arrangement diagram of a three-electrode surface discharge PDP, which is one of the most commonly used AC PDPs.

The structure of a typical three-electrode surface discharge PDP maintains a discharge and a scan electrode group 3, Y ₁ , Y ₂ , ..., Y _{N to} which a scan pulse is applied during an address period as shown in FIG. 1. To cause sustain discharge between the sustain electrode group 4, X ₁ , X ₂ ,..., X _N , to which the discharge sustain pulse is applied, and the scan electrode 3 and the sustain electrode 4 of the selected line. The data electrode group 2, D ₁ , D ₂ ,..., D _{M to} which data pulses are applied, and a set of scan electrodes 3 as vertical electrodes and a data electrode 2 as sustain electrodes 4 are horizontal electrodes. The cells 5 are formed at the point where they intersect with each other, and these cells are gathered to form one plasma display panel.

The basic driving principle of each cell of the three-electrode surface discharge PDP configured as described above is to generate an address discharge between the scan electrode 3 and the data electrode 2 so that wall charges are generated therein, and then the scan electrode 3 is maintained. Sustain discharge is caused between the electrodes 4 to make the discharge gas into a plasma state to generate ultraviolet rays, and the ultraviolet rays excite the phosphor to generate visible light.

Specifically, the ADS method which is the most basic method for driving the 3-electrode surface discharge PDP will be described.

The ADS driving method of the PDP includes a reset period for uniformly erasing all wall charges of the entire cell when the PDP is driven, an address period for forming wall charges in cells at specific positions, and a display for The driving method divides the sustain period into three stages, that is, write discharge is selectively performed by separating the address period and the sustain period for the discharge cells to be displayed.

FIG. 2 is an exemplary driving voltage waveform diagram applied to each electrode of the three-electrode surface discharge PDP.

1 and 2, ADS driving of a three-electrode surface discharge PDP will be described.

First, in the reset period, as shown in FIG. 2, a high voltage higher than the discharge start voltage V _f is applied to the sustain electrodes 4 and X while 0 V is applied to the N scan electrodes 3 and Y ₁ to Y _N. A write pulse of (V _w ) is applied to cause front write discharge between the scan electrodes 3, Y ₁ to Y _N and the sustain electrodes 4, X, that is, within the discharge space of all the discharge cells. As the write discharge proceeds, a negative wall charge is generated on the sustain electrodes 4 and X (the dielectric layer of the sustain electrode), and on the scan electrodes 3 and Y ₁ to Y _N (the dielectric layer of the scan electrode). +) Wall charge is generated. Subsequently, when the voltage Vs (discharge sustain voltage) lower than the discharge start voltage is applied to the scan electrodes 3 and Y ₁ to Y _N and 0 V is applied to the sustain electrodes 4 and X, the voltage of the wall charge generated immediately before is applied. Is added to sustain discharge between the scan electrodes 3, Y ₁ to Y _N and the sustain electrodes 4 and X, so that a positive wall charge is applied on the sustain electrodes 4 and X (the dielectric layer of the sustain electrode). Negative wall charges are respectively generated on the scan electrodes 3 and Y ₁ to Y _N (the dielectric layers of the scan electrodes), and the scan electrodes 3 are continuously applied with the Vs voltage applied to the sustain electrodes 4 and X, respectively. , Y ₁ to Y _N ) by applying an erase pulse of 0 V, all discharge cells are completely erased and discharged to reset the charge distribution state of all discharge cells in the panel to a uniform state without wall charges. In the address period, the addressing of the digital image signal corresponding to each cell proceeds sequentially. That is, a scan pulse of 0V is applied to any of the scan electrodes Y ₁ to Y _N to scan, and the data electrode D ₁ corresponding to a cell to be turned on among the cells constituted by the scan electrodes Y ₁ to Y _N. To D _M ) only by applying a data pulse of Va voltage so that address discharge occurs between both electrodes, and wall charge is generated inside the cell. When the above process is repeated for the _N scan electrodes Y ₁ to Y _N sequentially, all the cells are turned on or off according to the corresponding digital image signals.

When the address discharge is completed, the wall charge is added only to the cells in which the address discharge occurred in the immediately preceding address period by applying a Vs voltage to the scan electrodes Y ₁ to Y _N and a 0V voltage to the sustain electrode X in the sustain period. After the sustain discharge is generated therein, Vs voltage is applied to the sustain electrode X and 0 V is applied to the scan electrodes Y ₁ to Y _N to sustain sustain discharge again.

Thereafter, when the above processes are alternately repeated, that is, when an alternate sustain pulse is applied between the sustain electrodes X and the scan electrodes Y ₁ to Y _N , an image is displayed in the cells turned on in the immediately preceding address period. . At this time, gradation control of the image is performed by the number of sustain pulses.

In order to realize multi-gradation, one frame screen is divided into a plurality of subfield screens and displayed. Each of the subfield screens includes a reset period, an address period, and a sustain period. Among them, the reset period and the address period are all the same for each subfield, but the sustain period is a bit of the digital image data displayed in the address period. Since they are differently assigned according to weights, multi-gradation can be realized by combining each subfield using the integration effect of the eyes.

On the other hand, in the ADS subfield driving of the PDP, the wall charges generated by each data pulse in the address section continuously decrease with time, and the wall charge amount and the final discharge by the first discharge cell in each address section are continuously reduced. There is a difference between the wall charges by the cells. Therefore, there is a problem that a sustain voltage that is high enough must be applied to allow the discharge to be stably in view of the difference in the amount of charge in the sustain period.

The present invention provides a driving method and a driving circuit of a plasma display panel for removing the deterioration of image quality due to mis-discharge by maintaining the sustained discharge in the sustain period more stable by maintaining the same discharge state of all the discharge cells before the sustain period. The purpose is.

In addition, the present invention has been made to solve the above problems, by adjusting the discharge voltage for addressing in the address section at a constant rate in response to the time change of the address section by applying a constant ratio of the wall charge amount of each discharge cell The present invention provides a driving method and a driving circuit of a plasma display panel for lowering a sustain voltage applied in a sustain period by maintaining the same discharge state of each cell after the final addressing discharge in the address period is completed.

1 is an electrode arrangement diagram of a three-electrode surface discharge PDP which is one of the most commonly used AC type PDP.

2 is an exemplary driving voltage waveform applied to each electrode of the three-electrode surface discharge PDP.

3 is an embodiment block diagram of a driving circuit of a PDP according to the present invention;

4 is a waveform diagram of a driving voltage applied to a data electrode and a scan electrode according to an exemplary embodiment of the present invention.

* Description of the main parts of the drawing

100: logic controller

110: digital to analog converter

120: DC / DC converter

130: address driver

According to an aspect of the present invention, a plurality of first and second electrodes are disposed in parallel for each display line, and at the same time, a plurality of third electrodes are electrically separated from the first and second electrodes. And a method of driving a plasma display panel by dividing one frame screen into a plurality of subfields so as to display a multi-gradation image on a plasma display panel arranged to intersect the second electrode and having discharge cells formed at respective intersection regions. The voltage of the data pulse applied to the third electrode in response to a time change of the address period during an address discharge between the second electrode and the third electrode performed in the address period of each of the plurality of subfields. Variable voltage, but relatively to the voltage of the data pulse applied at the first address discharge and at the last address discharge. A data pulse voltage higher than a predetermined level is applied to the third electrode to uniformly distribute the wall charges formed in the plurality of discharge cells when the address period ends.

The present invention also provides a plurality of first and second electrodes arranged in parallel for each display line, and at the same time, a plurality of third electrodes electrically separated from the first and second electrodes and the first and second electrodes. A plasma display panel driving circuit for arranging a plurality of subfields in order to display a multi-gradation image on a plasma display panel having cross cells and discharging cells formed at respective crossing regions, wherein the plurality of subfields are driven. A logic control circuit unit for detecting the address period of the corresponding subfield for each subfield of the subfield, and outputting a level control signal of a digital data value for controlling the level of the data pulse voltage in synchronization with the detected address period; Digital-to-analog conversion means for receiving the level control signal output from the logic control circuit unit and converting the analog signal into an analog signal; DC / DC conversion means for receiving power from an external source and supplying a voltage of a data pulse required for address discharge between the second electrode and the third electrode; And an address driver for driving the data pulse voltage from the DC / DC converter to the third electrode, wherein the DC / DC converter comprises: a level control signal of an analog data value output from the digital-analog converter; And outputs a voltage of the data pulse in which the data pulse voltage of a predetermined level is linearly reduced and changed during the address time in response to the response.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

First, briefly summarizing the present invention, the state of all the discharge cells immediately before the start of discharge in the sustain period is kept the same by applying the discharge voltage of the address period at a constant rate when the AC surface discharge type PDP is driven. This prevents mis-discharge of all cells and enables sustain discharge at low sustain voltage.

FIG. 3 is a block diagram illustrating a driving circuit of a PDP according to the present invention, wherein an address period of a corresponding subfield is detected for each of a plurality of subfields, and digital for controlling the level of the data pulse voltage in synchronization with the detected address period. A logic controller 100 for outputting a level control signal of a data value, a digital-to-analog converter for receiving a level control signal of a digital data value output from the logic controller 100 and converting the signal into an analog signal; 110), a DC / DC converter (120) for supplying a data pulse voltage required for plasma discharge of the data electrode by receiving power from a main AC / DC converter (not shown in the figure). and fulfill the data pulse voltage from the DC / DC converter 120 by the address driver 130 for driving the M data electrodes (D ₁ to D _M) However, the DC / DC converter 120 receives a level control signal of an analog data value output from the digital-to-analog converter 110 as an internal comparator and compares the internal reference voltage in the comparator to set the preset value according to the comparison result. The data pulse voltage is changed to a predetermined level in the address period by outputting a data pulse voltage of a predetermined level.

The DC / DC converter 120 outputs a data pulse voltage applied to the data electrode in the address section as shown in FIG. 4, but outputs a discharge voltage higher than a final discharge voltage by a predetermined value or more at the beginning of the address section, thereby initial discharge. The wall charges generated inside the cell are increased by a certain level or more than the wall charges generated inside the final discharge cell. Here, the wall charges of the first discharge cells are larger than the wall charges of the final discharge cells, so that the wall charges of all the discharge cells appear to be nonuniform, but after the initial discharge, the wall charges of the first discharge cells continue to decrease until just before the start of the sustain period. Therefore, the wall charge amount of all the discharge cells becomes constant, which is the same as the wall charge amount of the last discharge cell in which the addressing discharge is performed just before the sustain period.

Therefore, since the sustain discharge condition in the sustain period is uniformly maintained due to the same wall charge amount of the entire discharge cells, it is possible to improve the image quality deterioration and reliability of the product by mis-discharge.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, by comparing the data pulse voltage of the first discharge cell with that of the last discharge cell in the address period, a voltage level relatively higher than a predetermined value is applied to make the wall charges in the entire discharge cells uniform. Sustain discharge in the sustain period can be more stably performed, thereby improving the image quality deterioration due to mis-discharge, and also having an excellent effect of lowering the sustain discharge voltage during the sustain period.

Claims (3)

A plurality of first and second electrodes are disposed in parallel for each display line, and at the same time, a plurality of third electrodes electrically separated from the first and second electrodes are arranged to intersect the first and second electrodes, A method of driving a plasma display panel in which a single frame screen is divided into a plurality of subfields to display a multi-gradation image on a plasma display panel having discharge cells formed at respective intersection regions. During address discharge between the second electrode and the third electrode performed in an address period of each of the plurality of subfields In response to the time change of the address period, the voltage of the data pulse applied to the third electrode is varied and applied, but the data is relatively higher than a predetermined level higher than the voltage of the data pulse applied at the last address discharge at the first address discharge. Applying a pulse voltage to the third electrode, And distributing the wall charges formed in the plurality of discharge cells uniformly when the address period ends. A plurality of first and second electrodes are disposed in parallel for each display line, and at the same time, a plurality of third electrodes electrically separated from the first and second electrodes are arranged to intersect the first and second electrodes, In the driving circuit of a plasma display panel for driving one frame screen divided into a plurality of subfields to display a multi-gradation image on a plasma display panel in which discharge cells are formed at respective intersection regions, A logic control circuit unit which detects an address period of a corresponding subfield for each of the plurality of subfields and outputs a level control signal of a digital data value for controlling the level of a data pulse voltage in synchronization with the detected address period; Digital-to-analog conversion means for receiving the level control signal output from the logic control circuit unit and converting the analog signal into an analog signal; DC / DC conversion means for receiving power from an external source and supplying a voltage of a data pulse required for address discharge between the second electrode and the third electrode; And An address driver for driving the data pulse voltage from the DC / DC conversion means to the third electrode, The DC / DC conversion means, And outputting a voltage of the data pulse in which the data pulse voltage of the predetermined level is linearly reduced and changed during the address time in response to the level control signal of the analog data value output from the digital-analog converting means. Panel driving circuit. The method according to claim 2, wherein the DC / DC conversion means, And comparing means for comparing a level control signal of an analog data value output from said digital-analog conversion means with a predetermined internal reference voltage, And a data pulse voltage reduced by a predetermined level from the data pulse voltage of the predetermined level in response to a comparison result of the comparing means.