KR20010045394A - Method for forming gate electrode in semiconductor device - Google Patents
Method for forming gate electrode in semiconductor device Download PDFInfo
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- KR20010045394A KR20010045394A KR1019990048664A KR19990048664A KR20010045394A KR 20010045394 A KR20010045394 A KR 20010045394A KR 1019990048664 A KR1019990048664 A KR 1019990048664A KR 19990048664 A KR19990048664 A KR 19990048664A KR 20010045394 A KR20010045394 A KR 20010045394A
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- Prior art keywords
- gate electrode
- titanium silicide
- film
- forming
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 229910052786 argon Inorganic materials 0.000 claims abstract description 16
- 239000011261 inert gas Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000010405 reoxidation reaction Methods 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052743 krypton Inorganic materials 0.000 claims description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052754 neon Inorganic materials 0.000 claims description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052724 xenon Inorganic materials 0.000 claims description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
- 229910008484 TiSi Inorganic materials 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 description 7
- 229910008486 TiSix Inorganic materials 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
Description
본 발명은 반도체 소자의 게이트 전극을 형성하는 방법에 관한 것으로, 보다 구체적으로는 티타늄 실리사이드막(TiSi2)/폴리 실리콘막(Poly Silicon)의 적층 구조로 된 게이트 전극에서 불활성 가스에 의한 어닐링(Annealing)을 수행함으로써 티타늄 실리사이드막의 표면이 비정상적으로 산화되는 것을 방지하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, annealing by an inert gas in a gate electrode having a stacked structure of a titanium silicide film (TiSi 2 ) / polysilicon film. The present invention relates to a method of preventing abnormal oxidation of the surface of a titanium silicide film.
일반적으로 게이트 전극은 MOS 트랜지스터(Metal Oxide Semiconductor Transistor)를 선택하기 위한 전극으로서, 주로 불순물이 도핑된 폴리 실리콘막으로 형성되거나, 불순물이 도핑된 폴리 실리콘막과 텅스텐 실리사이드막(WSi2)의 적층막으로 형성된다.In general, the gate electrode is an electrode for selecting a metal oxide semiconductor transistor (MOS transistor), and is mainly formed of a polysilicon film doped with impurities, or a laminated film of a polysilicon film and a tungsten silicide film WSi 2 doped with impurities. Is formed.
그러나, 상기한 불순물이 도핑된 폴리 실리콘막과 불순물이 도핑된 폴리 실리콘막/텅스텐 실리사이드막(WSi2)은 낮은 집적도를 갖는 반도체 소자에는 용이하게 사용되었으나, 현재의 고집적 반도체 소자의 미세 게이트 전극으로는 낮은 저항값을 얻을 수 없어서 이를 사용하는데 문제점이 있다.However, the above-described impurity doped polysilicon film and the impurity doped polysilicon film / tungsten silicide film (WSi 2 ) have been easily used in semiconductor devices having low integration, but have been used as fine gate electrodes of current highly integrated semiconductor devices. Has a problem in using it because a low resistance value cannot be obtained.
따라서, 종래의 텅스텐 실리사이드막 보다 비저항이 더욱 낮은 티타늄 실리사이드막(TiSi2)을 폴리 실리콘막 상부에 적층하여 게이트 전극을 형성하는 방법이 제안되었다.Accordingly, a method of forming a gate electrode by stacking a titanium silicide layer (TiSi 2 ) having a lower specific resistance than a conventional tungsten silicide layer is formed on the polysilicon layer.
도 1a 내지 도 1e를 참조하여 이를 설명하면 다음과 같다.This will be described with reference to FIGS. 1A to 1E.
먼저, 도 1a를 참조하면, 반도체 기판(1) 상부에 게이트 산화막(2)을 열 성장 또는 증착 방식에 의하여 형성한 다음, 상기 게이트 산화막(2) 상부에 저압 화학적 기상 증착법(Low Pressure Chemical Vapor Deposition: LPCVD)으로 불순물이 도핑된 폴리 실리콘막(3)을 소정 두께로 증착한다.First, referring to FIG. 1A, a gate oxide film 2 is formed on a semiconductor substrate 1 by thermal growth or deposition, and then a low pressure chemical vapor deposition method is formed on the gate oxide film 2. : LPCVD) deposits the polysilicon film 3 doped with impurities to a predetermined thickness.
그런 다음, 도 1b에 도시된 바와 같이, 상기 폴리 실리콘막(3) 상부에 물리적 증착 방법으로 티타늄 실리사이드막(TiSix: 4)을 증착하는데, 이 때의 티타늄 실리사이드막(TiSix: 4)은 비정질 상태이다.Then, as illustrated in FIG. 1B, a titanium silicide layer (TiSix) 4 is deposited on the polysilicon layer 3 by a physical deposition method, wherein the titanium silicide layer (TiSix) 4 is in an amorphous state. to be.
그 후에, 도 1c에 도시된 바와 같이, 상기 기판 결과물을 소정 온도에서 수 초 동안 급속 열처리 공정(Rapid Thermal Process: RTP)을 실시하여, 비정질 상태의 티타늄 실리사이드막(TiSix: 4)을 결정질 상태의 티타늄 실리사이드막(TiSi2: 5)으로 상변화(Phase Transformation)시킨다.Subsequently, as shown in FIG. 1C, the substrate resultant is subjected to a rapid thermal process (RTP) for a few seconds at a predetermined temperature, thereby forming an amorphous titanium silicide film (TiSix: 4) in a crystalline state. Phase transformation is performed with a titanium silicide layer (TiSi 2 : 5).
이어서, 도 1d에 도시된 바와 같이, 결정질 상태의 티타늄 실리사이드막(TiSi2: 5) 상부에 고집적 소자에서 자기 정합 콘택(Self Aligned Contact: SAC) 형성을 목적으로 사용되는 하드 마스크(Hard Mask)막(6)으로 산화막 또는 질화막을 증착시킨다. 그리고 나서, 상기 하드 마스크 막(6)을 이용한 공지의 포토 리소그라피(Photo Lithography) 방식을 이용하여 티타늄 실리사이드막(TiSi2: 5), 도핑된 폴리 실리콘막(3) 및 게이트 절연막(2)을 소정의 형태로 패터닝하여 게이트 전극을 형성한다.Subsequently, as shown in FIG. 1D, a hard mask film used for forming a self-aligned contact (SAC) in a highly integrated device on the titanium silicide layer (TiSi 2 : 5) in a crystalline state. An oxide film or a nitride film is deposited by (6). Then, the titanium silicide layer (TiSi 2 : 5), the doped polysilicon layer (3) and the gate insulating layer (2) are predetermined by using a known photo lithography method using the hard mask layer (6). Patterned in the form of to form a gate electrode.
다음으로, 도 1e에 도시된 바와 같이, 게이트 전극 형성을 위한 식각 공정시, 반도체 기판(1) 표면에 발생된 손상 및 식각 잔재물을 제거하고, 게이트 산화막(2)의 신뢰성을 회복하기 위하여 반도체 기판(1) 결과물의 재산화 공정을 진행한다. 이 때, 폴리 실리콘막(3) 뿐만 아니라 티타늄 실리사이드막(TiSi2: 5)의 측면 부분도 산화되는데, 이는 일반적으로 금속 실리사이드 막이 산화에 약하기 때문이다.Next, as shown in FIG. 1E, in the etching process for forming the gate electrode, in order to remove damage and etching residues generated on the surface of the semiconductor substrate 1 and to restore the reliability of the gate oxide film 2. (1) Proceed with the process of property regeneration. At this time, not only the polysilicon film 3 but also the side portion of the titanium silicide film (TiSi2: 5) is oxidized, because the metal silicide film is generally weak to oxidation.
상기와 같은 재산화 공정은 예를 들어, 800 ℃ 이상의 온도에서 열 산화하는 것으로, 이와 같은 재산화 공정에 의하여 노출된 반도체 기판(1) 표면, 게이트 산화막(2), 폴리 실리콘막(3) 및 티타늄 실리사이드막(TiSi2: 5)의 측벽 부분에 산화막(7)이 형성되는데, 특히 티타늄 실리사이드막(TiSi2: 5)의 측면 부분이 비정상적으로 산화된다.The reoxidation process as described above is, for example, thermal oxidation at a temperature of 800 ° C. or higher, and the semiconductor substrate 1 surface, the gate oxide film 2, the polysilicon film 3, titanium silicide films (TiSi 2: 5), the oxide film 7 to the side wall of this is formed, in particular, titanium silicide film: the side portion of (5 TiSi 2) is abnormally oxidized.
이 때 온도를 750 ℃ 이하로 하여 재산화 공정을 수행하는 경우에는 티타늄 실리사이드막(TiSi2) 표면에 성장되는 산화막의 두께가 폴리 실리콘 표면에서 성장된 산화막의 두께와 유사해져서 재산화 공정 시에 나타나는 비정상적인 산화가 완화된다.In this case, when the reoxidation process is performed at a temperature of 750 ° C. or lower, the thickness of the oxide film grown on the surface of the titanium silicide layer (TiSi 2 ) becomes similar to that of the oxide film grown on the surface of the polysilicon. Abnormal oxidation is alleviated.
도 2a 와 도 2b에는 온도를 각각 800 ℃이상과 750 ℃ 이하로 하여 재산화 공정을 진행한 경우에 있어서, 게이트 전극의 산화 상태를 도시하였다. 도 2b에 도시된 바와 같이 750 ℃ 이하의 재산화 공정에서 나타나는 산화 형태(7b)는 800 ℃ 이상의 재산화 공정에 의한 산화 형태(7a)에 비해 안정적으로 수행된 것을 볼 수 있으나, 상기와 같이 온도를 750 ℃ 이하로 하여 재산화 공정을 실험한 결과, 웨이퍼(Wafer) 상의 일부분에서 여전히 비정상적인 산화가 국부적으로 발견되는 것을 볼 수 있었다.2A and 2B show the oxidation state of the gate electrode when the reoxidation process is carried out at temperatures of 800 ° C. or higher and 750 ° C. or lower, respectively. As shown in FIG. 2B, the oxidized form 7b exhibited in the reoxidation process of 750 ° C. or less is more stably performed than the oxidized form 7a by the reoxidation process of 800 ° C. or higher. When the reoxidation process was tested at below 750 ° C., it was found that abnormal oxidation was still found locally in a portion on the wafer.
한편, 폴리 실리콘막과 텅스텐 실리사이드막(WSi2)의 적층 구조로 게이트 전극을 형성하는 경우에는 게이트 전극 재산화 공정 전에 800 ℃ 내지 950 ℃에서 30 분 내지 90 분 동안 질소 어닐링을 진행하면, 상기 텅스텐 실리사이드막(WSi2)에 과잉으로 존재하는 실리콘이 확산되어 텅스텐 실리사이드막(WSi2)의 측면이 실리콘 과잉(Silicon-rich) 상태로 된다. 따라서, 질소 어닐링 후에 재산화 공정을 진행하면 텅스텐 실리사이드막(WSi2)의 측면도 폴리 실리콘막의 측면과 유사한 산화 특성을 나타내게 되어 재산화 공정이 안정적으로 수행되는 것으로 알려져 있다.On the other hand, when forming a gate electrode with a laminated structure of a polysilicon film and a tungsten silicide film (WSi 2 ), if the nitrogen annealing is performed for 30 minutes to 90 minutes at 800 ℃ to 950 ℃ before the gate electrode reoxidation process, the tungsten the silicone is present in an excessive diffusion of the silicide film (WSi 2) the sides of the tungsten silicide film (WSi 2) is a silicon excess (silicon-rich) conditions. Therefore, when the reoxidation process is performed after nitrogen annealing, the side surface of the tungsten silicide film WSi 2 also exhibits similar oxidation characteristics to the side surface of the polysilicon film, so that the reoxidation process is stable.
폴리 실리콘막과 티타늄 실리사이드막의 적층 구조로 형성된 게이트 전극에 상기와 같은 조건을 적용하는 경우, 즉, 게이트 재산화 공정 전에 800 ℃ 내지 950 ℃의 온도로 30 분 내지 90 분 동안 폴리 실리콘막과 티타늄 실리사이드막의 게이트 전극에 질소 어닐링을 진행하였다.When the above conditions are applied to the gate electrode formed of the laminated structure of the polysilicon film and the titanium silicide film, that is, the polysilicon film and the titanium silicide for 30 minutes to 90 minutes at a temperature of 800 ° C to 950 ° C before the gate reoxidation process Nitrogen annealing was performed to the gate electrode of the film.
그러나, 이 경우에는 도 3에 도시된 바와 같이, 상기 텅스텐 실리사이드막의 경우와는 달리 오히려 티타늄 실리사이드막의 측면 부분의 형상(7c)이 더욱 악화되었다. 이는, 질소 어닐링 초기에 티타늄 실리사이드막(TiSi2)의 티타늄과 질소가 반응하여 티타늄 질화막(TiN)이 형성되기 때문이다.However, in this case, unlike in the case of the tungsten silicide film, as shown in Fig. 3, the shape 7c of the side portion of the titanium silicide film is further worsened. This is because the titanium nitride film TiN is formed by reacting titanium and nitrogen of the titanium silicide film TiSi 2 at the initial stage of nitrogen annealing.
다시 말해서, 티타늄 질화막(TiN)은 산화가 쉽게 되는 특성이 있어서 질소 어닐링 후의 게이트 재산화 공정에서 티타늄 질화막(TiN)이 산화되어 버리기 때문에, 게이트 전극의 측면(7c)은 오히려 산화가 불안정하게 된다.In other words, since the titanium nitride film TiN is easily oxidized and the titanium nitride film TiN is oxidized in the gate reoxidation process after nitrogen annealing, the side surface 7c of the gate electrode is rather unstable in oxidation.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 게이트 재산화 공정 전에 아르곤 등의 불활성 가스를 이용하여 어닐링을 진행함으로써 안정적인 재산화 공정을 수행하도록 하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to perform a stable reoxidation process by annealing using an inert gas such as argon before the gate reoxidation process.
도 1a 내지 도 1e는 종래의 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 각 공정별 단면도,1A to 1E are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a conventional semiconductor device;
도 2a는 상기 도 1의 경우에 있어서, 800 ℃ 이상에서 게이트 재산화 공정을 진행한 경우의 단면도,FIG. 2A is a cross-sectional view when the gate reoxidation process is performed at 800 ° C. or higher in the case of FIG. 1;
도 2b는 상기 도 1의 경우에 있어서, 750 ℃ 이하에서 게이트 재산화 공정을 진행한 경우의 단면도,FIG. 2B is a cross-sectional view when the gate reoxidation process is performed at 750 ° C. or lower in the case of FIG. 1;
도 3은 티타늄 실리사이드/폴리 실리콘 구조의 게이트 전극에 있어서 질소 어닐링을 실시한 후 게이트 재산화 공정을 진행한 경우의 단면도,3 is a cross-sectional view when a gate reoxidation process is performed after nitrogen annealing is performed on a titanium silicide / polysilicon structure gate electrode;
도 4a 내지 도 4e는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 각 공정별 단면도.4A to 4E are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 명칭)(Name of the code for the main part of the drawing)
11: 반도체 기판 12: 게이트 산화막11: semiconductor substrate 12: gate oxide film
13: 폴리 실리콘막 14: 비정질 티타늄 실리사이드막13: polysilicon film 14: amorphous titanium silicide film
15: 결정질 티타늄 실리사이드막 16: 하드 마스크막15: crystalline titanium silicide film 16: hard mask film
17: 게이트 재산화막17: gate property curtain
상기한 목적을 달성하기 위하여, 본 발명은 반도체 기판 상에 게이트 산화막, 불순물이 도핑된 폴리 실리콘막 및, 티타늄 실리사이드막을 순차적으로 적층하는 단계와, 하드 마스크막을 이용하여 상기 티타늄 실리사이드막, 폴리 실리콘막 및 게이트 산화막을 소정 형태로 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극이 형성된 기판 결과물을 불활성 가스 분위기에서 어닐링하는 단계와, 상기 게이트 전극을 재산화 하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of sequentially depositing a gate oxide film, a polysilicon film doped with an impurity, and a titanium silicide film on a semiconductor substrate, and using the hard silicide film, the titanium silicide film, polysilicon film And forming a gate electrode by patterning a gate oxide film into a predetermined shape, annealing a substrate resultant on which the gate electrode is formed in an inert gas atmosphere, and reoxidizing the gate electrode.
상기 티타늄 실리사이드막은 티타늄 대 실리콘의 비를 1 : 2.1 내지 1 : 3 정도로 하여 실리콘이 과잉 상태가 되도록 증착하는 것을 특징으로 한다.The titanium silicide film is characterized in that the silicon is deposited so that the ratio of titanium to silicon is about 1: 2.1 to 1: 3 so as to be in an excessive state.
상기 불활성 가스는 헬륨(He), 네온(Ne), 아르곤(Ar), 크세논(Xe) 또는 크립톤(Kr) 중의 어느 하나를 사용하는 것을 특징으로 한다.The inert gas is characterized by using any one of helium (He), neon (Ne), argon (Ar), xenon (Xe) or krypton (Kr).
상기에서 불활성 가스로 아르곤(Ar) 가스를 사용하는 경우에는 700 내지 1,000 ℃의 온도와, 100 Torr 내지 상압(760 Torr)의 압력에서 10 분 내지 90 분 동안 아르곤 어닐링을 진행하는 것을 특징으로 한다.When argon (Ar) gas is used as the inert gas, argon annealing is performed for 10 to 90 minutes at a temperature of 700 to 1,000 ° C. and a pressure of 100 Torr to 760 Torr.
상기 재산화 공정은 700 내지 750 ℃의 건식 산화 분위기에서 20 내지 100 Å의 타겟 두께로 진행하는 것을 특징으로 한다.The reoxidation process is characterized in that it proceeds to a target thickness of 20 to 100 kPa in a dry oxidizing atmosphere of 700 to 750 ℃.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 4a 내지 도 4e는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 각 공정별 단면도이다. 상기 도면을 참조하여, 본 발명의 게이트 전극 형성 방법을 설명하면 다음과 같다.4A to 4E are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention. Referring to the drawings, the gate electrode forming method of the present invention will be described.
먼저, 도 4a에 도시된 바와 같이, 반도체 기판(11) 상부에 게이트 산화막(12)을 형성한 다음, 상기 게이트 산화막(12) 상부에 불순물이 도핑된 폴리 실리콘막(13)을 소정 두께로 증착한다. 이 때, 상기 폴리 실리콘막(13)은 저압 화학적 기상 증착(LPCVD) 방법으로 비저항이 낮은 폴리 실리콘막(13)을 증착한다.First, as shown in FIG. 4A, a gate oxide layer 12 is formed on the semiconductor substrate 11, and then a polysilicon layer 13 doped with impurities is deposited on the gate oxide layer 12 to a predetermined thickness. do. At this time, the polysilicon film 13 deposits a polysilicon film 13 having a low specific resistance by low pressure chemical vapor deposition (LPCVD).
그런 다음, 도 4b에 도시된 바와 같이, 상기 폴리 실리콘막(13) 상부에 비정질 상태의 티타늄 실리사이드막(TiSix: 14)을 증착한다. 상기의 비정질 티타늄 실리사이드막(TiSix: 14)은 물리적 기상 증착(Physical Vapor Deposition: PVD) 또는 화학적 기상 증착(CVD) 방법을 사용하여 증착하는데, 티타늄(Ti) 대 실리콘(Si)의 비가 1 : 2.1 내지 1 : 3 정도로 증착한다.Next, as shown in FIG. 4B, an amorphous titanium silicide layer (TiSix) 14 is deposited on the polysilicon layer 13. The amorphous titanium silicide layer (TiSix) 14 is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the ratio of titanium (Ti) to silicon (Si) is 1: 2.1. To 1: 3 deposition.
이렇게 실리콘을 과잉 상태로 증착하는 이유는, 이후의 열처리 공정에서 티타늄 실리사이드막의 측면을 실리콘 과잉 상태로 만들어 줌으로써, 재산화 공정에서 폴리 실리콘막과 티타늄 실리사이드막 측면에서의 산화막이 동일하게 성장되도록 하기 위함이다.The reason why the silicon is deposited in an excessive state is to make the side of the titanium silicide film in the excess silicon state in a subsequent heat treatment process so that the oxide film on the side of the polysilicon film and the titanium silicide film is grown equally in the reoxidation process. to be.
그 후에, 도 4c에 도시된 바와 같이, 상기 기판 결과물을 소정 온도에서 수 초 동안 급속 열처리 공정(RTP)을 실시하여, 비정질 상태의 티타늄 실리사이드막(TiSix: 14)을 결정질 상태의 티타늄 실리사이드막(TiSi2: 15)으로 상변화 시킨다.Thereafter, as shown in FIG. 4C, the substrate resultant is subjected to a rapid heat treatment process (RTP) for a few seconds at a predetermined temperature, so that an amorphous titanium silicide film (TiSix) 14 is formed in a crystalline titanium silicide film ( Phase change to TiSi 2 : 15).
이어서, 도 4d에 도시된 바와 같이, 결정질 티타늄 실리사이드막(TiSi2: 15) 상부에 하드 마스크용 산화막 또는 질화막을 증착시키고 나서, 상기 하드 마스크막(16)을 이용한 포토 리소그라피 방식을 통해 티타늄 실리사이드막(TiSi2: 15), 폴리 실리콘막(13) 및 게이트 절연막(12)을 식각하여 게이트 전극을 형성한다.Subsequently, as illustrated in FIG. 4D, an oxide film or nitride film for a hard mask is deposited on the crystalline titanium silicide film (TiSi 2 : 15), and then a titanium silicide film is formed through a photolithography method using the hard mask film 16. (TiSi 2 : 15), the polysilicon film 13 and the gate insulating film 12 are etched to form a gate electrode.
상기에서 형성된 게이트 전극에 불활성 가스를 이용하여 어닐링을 실시함으로써, 상기 티타늄 실리사이드막(TiSi2: 15) 내부에 존재하는 과잉 실리콘(Si)을 측면 부분으로 확산시킨다.By annealing the gate electrode formed using an inert gas, excess silicon (Si) present in the titanium silicide layer (TiSi 2 : 15) is diffused to the side portion.
이 때, 불활성 가스로 아르곤(Ar) 가스를 사용하는 경우에는 700 내지 1,000 ℃의 온도에서 10 분 내지 90 분 동안 진행하며, 이 때의 아르곤(Ar) 가스의 압력은 100 Torr 내지 상압인 760 Torr로 한다.In this case, when argon (Ar) gas is used as the inert gas, the process proceeds for 10 minutes to 90 minutes at a temperature of 700 to 1,000 ℃, the pressure of argon (Ar) gas at this time is 100 Torr to 760 Torr at normal pressure Shall be.
상기의 불활성 가스로 어닐링을 수행한 다음에, 재산화 공정을 진행하는데 상기의 아르곤 어닐링 후의 재산화 공정은 700 내지 750 ℃의 온도 조건과, 건식 산소 분위기에서 타겟 두께를 20 내지 100 Å으로 하여 진행한다.After annealing is carried out with the inert gas, the reoxidation process is performed. The reoxidation process after argon annealing is performed at a temperature of 700 to 750 ° C. and a target thickness of 20 to 100 kPa in a dry oxygen atmosphere. do.
도 4e에는 상기와 같은 아르곤 어닐링과 재산화 공정을 진행한 후에 게이트 재산화막(17)이 형성된 후의 모습을 보여준다. 도 4e를 참조하면, 아르곤 어닐링에 의해서 티타늄 실리사이드막(TiSi2: 15)의 측면 부분에 형성된 과잉 실리콘은 재산화 공정에서 티타늄이 먼저 산화되는 것을 차단함으로써, 폴리 실리콘막(13)과 티타늄 실리사이드막(15)의 산화 속도가 동일하게 유지되도록 한다.4E shows a state after the gate reoxidation film 17 is formed after the argon annealing and reoxidation processes as described above. Referring to FIG. 4E, the excess silicon formed on the side portion of the titanium silicide film (TiSi 2 : 15) by argon annealing prevents titanium from being oxidized first in the reoxidation process, thereby preventing the polysilicon film 13 and the titanium silicide film. The oxidation rate of (15) is kept the same.
따라서, 재산화 공정 후에도 폴리 실리콘막(13)과 티타늄 실리사이드막(15)에서 서로 상이한 두께의 산화막이 형성되지 않고, 동일한 두께의 산화막(17)이 형성됨으로써 안정적인 재산화 공정을 수행하게 된다.Therefore, even after the reoxidation process, oxide films having different thicknesses are not formed in the polysilicon film 13 and the titanium silicide film 15, and the oxide film 17 having the same thickness is formed to perform a stable reoxidation process.
상기에서 설명한 아르곤 어닐링 과정과 재산화 공정은 하나의 레시피(Recipe) 내에서 연속적으로 진행하는 경우를 예로 들어 설명하였으나, 아르곤 어닐링 과정과 게이트 재산화 공정을 독립적인 레시피 내에서 진행하는 것도 가능하다.Although the argon annealing process and the reoxidation process described above have been described by taking the case of continuously proceeding in one recipe, the argon annealing process and the gate reoxidation process may be performed in an independent recipe.
이상에서 자세히 설명된 바와 같이, 본 발명의 게이트 전극 형성 방법에 의하면, 폴리 실리콘막과 티타늄 실리사이드막의 구조로 이루어진 게이트 전극의 재산화 공정 전에, 아르곤 등의 불활성 가스에 의한 어닐링을 진행하여, 폴리 실리콘막과 티타늄 실리사이드막의 재산화 속도를 동일하게 유지함으로써 안정적인 재산화 공정을 확보할 수 있는 이점이 있다.As described in detail above, according to the gate electrode forming method of the present invention, annealing with an inert gas such as argon is performed before the reoxidation process of the gate electrode having the structure of the polysilicon film and the titanium silicide film, thereby obtaining polysilicon. By keeping the reoxidation rate of the film and the titanium silicide film the same, there is an advantage that a stable reoxidation process can be secured.
이하, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100472745B1 (en) * | 2002-10-31 | 2005-03-11 | 삼성전자주식회사 | Method for forming a gate electrode and forming a semiconductor device having the gate electrode and method for oxidation of substrate |
| KR100700926B1 (en) * | 2005-07-11 | 2007-03-28 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100472745B1 (en) * | 2002-10-31 | 2005-03-11 | 삼성전자주식회사 | Method for forming a gate electrode and forming a semiconductor device having the gate electrode and method for oxidation of substrate |
| KR100700926B1 (en) * | 2005-07-11 | 2007-03-28 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
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