KR20010039520A - Method for manufacturing capacitor of semiconductor memory device using electroplating method - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device by an electroplating method is provided to prevent an electrical characteristic of the capacitor from being degraded by a seed layer for the lower electrode left after the electroplating method, by completely eliminating a seed layer pattern for the lower electrode used in the electroplating process. CONSTITUTION: An active region and a conductive region electrically connected to the active region are formed in the semiconductor substrate(50). A seed layer for a lower electrode is formed. A plating mask layer is formed on the seed layer. The seed layer and the plating mask layer are patterned to form a seed layer pattern and a plating mask layer pattern which define a region for the lower electrode of a capacitor. A hole exposing the conductive region and a sidewall of the plating mask layer pattern is formed. An electroplating process is performed by using the seed layer pattern of which the sidewall is exposed by the hole, and a conductive layer(96) for the lower electrode is formed inside the hole. The plating mask layer pattern and the seed layer for the lower electrode are removed to expose the sidewall of the conductive layer so that the lower electrode of the capacitor is formed.

Description

Method for manufacturing capacitor of semiconductor memory device using electroplating method

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a capacitor of a semiconductor memory device using an electroplating method.

Recently, as the degree of integration of semiconductor memory devices increases, a method of increasing the capacitance of a capacitor within a limited cell area is to increase the electric field formed inside the capacitor by thinning the dielectric film of the capacitor and the structure of the capacitor lower electrode. A method of increasing the effective area of a capacitor by three-dimensionally has been proposed.

However, even if the above-described method is employed, when a conventional dielectric film such as a TiO ₂ film or a SiO ₂ film is used as the capacitor dielectric film, the semiconductor memory device having an integration degree of 1 G (giga) or more ensures capacitance required for device operation. There is a problem that is difficult to do. Therefore, in order to solve this problem, a capacitor dielectric film such as (Ba, Sr) TiO ₃ (BST), PbZrTiO ₃ (PZT), (Pb, La) (Zr, Ti) O ₃ (PLZT) or a high dielectric film There is an active research to form a.

For example, according to the method of manufacturing a semiconductor memory device according to the related art, in which a high dielectric film or a ferroelectric film is formed as a capacitor dielectric film, first, a lower electrode pad made of doped polysilicon is formed on an impurity implantation region formed on a semiconductor substrate. . Thereafter, a lower electrode contact electrically connected to the lower electrode pad is formed, and then a capacitor lower electrode is formed on the lower electrode contact. Then, a capacitor dielectric film made of a high dielectric film or a ferroelectric film is formed on the capacitor lower electrode, and the capacitor dielectric film is crystallized to enhance insulation characteristics, thereby improving the capacitance of the capacitor and reducing the capacitor leakage current under an oxygen atmosphere. A high temperature heat treatment process is performed. However, since the high temperature heat treatment process is performed under a high temperature and oxygen atmosphere between 600 ° C. and 900 ° C., when the capacitor lower electrode is formed of doped polysilicon, which is a general electrode material, the capacitor lower part during the high temperature heat treatment process is performed. The electrode may be oxidized to deteriorate contact resistance, or a metal silicide layer may be formed between the capacitor dielectric layer and the capacitor lower electrode.

Accordingly, when manufacturing a capacitor of a semiconductor memory device using a high dielectric film or a ferroelectric film, it is common to use a platinum group element or an oxide thereof, for example, Pt, Ir, Ru, RuO ₂ , IrO _2, or the like as an electrode material. to be.

In the prior art, in order to form a lower electrode using a platinum group metal, first, a conductive film made of the platinum group metal was formed and then patterned by a dry etching method to form a lower electrode. However, it is known that a conductive film made of a platinum group metal is not easy to be converted into a volatile gas form by a dry etching method, and thus it is very difficult to separate the lower electrodes by unit cells. Therefore, when fabricating a semiconductor memory device having a lower electrode width of 300 nm or less, in particular, a semiconductor memory device having an integration degree of 4 Gbits or more, there is a limit in forming the lower electrode by a dry etching method. As a result, various methods for forming the capacitor lower electrode have been proposed.

Therefore, hereinafter, a conventional technique of forming a capacitor lower electrode of a platinum group metal by using an electroplating method will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of forming a capacitor lower electrode made of a Pt film using an electroplating method.

Referring to FIG. 1A, according to the prior art of forming a capacitor lower electrode using an electroplating method, first, a lower electrode pad 12 made of conductive polysilicon on an impurity implantation region (not shown) on a semiconductor substrate 10 is described. To form. Subsequently, an interlayer insulating film 14 for electrically separating adjacent lower electrode pads 12 is formed on the lower electrode pads 12. Then, the interlayer insulating layer 14 is patterned by a photolithography process to form holes 16 exposing the lower electrode pads 11, and then the bottom surface, sidewalls, and top surfaces of the interlayer insulating layer 14 are formed. On the lower electrode seed layer 18 made of a platinum group metal is formed. Then, the plating mask layer pattern 20 defining the shape of the lower electrode is formed around the hole 16 while exposing only the region where the lower electrode is to be formed on the lower electrode seed layer 18.

After forming the lower electrode seed layer 18 and the plating mask layer pattern 20, a capacitor lower electrode forming process using an electroplating method is performed. For example, in order to form a capacitor lower electrode made of Pt, the semiconductor substrate 10 is immersed in a plating solution in which a metal salt containing Pt is dissolved. The cathode is connected to the lower electrode seed layer 18 through the first wiring 24, and the anode of the power source 22 is connected to the source electrode 28 made of Pt through the second wiring 26. Then, Pt is deposited on the lower electrode seed layer 18 to form a Pt film at substantially the same level as the upper surface of the plating mask layer pattern 20. As a result, a lower electrode contact 30 is formed at the bottom of the hole 16 with a dotted line border, and a capacitor lower electrode 32 is formed on the lower electrode contact 30 in which a dielectric film is formed in a subsequent process.

Referring to FIG. 1B, after forming the lower electrode contact 30 and the capacitor lower electrode 32 using an electroplating method, the plating mask layer pattern 20 is removed using a wet etching method. Then, the lower electrode seed layer 18 on the upper surface of the interlayer insulating film 14 exposed by removing the plating mask layer pattern 20 is removed to separate the lower electrode 32 by unit cell.

However, when the lower electrode seed layer 18 is made of Pt, the lower electrode seed layer 18 exposed by the removal of the plating mask layer pattern 20 should be removed by a dry etching method. However, since Pt is not easy to convert into a volatile gaseous compound even when using a dry etching method, it is difficult to separate the capacitor lower electrode for each unit cell. In particular, in the fabrication of semiconductor memory devices having a design rule of 0.15 μm or less, the pitch of the lower electrode seed layer 18 exposed between the lower electrodes 32 is further reduced, so that the capacitor lower electrode is unit cell. It is more difficult to separate them.

Therefore, in order to solve this problem, a method of forming the lower electrode seed layer 18 into Ru, which is easy to convert into a volatile gas phase compound, has been proposed by using a dry etching method. However, when the lower electrode seed layer 18 is formed of Ru, an alloy of Pt and Ru is formed at the interface between the lower electrode contact 30 made of Pt and the lower electrode seed layer 18 remaining after the node separation. This causes problems in subsequent heat treatment steps of the capacitor dielectric film. This will be described below with reference to FIG. 1C.

Referring to FIG. 1C, after the capacitor lower electrode 32 is separated for each unit cell by performing a node separation process, a dielectric layer 33 made of a ferroelectric material or a high dielectric material is formed over the resultant. Then, in order to enhance the insulating properties of the dielectric film 33, a high temperature heat treatment process (see arrow) is performed in an oxygen atmosphere. However, when the lower electrode seed layer 18 remaining after the node separation is Ru, Pt and Ru may be formed at the interface between the lower electrode seed layer 18 made of Ru and the lower electrode contact 30 made of Pt. An alloy is formed, and Ru, whose oxidation resistance is weaker than Pt among the elements contained in the alloy, is oxidized in the high temperature heat treatment step of the dielectric film 33. As such, when an oxide of Ru having a volume larger than Pt is produced in the high temperature heat treatment step of the dielectric film 33, the morphology of the capacitor lower electrode 32 is changed, resulting in physical stress on the dielectric film 33, thereby lowering the capacitor. The interface property between the electrode 32 and the dielectric film 33 is deteriorated. This results in an increase in the leakage current of the capacitor.

The technical problem to be achieved by the present invention is to easily remove the seed layer for the lower electrode used in the electroplating process even if the capacitor lower electrode is formed using the electroplating method, the semiconductor layer does not remain the seed layer for the lower electrode in the completed capacitor It is to provide a method of manufacturing a capacitor of a memory device.

Another technical problem to be achieved by the present invention is that when the capacitor lower electrode is formed by using an electroplating method, even when the lower electrode seed layer and the capacitor lower electrode are formed of different materials, the electrical characteristics of the capacitor are lower electrode seed. It is to provide a method of manufacturing a capacitor of a semiconductor memory device that can be prevented from being degraded by a layer.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device, which does not require forming a bottom electrode contact made of a barrier material before performing an electroplating process for forming a capacitor bottom electrode.

1A to 1C are cross-sectional views illustrating a process of forming a capacitor lower electrode using an electroplating method according to the related art.

2 is a layout diagram to which a method for manufacturing a capacitor of a semiconductor memory device using the electroplating method according to the present invention is applied.

3A through 3F are process cross-sectional views showing a first embodiment of the present invention.

4 is a process sectional view showing a second embodiment of the present invention.

5A to 5F are cross-sectional views showing a third embodiment of the present invention.

6A to 6D are process cross-sectional views showing a fourth embodiment of the present invention.

7A to 7B are process cross-sectional views showing a fifth embodiment of the present invention.

The method of manufacturing a semiconductor memory device using the electroplating method according to an aspect of the present invention for achieving the above technical problem, for the lower electrode on the semiconductor substrate is first formed a conductive region electrically connected to the active region on the semiconductor substrate A seed layer is formed. Then, a plating mask layer is formed on the seed layer. Subsequently, the seed layer and the plating mask layer are patterned to form a seed layer pattern and a plating mask layer pattern, thereby defining a region where a capacitor lower electrode is to be formed and forming a hole exposing the conductive region. Then, an electroplating process is performed using the seed layer pattern in which sidewalls are exposed by the holes, thereby forming a lower electrode conductive film in the holes. Thereafter, the capacitor lower electrode is formed by removing the plating mask layer pattern and the seed layer pattern for the lower electrode so that the sidewall of the conductive film is exposed. Next, a capacitor dielectric layer is formed on the capacitor lower electrode, and a capacitor upper electrode is formed on the capacitor dielectric layer.

The seed layer may be formed of a multilayer film including a platinum group metal film, a platinum group metal oxide film, a conductive material film having a perovskite structure, a conductive metal film, a metal silicide film, a metal nitride film, or a combination thereof.

The plating mask layer may include a boro-phospho-silicate glass (BPSG) film, a spin-on glass (SOG) film, a phosphor-silicate glass (PSG) film, a photoresist film, a diamond like carbon (DLC) film, a SiO _x film, It is possible to form a multilayer film made of a SiN _x film, a SiON _x film, a TiO _x film, an AlO _x film, an AlN _x film, or a combination thereof.

The plating mask layer pattern and the seed layer pattern may be removed by performing a wet or dry etching process, respectively. In some cases, the plating mask layer pattern and the seed layer pattern for the lower electrode may be removed by performing one wet or dry etching process.

An etch stop layer may be formed before the seed layer for the lower electrode is formed. In this case, the lower electrode seed layer is formed on the etch stop layer, and the hole is formed by patterning the plating mask layer, the lower electrode seed layer, and the etch stop layer.

The capacitor upper electrode may be formed using an electroplating method.

In a method of manufacturing a capacitor of a semiconductor memory device using an electroplating method according to another aspect of the present invention, first, a lower electrode pad made of a conductive material is formed on an active region of a semiconductor substrate, and then a first interlayer is formed on the lower electrode pad. An insulating film is formed. Then, a bit line is formed on the first interlayer insulating film, and a second interlayer insulating film is formed on the bit line. Then, a seed layer for the lower electrode is formed on the second interlayer insulating film, and a plating mask layer is formed on the seed layer for the lower electrode. Thereafter, the plating mask layer, the seed layer for the lower electrode, the second interlayer insulating layer, and the first interlayer insulating layer are patterned to form holes for exposing the lower electrode pads. Next, the inside of the hole is filled with a conductive film, and at least a conductive film on a level substantially the same as the upper surface of the lower electrode seed layer is formed by performing an electroplating process using a patterned lower electrode seed layer. . After that, the patterned mask layer and the lower electrode seed layer are removed to expose sidewalls of the conductive film to form a capacitor lower electrode. Subsequently, a capacitor dielectric layer is formed on the capacitor lower electrode, and a capacitor upper electrode is formed on the capacitor dielectric layer.

The forming of the conductive film may be performed as follows. First, a conductive barrier layer is formed on the lower electrode pad exposed at the bottom of the hole, but not to cover sidewalls of the lower electrode seed layer exposed by the hole. Then, an electroplating process using the patterned lower electrode seed layer is performed to form a conductive layer for the lower electrode on the barrier layer.

The forming of the barrier film may be performed as follows. First, a barrier material is formed in the hole and on the patterned mask layer. The top of the barrier material is then removed to expose the top surface of the patterned plating mask layer. Thereafter, the barrier material formed in the hole is selectively removed to expose the sidewall of the patterned lower electrode seed layer.

The barrier layer may be formed of a multilayer formed of a metal silicide layer, a metal nitride layer, a doped polysilicon layer, or a combination thereof.

The plating mask layer and the lower electrode seed layer patterned in the hole forming step may be removed by performing a wet or dry etching process. In some cases, the plating mask layer and the lower electrode seed layer patterned in the hole forming step may be removed by performing a single wet etching process.

An etch stop layer may be further formed on the second interlayer insulating layer before forming the seed layer for the lower electrode.

Prior to forming the second interlayer insulating layer, a spacer and a capping insulating layer may be formed of a material layer having an etching selectivity with the second interlayer insulating layer on the sidewalls and the upper surface of the bit line, respectively. In this case, the holes may be self-aligned by bit lines masked by spacers and capping insulating layers.

Prior to forming the conductive layer in the hole, a liner seed layer electrically connected to the seed layer sidewall for the lower electrode exposed by the hole may be formed at the bottom of the hole.

The liner seed layer forming step may proceed as follows. First, a hemispherical seed is formed on the sidewall of the seed layer for the lower electrode exposed by the hole. The hemispherical seed is then reactive ion etched at low temperature to redeposit on the bottom of the hole to form the liner seed layer.

The liner seed layer forming step may proceed as follows. First, the entire surface of the semiconductor substrate on which the holes are formed is lined with a conductive film. Then, the conductive film is reactive ion etched at a low temperature to form the liner seed layer in the form of a spacer.

The lower electrode pad may be formed of multiple layers, and the uppermost layer of the lower electrode pad may be formed of a conductive barrier layer.

The lower electrode pad may be formed of multiple layers, and the uppermost layer of the lower electrode pad may be a platinum group metal layer, and the lower electrode pad may include at least one conductive barrier layer. In this case, the liner seed layer may be formed by reactive ion etching a platinum group metal film, which is the uppermost layer of the lower electrode pad, at a low temperature.

When the capacitor lower electrode is formed by applying the capacitor manufacturing method according to the present invention, the problem of the prior art generated when the lower electrode is separated for each unit cell by a dry etching method is solved. In addition, according to another aspect of the present invention, since the self-aligning technique using the masked bit line may be applied when forming the hole exposing the lower electrode pad, the hole may be formed by only one photo process. Further, according to another aspect of the present invention, after forming the lower electrode by the electroplating method, it is possible to completely remove the seed layer pattern for the lower electrode by a simple method. Accordingly, the electrical characteristics of the capacitor can be prevented from being degraded by the seed layer for the lower electrode remaining after the electroplating process. In addition, according to another aspect of the present invention, the lower electrode and the lower electrode seed layer need not necessarily be formed of the same material, and may be freely selected as necessary.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the invention may be modified in many different forms, the scope of the invention is not limited to the embodiments described in the following. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In the accompanying drawings, the thicknesses of layers or regions are exaggerated for clarity of specification. Like reference numerals in the accompanying drawings indicate like elements. In addition, where a layer is described as being on the "top" of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third other layer interposed therebetween.

First, a layout in which a capacitor manufacturing method of a semiconductor memory device according to the present invention is implemented will be described with reference to FIG. 2.

Referring to FIG. 2, an active region A is defined by an isolation layer, and two word lines W / L pass through the active region A. Referring to FIG. The bit line B / L has a layer different from the word line W / L and passes perpendicular to the word line W / L. There is a bit line contact I on the drain region formed on the active region A, and a lower electrode contact II on the source region formed on the active region A. FIG. On the lower electrode contact II, there is a capacitor lower electrode C of the semiconductor memory device. Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings, which will be described with reference to a cross section taken along the line BB ′ of FIG. 2.

<First Example>

3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 3A, a seed layer 52 for lower electrodes is first formed on a semiconductor substrate 50. Although not specifically illustrated, the semiconductor substrate 50 may be a silicon substrate in which an impurity implantation region is formed, or a silicon substrate including a film structure such as a gate electrode and a bit line on an upper surface thereof.

The lower electrode seed layer 52 may be formed of a conductive material having oxidation resistance. For example, the lower electrode seed layer 52 may be a platinum group metal film, a platinum group metal oxide film, a conductive material film having a perovskite structure, a conductive metal film, a metal silicide film, a metal nitride film, or a combination thereof. It can be formed into a multilayer formed. The platinum group metal film may be a Pt film, an Rh film, a Ru film, an Ir film, an Os film, or a Pd film, and the platinum group metal oxide film may be a PtO _x film, a RhO _x film, a RuO _x film, an IrO _x film, an OsO _x film, or a PdO film. _x can makil the conductive perovskite CaRuO ₃ layer film is a conductive material having a structure, SrRuO ₃ film, BaRuO ₃ film, BaSrRuO ₃ film, CaIrO ₃ film, SrIrO ₃ film, BaIrO ₃ film, or (La, Sr) CoO ₃ film, the conductive metal film may be a Cu film, Al film, Ta film, Mo film, W film, Au film or Ag film, the metal silicide film is WSi _x film, TiSi _x film, CoSi _x film, MoSi _x film or TaSi _x film, and the metal nitride film may be a TiN film, a TaN film, a WN film, a TiSiN film, a TiAlN film, a TiBN film, a ZrSiN film, a ZrAlN film, a MoSiN film, a MoAlN film, a TaSiN film, or a TaAlN film. .

The lower electrode seed layer 52 may be formed of a material film that is easily oxidized and easily removed by a wet etching method or a dry etching method. This is because a part of the lower electrode seed layer 52 must be removed by a wet etching method or a dry etching method in a subsequent process. For example, when a part of the lower electrode seed layer 52 is removed by a dry etching method in a subsequent process, the lower electrode seed layer 52 may be formed of a Ru film. In addition, when a part of the lower electrode seed layer 52 is removed by a wet etching method in a subsequent process, the lower electrode seed layer 52 may be formed of Cu or Ag.

The lower electrode seed layer 52 may be formed using a sputtering method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method or a laser deposition method, but for forming the lower electrode seed layer 52. The preferred method may vary depending on the type of material film for forming the lower electrode seed layer 52.

For example, when the lower electrode seed layer 52 is formed of a Ru film, it is preferable to form the sputtering method. When forming the seed layer 52 for the lower electrode made of the Ru film by using a sputtering method, a DC sputtering equipment can be used. At this time, the DC power is about 1,000 W, the flow rate of Ar gas is about 20 sccm, the temperature of the wafer is set to about 200 ℃ can form the seed layer 52 for the lower electrode of the Ru film.

Preferably, the lower electrode seed layer 52 is formed to a thickness of about 50 to 2000 microns. For example, when the lower electrode seed layer 52 is formed of a Ru film, the lower electrode seed layer 52 may be formed to a thickness of about 500 GPa.

After forming the lower electrode seed layer 52 as described above, a plating mask layer 54 is formed on the lower electrode seed layer 52. Since the plating mask layer 54 is used as a plating mask in a subsequent electroplating process, the plating mask layer 54 should be a non-conductor and can be easily removed by a dry or wet etching method after forming the capacitor lower electrode. Therefore, the plating mask layer 54 may include a boro-phospho-silicate glass (BPSG) film, a spin-on glass (SOG) film, a phosphor-silicate glass (PSG) film, a photoresist film, and a diamond like carbon (DLC) film. It is preferable to form a multilayer film made of a SiO _x film, a SiN _x film, a SiON _x film, a TiO _x film, an AlO _x film, an AlN _x film or a combination thereof.

The plating mask layer 54 may be formed by a sputtering method, a chemical vapor deposition method, a physical vapor deposition method or an atomic layer deposition method. A preferred method for forming the plating mask layer 54 is the plating mask layer 54. It may vary depending on the type of material film for forming the film. For example, when the plating mask layer 54 is formed of a silicon oxide film, it is preferable to form using the chemical vapor deposition method.

The formation thickness of the plating mask layer 54 is determined by the size of the capacitor lower electrode to be formed. For example, when forming a capacitor lower electrode having a height of about 1000 mW, the plating mask layer 54 may be formed to a thickness of about 1000 mW.

Referring to FIG. 3B, a portion of the plating mask layer 54 formed on the lower electrode formation region of the plating mask layer 54 and the lower electrode seed layer 52 below the reactive ion are formed by performing a photolithography process. The plating mask layer pattern 54 'and the seed layer pattern 52' for the lower electrode are formed by selectively removing the wafer by a reactive ion etching method. In this case, the hole H1 exposing the conductive region 56 on the semiconductor substrate 50, that is, the region on which the lower electrode is to be formed, is exposed by the plating mask layer pattern 54 ′ and the seed layer pattern 52 ′ for the lower electrode. ) Is defined. In addition, a sidewall of the seed layer pattern 52 'for the lower electrode and a sidewall of the plating mask layer pattern 54' are exposed on the sidewall of the hole H1.

Referring to FIG. 3C, a step of forming the lower electrode conductive film 66 in the hole H1 is performed by using an electroplating method. That is, the cathode of the power source 58 is connected to the seed layer pattern 52 ′ for the lower electrode through the first wiring 60, and the anode of the power source 58 is the source electrode (via the second wiring 62). 64). In this state, the semiconductor substrate 50 is immersed in a plating solution and electroplated. Then, on the sidewall of the lower electrode seed layer pattern 52 ′ exposed inside the hole H1, metal of substantially the same type as the source electrode 64 starts to precipitate. The lower electrode conductive film 66 made of a metal deposited on the sidewall of the lower electrode seed layer pattern 52 ′ is filled in the hole H1 to a height corresponding to the height of the capacitor lower electrode to be formed. For example, the lower electrode conductive film 66 may be filled to substantially the same level as the upper surface of the plating mask layer pattern 54 ′.

When the lower electrode conductive film 66 is formed of a Pt film, ammonium nitrite platinum solution (Pt (NH ₃ ) ₂ (NO ₂ ) ₂ ) is used as a plating solution, and the platinum electrode is used as a source electrode ( 64). At this time, as the electroplating condition, the temperature of the plating bathtub was 70 to 90 ° C, the concentration of the plating liquid was 8 to 12 g / l, the pH of the plating liquid was 0.8 to 4, and the concentration of the conductive salt sulfuric acid in the plating liquid was 0.5-1.5 g / l and current density can be 0.1-2 A / cm <^2> .

When the lower electrode conductive film 66 is formed of a Pt film, ammonium chloroplatinate (NH ₄ ) ₂ PtCl ₆ ) or chloroplatinic acid (H ₂ PtCl ₆ ) may be used as the plating solution. have.

Of course, when a plating liquid containing another metal salt is used as the plating liquid instead of platinum, the metal contained in the metal salt can be filled in the hole H1. As the plating solution, a plating solution in which a metal salt containing Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni, or a combination thereof is dissolved may be used. For example, (NH ₄ ) ₂ PtCl ₆ , H ₂ PtCl ₆ , RuNOCl ₃ , RuCl ₃ , IrCl ₄ , (NH ₄ ) ₂ IrCl ₆ , or the like may be used as the plating solution.

The source electrode 64 may be made of Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni, W, or an alloy thereof.

Referring to FIG. 3D, the plating mask layer pattern 54 ′ may be selectively removed to partially expose sidewalls of the lower electrode conductive layer 66. For example, when the plating mask layer pattern 54 ′ is formed of SiO ₂ , the plating mask layer pattern 54 ′ may be formed using a wet etching method using a HF solution or a buffered oxide etchant (BOE) solution as a wet etchant. Can be removed. The lower electrode seed layer pattern 52 ′ may be removed in the process of removing the plating mask layer pattern 54 ′ or may be removed by performing a separate process. For example, when the seed layer pattern 52 'for the lower electrode is formed of Pt or Ru, since these materials are insoluble to the HF solution or the BOE solution, the lower electrode is removed when the plating mask layer pattern 54' is removed. The dragon seed layer pattern 52 'is not removed and remains as it is.

Referring to FIG. 3E, the sidewall of the lower electrode 70 is completely exposed by removing the lower electrode seed layer pattern 52 ′. In this case, a wet etching method may be used when the lower electrode seed layer pattern 52 'is removed, or a dry etching method may be used, depending on the material film constituting the lower electrode seed layer pattern 52'.

For example, when the seed layer pattern 52 'for the lower electrode is formed of a Ru film, the reactive ion etching method makes it easier to change Ru into a volatile gas compound than other platinum group metals. The electrode seed layer pattern 52 'can be removed.

When the lower electrode seed layer pattern 52 'is formed of a material that is dissolved in an HF solution such as Cu or Ag, the plating mask layer pattern 54' and the lower electrode seed layer pattern 52 'are formed of HF. It can also be removed at once by one wet etching process.

When the plating mask layer pattern 54 ′ and the seed layer pattern 52 ′ for the lower electrode are removed as described above, the capacitor lower electrode 66 separated for each unit cell is formed.

Referring to FIG. 3F, a dielectric material is deposited by a CVD method or a sputtering method on a resultant product on which the capacitor lower electrode 66 is formed to form a dielectric film 68 to a predetermined thickness. The formation thickness of the dielectric film 68 is determined in consideration of the required capacitance of the capacitor. For example, the dielectric film 68 may be formed to a thickness of 20 nm.

The dielectric film 68 may include a Ta ₂ O ₅ film, an SrTiO ₃ (STO) film, a (Ba, Sr) TiO ₃ (BST) film, a PbZrTiO ₃ (PZT) film, an SrBi ₂ Ta ₂ O ₉ (SBT) film, ( Pb, La) (Zr, Ti) O ₃ (PLZT) film, Bi ₄ Ti ₃ O ₁₂ It can be formed of a multi-layer consisting of a film or a combination thereof.

Subsequently, a conductive material is deposited on the dielectric layer 66 by a CVD method or a sputtering method to form a capacitor upper electrode 70. The capacitor upper electrode 70 may be formed of a material film of substantially the same type as that of the lower electrode seed layer (see 52 of FIG. 3A).

Meanwhile, the capacitor upper electrode 70 may be formed by forming a Pt thin film to a predetermined thickness, for example, about 50 nm by using a metal-organic deposition (MOD) method. In this case, the thickness of the Pt thin film formed by the capacitor upper electrode 70 by adjusting the spin recovery and the concentration of the Pt MOD solution (a mixture of 10% Pt-acetylacetonate and 90% ethanol) using the spin coating method. And the density of the film can be adjusted.

When the upper electrode 70 is formed of a Pt film, another method that can be used is a spin coating method of a colloid. When using this method, a Pt colloidal solution in which a solid content consisting of Pt colloids having an average size of about 30 to 50 mm 3 is uniformly dispersed in an organic solvent consisting of alcohol components at a concentration of about 5% by weight is conventionally used. It is coated by a thickness of about 1000 mm 3 by a spin coating method. Then, after performing a heat treatment process at about 300 to 500 ° C. for about 10 minutes to volatilize the alcohol component, the remaining Pt thin film may be formed as the capacitor upper electrode 70.

<2nd Example>

4 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a second embodiment of the present invention.

The second embodiment according to the present invention proceeds substantially the same process steps as the first embodiment except that the upper electrode 70 'is formed by the electroplating method.

In more detail, the capacitor lower electrode 66 is formed on the semiconductor substrate 50 in substantially the same manner as described with reference to FIGS. 3A to 3E. Thereafter, dielectric film 68 is formed using substantially the same method as in FIG. 3F.

Then, the upper electrode seed layer 72 is formed on the dielectric film 68 by a thickness of about 50 to 1000 mW by the CVD method or the sputtering method.

The upper electrode seed layer 72 may be formed of a material film of substantially the same type as the lower electrode seed layer of the first embodiment.

Subsequently, the cathode of the power source 58 is connected to the seed layer 72 for the upper electrode through the first wiring 60 and the anode is connected to the source electrode 64 through the second wiring 62. By using the same method as the electroplating method described with reference to FIG. 3C, the capacitor upper electrode 70 ′ is formed on the upper electrode seed layer 72 to a desired thickness.

When the capacitor upper electrode 70 'is formed by the electroplating method, Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Cu, Mo, Co, Ni, Zn, Cr, Fe, or a combination thereof may be used. A solution in which the metal salt is dissolved can be used as a plating solution. In addition, when the capacitor upper electrode 70 'is formed by an electroplating method, Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Cu, Mo, Co, Ni, Zn, Cr, Fe, or these Alloy may be used as the source electrode 64.

When the capacitor upper electrode 70 'is formed by the electroplating method as described above, the step coverage of the film formed by plating is excellent, so that the capacitor upper electrode 70' formed on the entire surface of the semiconductor substrate 50 is uniform. It can be easily formed in one thickness. In addition, when the thickness of the capacitor upper electrode 70 'formed by the electroplating method is increased, the space between the adjacent capacitor lower electrodes 66 is completely filled to improve the flatness of the capacitor upper electrode.

<Third example>

5A to 5F are cross-sectional views illustrating a third embodiment of a method of manufacturing a capacitor of a semiconductor memory device according to the present invention. The third embodiment according to the present invention is a case where the present invention is applied when the capacitor of the semiconductor memory device has a capacitor over bit line (COB) structure. However, the present invention can also be applied to forming a capacitor of a semiconductor memory device having a CUB (capacitor under bit line) structure.

Referring to FIG. 5A, in the method of manufacturing a capacitor of a semiconductor memory device according to the third embodiment of the present invention, first, an isolation region 74 is formed on a semiconductor substrate 50 to define an active region and an inactive region. The device isolation layer 74 may be formed by a LOCOS (LOCal Oxidation of Silicon) method or a trench device isolation method. Subsequently, a field effect transistor including a gate electrode (not shown), a source region 76, and a drain region (not shown) is formed on the active region. Then, after forming the lower electrode pad 78 on the source region 76, a first interlayer insulating film 80 made of an oxide film on the entire surface of the semiconductor substrate 50 to form an adjacent lower electrode pad 78 ) Is electrically isolated.

Although not specifically illustrated in the drawings, the lower electrode pad 78 may be formed of a single layer composed of only conductive polysilicon, or may be formed of multiple layers of two or more double layers. When the lower electrode pad 78 is formed of multiple layers, the lower electrode pad 78 may be formed in a stacked structure in the following order.

In detail, the lower electrode pad 78 may be formed of multiple layers, but the uppermost layer may be formed of a barrier layer. For example, when the lower electrode pad 78 is formed of a double film, the conductive polysilicon film barrier film may be sequentially stacked. The barrier film may be a TiN film, a TaN film, a WN film, a TiSiN film, a TiAlN film, a TiBN film, a ZrSiN film, a ZrAlN film, a MoSiN film, a MoAlN film, a TaSiN film, or a TaAlN film.

Alternatively, the lower electrode pad 78 may be formed such that an uppermost layer is formed of a platinum group metal film and at least one barrier film is inserted under the platinum group metal film. For example, when the lower electrode pad 78 is formed in a triple layer, the conductive polysilicon film, the barrier film, and the platinum group metal film may be sequentially stacked. The barrier film may be a TiN film, a TaN film, a WN film, a TiSiN film, a TiAlN film, a TiBN film, a ZrSiN film, a ZrAlN film, a MoSiN film, a MoAlN film, a TaSiN film, or a TaAlN film, and the platinum group metal film is a Pt film. , Rh film, Ru film, Ir film, Os film or Pd film.

As described above, the technical effects generated when the lower electrode pad 78 is formed in multiple layers will be described in detail later.

Subsequently, a bit line 82 is formed on the first interlayer insulating film 80, and a second interlayer insulating film 84 made of an oxide film and covering the bit line 82 is formed on the entire surface of the semiconductor substrate 50. do. On the sidewalls and the upper surface of the bit line 82, a spacer S and a capping insulating layer C each including an insulating film having an etching selectivity, for example, a nitride film, may be formed. In this case, when forming the hole in which the lower electrode of the capacitor is to be formed in the subsequent process, the hole can be self-aligned by the bit line 82.

Subsequently, an etch stop film 86 is formed on the second interlayer insulating film 84. The etch stop layer 86 may be formed of a material layer having a high etch selectivity with respect to the material layer forming the second interlayer insulating layer 84. For example, the etch stop layer may be formed of a Si ₃ N ₄ film, a TiO ₂ film, a Ta ₂ O ₅ film, or an Al ₂ O ₃ film.

The etch stop layer 86 is formed to prevent the lower layer of the etch stop layer 86, for example, the second interlayer insulating layer 84, from being etched in a subsequent etching process. If the etchant is not likely to damage the lower layer of the etch stop layer, the step of forming the etch stop layer 86 may be omitted.

A conductive lower electrode seed layer 88 is formed on the etch stop layer 86, and a plating mask layer 90 is formed on the lower electrode seed layer 88.

The type, thickness, and manufacturing method of the material film that may be formed of the lower electrode seed layer 88 and the plating mask layer 90 may be formed of the lower electrode seed layer and the plating mask layer of the first embodiment. It is substantially the same as the type, thickness and manufacturing method of the material film. For example, a portion of the lower electrode seed layer 88 may be removed by a wet etching method or a dry etching method in a subsequent process, and thus may be formed as a material film that is easily removed by a wet etching method or a dry etching method. . Specifically, when a part of the lower electrode seed layer 88 is removed by a wet etching method in a subsequent process, the lower electrode seed layer 88 may be formed of a Cu film or an Ag film. In the subsequent process, when the part of the lower electrode seed layer 88 is removed by using a dry etching method, the lower electrode seed layer 88 may be formed of a Ru film. The plating mask layer 90 may be formed of a SiO ₂ film. As described above, the process advantages caused when the lower electrode seed layer 88 and the plating mask layer 90 are formed are described in detail in the first embodiment.

Referring to FIG. 5B, the photoresist pattern 92 is formed on the plating mask layer 90 by performing a photo process to define the width of the hole H2 in which the capacitor lower electrode is to be formed. Then, the plating mask layer 90, the lower electrode seed layer 88, and the etch stop layer 86 are selectively removed by using a reactive ion etching method using the photoresist pattern 92 as an etching mask. The pattern 90a, the seed layer pattern 88a for the lower electrode, and the etch stop layer pattern 86a are formed. Thereafter, the second interlayer insulating film 84 exposed by the etch stop film pattern 86a and the first interlayer insulating film 80 thereunder are exposed by using a reactive ion etching method using the photoresist pattern 92 as an etching mask. By sequentially etching to form a hole (H2) when the lower electrode pad 78 is exposed. When the hole H2 exposing the lower electrode pad 78 is formed, the sidewall of the seed layer pattern 88a for lower electrode is exposed.

On the other hand, when the spacer S and the capping insulating layer C having an etch selectivity and the second interlayer insulating layer 84 and the etching selectivity are formed on the sidewalls and the upper surface of the bit line 82, the hole H2 is formed. The self-aligning technique can be applied at. In other words, since the spacer S and the capping insulating layer C may be used as the etch stop layer when the hole H2 is formed using the reactive ion etching method, the upper surface of the lower electrode pad 78 may be exposed. The hole H2 is self-aligned by the bit line 82. As such, when the self-aligning technique may be applied in the process of forming the hole H2, the alignment margin may be increased in the photographing process of forming the photoresist pattern 92.

Referring to FIG. 5C, the photosensitive film pattern 92 formed on the plating mask layer pattern 90a is removed. Then, a barrier material (not shown) is formed on the inside of the hole H2 and on the plating mask layer pattern 90a. Then, the deposited barrier material is planarized to expose the upper surface of the plating mask layer pattern 90a, and then a barrier formed in the hole H2 until the sidewall of the seed layer pattern 88a for lower electrode is exposed. The material is selectively removed using a reactive ion etching method to form the barrier film 94.

For example, TiN is deposited as the barrier material on the inside of the hole H2 and on the plating mask layer pattern 90a by a CVD method or an atomic layer deposition method having good step coverage characteristics. Then, the TiN deposited using the CMP (Chemical Mechanical Polishing) method is removed to expose the upper surface of the plating mask layer pattern 90a, and the TiN deposited in the hole H2 is selectively selected by the reactive ion etching method. It removes and exposes the side wall of the seed layer pattern 88a for lower electrodes. Then, the barrier layer 94 that is electrically connected to the lower electrode pad 78 and fills the lower portion of the hole H2 is formed. The barrier layer 94 may stably secure a contact resistance by preventing a material constituting the capacitor lower electrode formed on the barrier layer 94 from being diffused into the lower electrode pad 78 in a subsequent process. In addition, the barrier layer 94 serves as an adhesive layer between the capacitor lower electrode and the lower electrode pad 78.

The barrier film 94 may not be formed only of the TiN film. The barrier layer 94 may be formed of a multilayer formed of a metal silicide layer, a metal nitride layer, a doped polysilicon layer, or a combination thereof. Here, the metal silicide film may be a WSi _x film, a TiSi _x film, a CoSi _x film, a MoSi _x film or a TaSi _x film, and the metal nitride film may be a TiN film, a TaN film, a WN film, a TiSiN film, a TiAlN film, or a TiBN film. , ZrSiN film, ZrAlN film, MoSiN film, MoAlN film, TaSiN film or TaAlN film.

Referring to FIG. 5D, the electroplating process is performed substantially the same as in the first embodiment to form the lower electrode conductive film 96 on the barrier film 94. In other words, while the semiconductor substrate 50 is immersed in the plating solution in which the metal salt is dissolved, the cathode of the power source 58 is connected to the lower electrode seed layer pattern 88a through the first wiring 60 and the power source 58 The anode of is connected to the source electrode 64 through the second wiring 62. Then, the lower electrode conductive film 96 begins to precipitate on the sidewall of the lower electrode seed layer pattern 88a so that the inside of the hole H2 is filled with the lower electrode conductive film 96. At this time, the type of solution that can be used as the plating liquid, the type of material film that can be used as the source electrode, and the process conditions of the electroplating process are substantially the same as in the first embodiment.

On the other hand, the lower electrode pad 78 can be formed not only by a single film made of conductive polysilicon, but may also be formed by multiple films, as described above. In particular, when the lower electrode pad 78 is formed of a double layer in which conductive polysilicon film barrier films are sequentially stacked, or the conductive polysilicon film in barrier film-platinum group metal film is sequentially formed, the triple electrode film is formed. The electroplating process may be performed without the barrier film 94 formed at the bottom of the hole H2 to fill the entire hole H2 with only the conductive film 96 for the lower electrode. In other words, since the lower electrode pad 78 is formed of a multilayer including at least one barrier film, it is not necessary to form a separate barrier film 94 at the bottom of the hole H2. Accordingly, the process step of forming the barrier layer 94 on the bottom of the hole H2 can be omitted.

Referring to FIG. 5E, the plating mask layer pattern 90a and the lower electrode seed layer pattern 88a are removed using a method substantially the same as that of the first embodiment. For example, when the plating mask layer pattern 90a is formed of SiO ₂ , and the lower electrode seed layer pattern 88a is formed of Cu or Ag, a wet etching process using an HF solution as a wet etchant. The plating mask layer pattern 90a and the lower electrode seed layer pattern 88a may be simultaneously removed. In addition, when the plating mask layer pattern 90a is formed of SiO ₂ and the lower electrode seed layer pattern 88a is formed of Ru, the plating mask layer pattern 90a is formed by etching an HF solution or a BOE solution. The wet layer may be removed by a wet etching process, and the seed layer pattern 88a for the lower electrode may be removed using a reactive ion etching method. In this case, since the etch stop layer pattern 86a is formed directly under the seed layer pattern 88a for the lower electrode, the plating mask layer pattern 90a and / or may be subjected to a wet etching process and / or a dry etching process. Alternatively, the second interlayer insulating film 84 may be prevented from being etched in the process of removing the lower electrode seed layer pattern 88a. In particular, when the etch stop film pattern 86a is formed of a TiO ₂ film, the etching of the material film formed under the etch stop film pattern 86a, for example, the second interlayer insulating film 84, is more effectively prevented.

As described above, the plating mask layer pattern 90a and the lower electrode seed layer pattern 88a are removed to expose sidewalls of the conductive layer 96 for the lower electrode, thereby forming the capacitor lower electrode 96.

Referring to FIG. 5F, the dielectric film 98 is formed on the capacitor lower electrode 96, and the capacitor upper electrode 100 is formed on the dielectric film. The type, thickness, and manufacturing method of the material film constituting the dielectric film 98 and the capacitor upper electrode 100 are substantially the same as in the first embodiment. For example, the capacitor upper electrode 100 may be formed by a CVD method, a sputtering method, or a MOD method as shown in FIG. 3F, and an electroplating method using the seed layer 72 for the upper electrode as shown in FIG. 4. It can also form using.

According to the third embodiment of the present invention, the hole H2 may be formed to be self-aligned by the bit line 82. In this case, it is possible to prevent the misalignment between the barrier layer 94 and the capacitor lower electrode 96.

In addition, when the capacitor lower electrode 96 is formed using an electroplating method, voids are formed in the hole H2 because the lower electrode conductive film 96 is deposited on the sidewall of the seed layer pattern 88a for the lower electrode. Can be prevented. In addition, since the lower electrode seed layer pattern 88a can be completely removed after the capacitor lower electrode 96 is formed, deterioration of device characteristics of the semiconductor memory device due to the lower electrode seed layer pattern 88a can be prevented. Can be.

<Fourth Example>

The fourth embodiment according to the present invention described with reference to FIGS. 6A to 6D forms the lower electrode pad P as a multilayer including at least one barrier film 104 and performs an electroplating process. Before proceeding substantially the same as the case of the third embodiment, except that the liner seed layer (L) electrically connected to the side wall of the lower electrode seed layer pattern (86a) is further formed.

Referring to FIG. 6A, a lower electrode pad P formed of multiple layers is formed on an impurity implantation region, for example, a source region 76, on the semiconductor substrate 50. The lower electrode pad P may be formed to include a barrier film made of at least metal nitride. This is because the fourth embodiment according to the present invention is formed so as to omit the step of forming the barrier film (see 94 in FIG. 5F) in the third embodiment by forming the lower electrode pad P to include the barrier film. to be. For example, the lower electrode pad P may have a double layer structure in which the conductive polysilicon layer 102 and the barrier layer 104 are sequentially stacked as shown in FIG. 6A. The barrier film 104 may be formed of a material film of substantially the same type as the barrier film 94 illustrated in FIG. 5F. For example, the barrier film 104 may be formed of a TiN film.

As described above, the lower electrode pad P is formed to include at least one layer of the barrier film 104, and then the process steps substantially the same as those of the third embodiment are performed to form the upper surface of the lower electrode pad P. The hole H3 exposing the hole is formed. Then, the liner seed layer L is electrically connected to the sidewall of the seed layer pattern 88a for the lower electrode exposed on the sidewall of the hole H3.

The liner seed layer L may be formed of a material substantially the same as a material capable of forming the seed layer pattern 88a for the lower electrode. However, it is preferable to form the same material as the lower electrode conductive film (see 106 of FIG. 6C) which is embedded in the hole H3 by a subsequent electroplating process. In addition, the liner seed layer L may be formed of a material different from that of the lower electrode seed layer pattern 88a. For example, in the subsequent step, when the lower electrode conductive film (see 106 in FIG. 6C) embedded in the hole H3 is a Pt film, the liner seed layer L is preferably formed of a Pt film. As such, when the lower electrode conductive layer (see 106 of FIG. 6C) and the liner seed layer L formed in the hole H3 are formed of the same material in a subsequent process, the insulating property of the capacitor dielectric layer is enhanced in a subsequent process. In order to oxidize the liner seed layer L during the heat treatment process under an oxygen atmosphere, physical stress is induced at the interface between the lower electrode conductive layer (see 106 of FIG. 6C) and the liner seed layer L. It can be alleviated more. Of course, when the liner seed layer L is formed of a material different from that of the lower electrode conductive film (see 106 of FIG. 6C) formed in the hole H3 in the subsequent step, the lower electrode conductive film (FIG. 6c) 106) and the liner seed layer (L) does not cause a physical stress. For example, when the lower electrode conductive layer (see 106 of FIG. 6C) and the liner seed layer L formed in the hole H3 are formed of different materials in a subsequent process, The liner seed layer L may be formed of a material film that does not cause physical stress at an interface between the conductive film (see 106 of FIG. 6C) and the liner seed layer L. The selection of the material film in the formation of the liner seed layer L can be easily made by one of ordinary skill in the art to recognize the fourth embodiment according to the present invention.

Hereinafter, a method of forming the liner seed layer will be described in more detail with reference to FIG. 6B.

Referring to FIG. 6B, one method for forming the liner seed layer L may be performed by performing an electroplating process using the seed layer pattern 88a for the lower electrode to expose the lower electrode to the sidewall of the hole H3. A hemispherical seed 106 is formed on the seed layer pattern 88a. Here, the electroplating process for forming the hemispherical seed 106 may be performed substantially the same as the electroplating process of the third embodiment. In other words, the cathode of the power source 58 is connected to the seed layer pattern 88a for the lower electrode through the first wiring 60, and the anode of the power source 58 is connected to the source through the second wiring 62. After connecting to the electrode 64, the electroplating process may be performed while the semiconductor substrate 50 is immersed in the plating liquid.

When the hemispherical seed 106 is formed of Pt, the type of plating liquid, the type of the source electrode 64, and the plating conditions used in the electroplating process are substantially the same as in the third embodiment. However, the hemispherical seed 106 is more preferably formed of a material which is chemically very stable and has no volatility.

In forming the hemispherical seed 106, it is preferable that the radius of the hemispherical seed 106 is formed to be less than 1/2 of the width of the hole H3. In other words, when the hemispherical seed 106 is formed, the hole H3 is preferably formed so as not to be closed by the hemispherical seed 106 near the lower electrode seed layer pattern 88a. In this manner, in the formation of the hemispherical seed 106, the reason why the radius of the hemispherical seed 106 is less than 1/2 of the width of the hole H3 will be described below.

After the hemispherical seed 106 is formed as described above, the hemispherical seed 106 is physically etched using a low temperature reactive ion etching method capable of selectively etching the hemispherical seed 106, for example, a low temperature argon etching method. In this case, it is preferable that the temperature of the reaction chamber where the low temperature reactive ion etching process is performed is 0 to 50 ° C.

When the hemispherical seed 106 is etched using the low temperature reactive ion etching method as described above, the material constituting the hemispherical seed 106 is selectively etched and redeposited at the bottom of the hole H3 as shown in FIG. 6A. Liner seed layer L is formed. In particular, when the hemispherical seed 106 is formed of a chemically stable platinum group metal such as Pt, the above redeposition phenomenon is prominent. This is because the platinum group metal is chemically stable and is not easily converted to a volatile gaseous compound even when a low temperature reactive ion etching method such as a low temperature argon etching method is performed.

On the other hand, in forming the hemispherical seed 106, it has already been described that the radius of the hemispherical seed 106 is preferably less than 1/2 of the width of the hole H3. This involves the reactive ion etching of the hemispherical seed 106 to form a liner seed layer L. In other words, in forming the hemispherical seed 106, when the radius of the hemispherical seed 106 is formed to be 1/2 or more, the liner seed layer L is formed on the sidewall of the bottom of the hole H3 in the reactive ion etching step. It is not formed and is formed on the upper sidewall of the hole H3. As such, when the liner seed layer L is formed on the upper portion of the hole H3, the possibility of causing voids in the hole H3 is increased in a subsequent electroplating process.

Although not specifically illustrated in the drawings, a spacer manufacturing method may be used to form the liner seed layer L as illustrated in FIG. 6A. That is, first, the conductive film is formed on the sidewalls, the bottom surface of the hole H3, and the plating mask layer pattern 90a, and then the conductive film is selectively etched by reactive ion etching to form the liner seed layer L in the form of a spacer. Can be. Here, the conductive film may be formed of a material film substantially the same as that of the lower electrode seed layer pattern 88a of the third embodiment, and in particular, the lower electrode conductive film formed in the hole H3 in a subsequent process (FIG. Preferably from the same material). The reason for this is described in detail with reference to the formation step of the hemispherical seed 106.

When forming the spacer-type liner seed layer L made of the Pt film, a Pt film is deposited on the inside of the hole H3 and on the upper surface of the plating mask layer pattern 90a.

The conductive film for forming the liner seed layer L may be formed using a chemical vapor deposition method, an atomic layer deposition method, a sputtering method or a laser deposition method. The selection of a specific method for forming the conductive film depends on the type of material film to be formed as the conductive film. For example, when forming a conductive film from a Pt film, it is preferable to form using a sputtering method. In addition, conventional sputtering equipment may be used to form the conductive film using a sputtering method. However, when the aspect ratio of the hole H3 is larger than a threshold, it is preferable to use a Long Through Sputtering (LTS) equipment. The formation thickness of the conductive film is determined in consideration of the width of the hole H3 and the thickness of the liner seed layer L to be formed by the spacer manufacturing method. For example, the conductive film may be deposited to about 100 nm. According to the experiments of the present inventors, when the conductive film is formed into a Pt film by using the LTS device, the DC power of the LTS device can be about 10 kW, the Ar flow rate can be about 5 sccm, and the temperature of the semiconductor substrate is It can be made into about 300 degreeC.

Subsequently, when the conductive film deposited on the entire surface of the semiconductor substrate 50 is anisotropically etched by using a reactive ion etching method such as a low temperature argon etching method, a liner seed layer L having a spacer shape may be formed.

Referring to FIG. 6C, an electroplating process using the seed layer pattern 88a for the lower electrode and the liner seed layer L is performed. Here, the electroplating process is substantially the same as the electroplating process performed to form the conductive film for the lower electrode (see 96 in FIG. 5D) in the third embodiment. In other words, the cathode of the power source 58 is connected to the seed layer pattern 88a for the lower electrode through the first wiring 60, and the anode of the power source 58 is connected to the source through the second wiring 62. After connecting to the electrode 64, the electroplating process is performed while the semiconductor substrate 50 is immersed in a plating solution. Then, the lower electrode conductive layer 106 begins to precipitate on the liner seed layer L, and consequently, the lower electrode conductive layer is formed in the hole H3 to a height corresponding to the size of the capacitor lower electrode to be formed. Membrane 106 is gradually filled (see dashed line).

Referring to FIG. 6D, the removing of the plating mask layer pattern 90a and the seed layer pattern 88a for the lower electrode is performed in substantially the same manner as in the third embodiment to form the capacitor lower electrode 106. In particular, when the lower electrode conductive layer 106 and the liner seed layer L are made of the same material, for example, Pt, the liner seed may be removed in the step of removing the plating mask layer pattern 90a and the lower electrode seed layer pattern 88a. The layer L can be prevented from being etched. For example, when the lower electrode seed layer pattern 88a is made of Ag or Cu, and the lower electrode conductive film 106 and the liner seed layer L are made of Pt, a wet type using an HF solution as an etchant Even when the plating mask layer pattern 90a and the lower electrode seed layer pattern 88a are removed using an etching method, the lower electrode conductive layer 106 and the liner seed layer L are not etched.

Subsequently, if the capacitor dielectric film 108 forming step and the capacitor upper electrode 110 forming step are proceeded substantially in the same manner as in the third embodiment, the capacitor of the semiconductor memory device is completed. In particular, when the liner seed layer L is formed of the same material as the lower electrode conductive film 106, the lower electrode conductive film 106 and the liner seed in the process of high temperature heat treatment of the capacitor dielectric film 108 in an oxygen atmosphere. It is possible to prevent the formation of oxides at the interface between the layers (L). Accordingly, physical stress is induced at the interface between the capacitor lower electrode 106 and the capacitor dielectric layer 108 to prevent an increase in the leakage current of the capacitor.

Although not specifically illustrated in the drawings, the capacitor upper electrode 110 may be formed by performing an electroplating process as in the second embodiment.

According to the fourth embodiment of the present invention, the lower electrode pad P is formed of multiple layers to include the barrier layer. For example, the lower electrode pad P is formed of a double film in which the conductive polysilicon film 102 and the TiN film 104 are sequentially stacked. As a result, it is not necessary to form the barrier film (see 94 in Fig. 5C) as in the third embodiment. Therefore, the fourth embodiment according to the present invention has an advantage of reducing the number of process steps in the capacitor manufacturing process as compared with the third embodiment.

<Fifth Embodiment>

In the fifth embodiment according to the present invention described with reference to FIGS. 7A and 7B, as in the fourth embodiment, the lower electrode pad P is formed of multiple layers to include at least one barrier film. However, in the fifth embodiment, the uppermost layer of the lower electrode pad P is formed of the same kind of material film as the material film of which the liner seed layer L is to be formed. In addition, in the fifth embodiment, when the liner seed layer L is formed, the bottom surface of the liner seed layer L is formed to be recessed from the upper surface of the lower electrode pad P. FIG.

Referring to FIG. 7A, first, a lower electrode pad P formed of multiple layers is formed on an impurity implantation region, for example, a source region 76, formed in the semiconductor substrate 50. The lower electrode pad P includes at least one barrier film, and the uppermost layer is formed of a material film of the same kind as the material film of the liner seed layer L. As in the case of the fourth embodiment, the liner seed layer L is preferably formed of a material film of substantially the same type as the lower electrode conductive film formed in the hole H4.

As illustrated in FIG. 7A, the lower electrode pad P may have a triple layer structure in which the conductive polysilicon 112, the barrier layer 114, and the platinum group metal layer 116 are sequentially stacked. The barrier film 114 may be formed of a material film substantially the same as the barrier film (see 94 of FIG. 5C) of the third embodiment of the present invention. For example, the barrier layer 114 may be formed of a TiN layer, and the platinum group metal layer 116 may be formed of a Pt layer.

Subsequently, the same process steps as those of the third embodiment are performed to form holes H4 exposing the upper surface of the lower electrode pad P. The sidewalls of the lower electrode seed layer pattern 88a are exposed by the formation of the hole H4.

Subsequently, the forming of the liner seed layer L electrically connected to the seed layer pattern 88a for the lower electrode is performed. Specifically, the platinum group metal film 116, which is the uppermost layer of the lower electrode pad P, is etched by using a reactive ion etching method. Then, the material constituting the platinum group metal film 116 is etched and re-bonded to the inside of the hole H4 so that the liner seed layer L is electrically connected to the sidewall of the seed layer pattern 88a for the lower electrode. Is formed. In this case, as the reactive ion etching method for etching the platinum group metal film 116, it is preferable to use a low-temperature argon etching method, and the temperature of the reaction chamber where the low-temperature reactive ion etching process is performed is preferably 0 to 50 ° C. Do.

Since the liner seed layer L is formed by reactive ion etching the platinum group metal film 116, which is the uppermost layer of the lower electrode pad P, the bottom surface of the liner seed layer L is formed on the upper surface of the lower electrode pad P. It is formed in a recessed form from.

Referring to FIG. 7B, an electroplating process using the seed layer pattern 88a for the lower electrode and the liner seed layer L is performed to fill the inside of the hole with the conductive layer 118 for the lower electrode. The electroplating process is performed substantially the same as the electroplating process performed in the third embodiment. When the electroplating process is performed, a metal material begins to precipitate on the liner seed layer L, so that the lower electrode conductive film 118 is formed inside the hole H4 to a height substantially equal to the dimension of the capacitor lower electrode to be formed. Will be filled in. At this time, the material film that can be used as the source electrode, the solution that can be used as the plating solution, and the plating conditions are substantially the same as in the third embodiment.

By filling the inside of the hole H4 with the lower electrode conductive layer 118 by performing the electroplating process as described above, the step of removing the plating mask layer pattern 90a and the seed layer pattern 88a for the lower electrode, the capacitor When the forming of the dielectric film 120 and the forming of the capacitor upper electrode 122 are performed in substantially the same manner as in the third embodiment, the capacitor of the semiconductor memory device according to the present invention is formed.

Although not specifically illustrated in the drawings, the capacitor upper electrode 122 may be formed by performing an electroplating process as in the case of the second embodiment.

When the capacitor lower electrode is formed by applying the capacitor manufacturing method according to the present invention, the problem of the prior art generated when the lower electrode is separated for each unit cell by a dry etching method is solved. In addition, according to another aspect of the present invention, since the self-aligning technique using the masked bit line may be applied when forming the hole exposing the lower electrode pad, the hole may be formed by only one photo process. Further, according to another aspect of the present invention, after forming the lower electrode by the electroplating method, it is possible to completely remove the seed layer pattern for the lower electrode by a simple method. Accordingly, the electrical characteristics of the capacitor can be prevented from being degraded by the seed layer for the lower electrode remaining after the electroplating process. In addition, according to another aspect of the present invention, the lower electrode and the lower electrode seed layer need not necessarily be formed of the same material, and may be freely selected as necessary.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited thereto, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

Claims (37)

(a) forming a seed layer for the lower electrode on the semiconductor substrate having a conductive region electrically connected to the active region on the semiconductor substrate; (b) forming a plating mask layer on the seed layer; (c) patterning the seed layer and the plating mask layer to form a seed layer pattern and a plating mask layer pattern defining a region where a capacitor lower electrode is to be formed, thereby exposing sidewalls of the conductive region and the plating mask layer pattern; Forming a hole; (d) forming a lower electrode conductive film in the hole by performing an electroplating process using the seed layer pattern having sidewalls exposed by the hole; And (e) forming a capacitor lower electrode by removing the plating mask layer pattern and the seed layer pattern for the lower electrode such that sidewalls of the conductive film are exposed. The method of claim 1, The seed layer is formed of a multilayer film made of a platinum group metal film, a platinum group metal oxide film, a conductive material film having a perovskite structure, a conductive metal film, a metal silicide film, a metal nitride film, or a combination thereof. A method for manufacturing a capacitor of a semiconductor memory device. The method of claim 1, The seed layer is a Pt film, Rh film, a Ru film, Ir film, Os film, a Pd film, the PtO _x layer, RhO _x film, a RuO _x film, the IrO _x film, OsO _x film, PdO _x film, CaRuO ₃ film, SrRuO ₃ film, BaRuO ₃ film, BaSrRuO ₃ film, CaIrO ₃ film, SrIrO ₃ film, BaIrO ₃ film, (La, Sr) CoO ₃ film, Cu film, Al film, Ta film, Mo film, W film, Au film , Ag film, WSi _x film, TiSi _x film, CoSi _x film, MoSi _x film, TaSi _x film, TiN film, TaN film, WN film, TiSiN film, TiAlN film, TiBN film, ZrSiN film, ZrAlN film, MoSiN film And a multi-layer consisting of a MoAlN film, a TaSiN film, a TaAlN film, or a combination thereof. The method of claim 1, The plating mask layer may include a boro-phospho-silicate glass (BPSG) film, a spin-on glass (SOG) film, a phosphor-silicate glass (PSG) film, a photoresist film, a diamond like carbon (DLC) film, a SiO _x film, A method for manufacturing a capacitor of a semiconductor memory device, characterized in that it is formed of a multilayer of SiN _x film, SiON _x film, TiO _x film, AlO _x film, AlN _x film, or a combination thereof. The method of claim 1, wherein step (d) As a plating solution, a plating solution in which a metal salt containing Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni or a combination thereof is dissolved is used, As the anode, an alloy made of Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni or a combination thereof is used. A capacitor manufacturing method for a semiconductor memory device, characterized in that the seed layer pattern is used as a cathode. The method of claim 1, The plating mask layer pattern and the seed layer pattern is a capacitor manufacturing method of a semiconductor memory device, characterized in that each removed by a wet or dry etching method. The method of claim 1, The plating mask layer pattern and the seed layer pattern for the lower electrode is a capacitor manufacturing method of a semiconductor memory device, characterized in that the removal by performing one wet or dry etching process. The method of claim 1, Forming a dielectric film on the capacitor lower electrode; And Capacitor manufacturing method of a semiconductor memory device, characterized in that it further comprises forming a capacitor upper electrode on the dielectric film. The method of claim 8, The dielectric film is a Ta ₂ O ₅ film, a SrTiO ₃ film, a (Ba, Sr) TiO ₃ film, a PbZrTiO ₃ film, a SrBi ₂ Ta ₂ O ₉ film, a (Pb, La) (Zr, Ti) O ₃ film, Bi ₄ A method of manufacturing a capacitor for a semiconductor memory device, characterized in that it is formed of a multilayer comprising a Ti ₃ O ₁₂ film or a combination thereof. The method of claim 8, The capacitor upper electrode is a capacitor manufacturing method of a semiconductor memory device, characterized in that formed by a CVD method, a sputtering method, a metal-organic deposition (MOD) method or a spin coating method of Pt colloid (colloid). The method of claim 8, Forming a seed layer for an upper electrode on the dielectric layer; The capacitor upper electrode is a capacitor manufacturing method of the semiconductor memory device, characterized in that formed by the electroplating method using the seed layer for the upper electrode. The method of claim 11, The upper electrode seed layer is a capacitor of a semiconductor memory device, characterized in that formed of a multilayer group consisting of a platinum group metal film, a platinum group metal oxide film, a conductive material film having a perovskite structure, a conductive metal film, or a combination thereof. Manufacturing method. The method of claim 11, The capacitor upper electrode forming step, As a plating solution, a plating solution in which metal salts containing Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Cu, Mo, Co, Ni, Zn, Cr, Fe, or a combination thereof is dissolved is used, Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Cu, Mo, Co, Ni, Zn, Cr, Fe or alloys thereof as the anode, A capacitor manufacturing method of a semiconductor memory device, characterized in that the seed layer for the upper electrode is used as a cathode. The method of claim 1, Forming an etch stop layer on the semiconductor substrate, The lower electrode seed layer is formed on the etch stop layer, The hole is formed by patterning the plating mask layer, the lower electrode seed layer and the etch stop layer. The method of claim 14, The etch stop layer is formed of a Si ₃ N ₄ film, Ta ₂ O ₅ film, TiO ₂ film, Al ₂ O ₃ film or a combination of them, a capacitor manufacturing method of a semiconductor memory device, characterized in that formed. (a) forming a lower electrode pad made of a conductive material on the active region of the semiconductor substrate; (b) forming a first interlayer insulating film on the lower electrode pads; (c) forming a bit line on the first interlayer insulating film; (d) forming a second interlayer insulating film on the bit line; (e) forming a seed layer for a lower electrode on the second interlayer insulating film; (f) forming a plating mask layer on the seed layer for the lower electrode; (g) forming a hole for exposing the lower electrode pad by patterning the plating mask layer, the lower electrode seed layer, the second interlayer insulating layer, and the first interlayer insulating layer by a photolithography process; (h) The inside of the hole is filled with a conductive film, and the conductive film formed on at least substantially the same level as the upper surface of the lower electrode seed layer is formed by performing an electroplating process using the patterned lower electrode seed layer. Doing; (i) forming a capacitor lower electrode by removing the patterned plating mask layer and the lower electrode seed layer to expose sidewalls of the conductive layer. The method of claim 16, The lower electrode seed layer may be formed of a multilayer film including a platinum group metal film, a platinum group metal oxide film, a conductive material film having a perovskite structure, a conductive metal film, a metal silicide film, a metal nitride film, or a combination thereof. A method for manufacturing a capacitor of a semiconductor memory device. The method of claim 16, wherein step (h) Forming a conductive barrier layer on the lower electrode pad exposed at the bottom of the hole, but not covering the sidewall of the lower electrode seed layer exposed by the hole; And And forming a conductive layer for the lower electrode on the barrier layer by performing an electroplating process using the patterned lower electrode seed layer. The method of claim 18, wherein the forming of the barrier film, Forming a barrier material in the hole and on the plating mask layer; And Removing an upper portion of the barrier layer to expose an upper surface of the patterned plating mask layer; And Selectively removing the barrier material in the hole to expose sidewalls of the seed layer for the patterned lower electrode. The method of claim 19, The barrier film is a capacitor manufacturing method of a semiconductor memory device, characterized in that formed of a multilayer film made of a metal silicide film, a metal nitride film, a doped polysilicon film or a combination thereof. The method of claim 16, wherein the electroplating process As a plating solution, a plating solution in which a metal salt containing Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni or a combination thereof is dissolved is used, Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni or an alloy thereof is used as the source electrode, A method for manufacturing a capacitor of a semiconductor memory device, characterized in that the patterned lower electrode seed layer is used as a cathode. The method of claim 16, wherein step (i) And removing the patterned plating mask layer and the lower electrode seed layer by performing a wet or dry etching process. The method of claim 16, wherein step (i) And removing the patterned plating mask layer and the lower electrode seed layer by performing one wet or dry etching process. The method of claim 16, Forming an etch stop layer on the second interlayer insulating layer before forming the seed layer for the lower electrode; The lower electrode seed layer is formed on the etch stop layer, And in the hole forming step, the etch stop layer is also patterned. The method of claim 24, The etch stop layer may be formed of a Si ₃ N ₄ film, a Ta ₂ O ₅ film _{, a} TiO ₂ film, or an Al ₂ O ₃ film. The method of claim 16, wherein before proceeding to step (d) Forming a spacer and a capping insulating layer on the sidewalls and the upper surface of the bit line, respectively, using a material layer having an etching selectivity with the second interlayer insulating layer; Wherein (g) is a method of manufacturing a capacitor of a semiconductor memory device, characterized in that for forming a self-aligned hole by the bit line masked by the spacer and the capping insulating film. The method of claim 16, wherein before proceeding to step (h) And forming a liner seed layer on the bottom of the hole, the liner seed layer being electrically connected to the lower electrode seed layer sidewall exposed by the hole. 28. The method of claim 27, wherein forming the liner seed layer Forming a hemispherical seed on sidewalls of the patterned lower electrode seed layer; And And reactively etching the hemispherical seed at a low temperature to redeposit the material constituting the hemispherical seed at the bottom of the hole. The method of claim 28, And the radius of the hemispherical seed is less than one half of the hole width. The method of claim 28, And said hemispherical seed is formed of the same kind of material film as said lower electrode conductive film. 28. The method of claim 27, wherein forming the liner seed layer Lining an entire surface of the semiconductor substrate on which the hole is formed with a conductive film; And And reactive ion etching the conductive film at a low temperature to form the liner seed layer in the form of a spacer. The method of claim 31, wherein The conductive film is a capacitor manufacturing method of a semiconductor memory device, characterized in that formed of the same kind of material film as the lower electrode conductive film. The method of claim 27, The method of manufacturing a capacitor of a semiconductor memory device, characterized in that the lower electrode pad is formed of multiple layers. The method of claim 33, wherein And forming a lower electrode pad so that an uppermost layer of the lower electrode pad is formed of a conductive barrier layer. The method of claim 34, wherein The lower electrode pad has a double layer structure in which a conductive polysilicon film and a metal nitride film are sequentially stacked. The method of claim 33, wherein An uppermost layer of the lower electrode pad is a platinum group metal film, and the lower electrode pad is formed to include at least one conductive barrier film under the lower electrode pad. And the liner seed layer is formed by reactive ion etching a platinum group metal film, which is an uppermost layer of the lower electrode pad, at a low temperature. The method of claim 36, And the platinum group metal layer, which is the uppermost layer of the lower electrode pad, is formed of the same material as that of the lower electrode conductive film.