KR20010039116A - Tape for forming out terminal - Google Patents
Tape for forming out terminal Download PDFInfo
- Publication number
- KR20010039116A KR20010039116A KR1019990047365A KR19990047365A KR20010039116A KR 20010039116 A KR20010039116 A KR 20010039116A KR 1019990047365 A KR1019990047365 A KR 1019990047365A KR 19990047365 A KR19990047365 A KR 19990047365A KR 20010039116 A KR20010039116 A KR 20010039116A
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- South Korea
- Prior art keywords
- wafer
- tape
- chip
- external terminal
- forming
- Prior art date
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- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- 239000007769 metal material Substances 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명에서는 웨이퍼상의 칩들에 금속제의 외부 단자를 형성하는 공정을 단순화하는 외부 단자 형성용 테이프가 개시된다.In the present invention, an external terminal forming tape is disclosed that simplifies the process of forming a metal external terminal on chips on a wafer.
반도체를 적용하는 각종 휴대용 기기들의 보급에 따른 반도체의 경박단소화에 대한 니즈에 대응하기 위하여, 반도체산업의 동향은 반도체의 크기가 칩 크기와 동일한 CSP(Chip size package)로 신속하게 전환되고 있으며 제조비용 절감, 초박형 CSP의 개발에 관심이 집중되고 있다.In order to respond to the needs of thin and short semiconductors due to the spread of various portable devices that apply semiconductors, the trend of the semiconductor industry is rapidly shifting to chip size packages (CSPs) where the size of the semiconductor is the same as the chip size. Attention has been focused on the development of cost-saving, ultra-thin CSPs.
일반적인 반도체는 칩을 리드프레임상에 설치하고 칩의 금속 패드와 리드프레임의 리드 사이를 와이어로 연결하고 리드프레임을 통하여 외부와 전기적으로 연결하는 것이지만, 리드프레임의 외부 돌출물로 인하여 반도체의 부피가 대폭 증가된다는 문제점이 있다In general, the semiconductor is installed on the lead frame, the wire is connected between the metal pad of the chip and the lead of the lead frame and electrically connected to the outside through the lead frame. There is a problem of increasing
이와 달리, CSP는 리드프레임을 적용하지 않고 웨이퍼상의 칩의 표면에 직접 금속제의 외부 단자를 형성하고, 상기 외부 단자와 칩의 금속 패드를 와이어로 연결하며 외부 단자를 통하여 외부와 전기적으로 연결한다. CSP는 리드 등의 외부 돌출물이 없으므로 반도체의 부피가 일반적인 반도체에 비하여 대폭 감소된다.In contrast, the CSP forms a metal external terminal directly on the surface of the chip on the wafer without applying a lead frame, connects the external terminal and the metal pad of the chip with a wire, and electrically connects to the outside through the external terminal. Since the CSP has no external protrusions such as leads, the volume of the semiconductor is greatly reduced compared to the general semiconductor.
CSP에서 칩의 표면에 외부 단자를 형성하는 단자 형성 공정은, 칩이 형성된 웨이퍼를 블레이드를 사용하여 개별 칩 단위로 절삭하고, 각각의 칩별로 일일이 단자 형성용 테이프를 접합하여 외부 단자를 형성한다.In the terminal forming process of forming an external terminal on the surface of a chip in the CSP, the wafer on which the chip is formed is cut in individual chip units using a blade, and the external terminal is formed by bonding the terminal forming tape to each chip.
종래의 금속 단자 형성용 테이프를 도 1을 참조하여 상세하게 설명하면, 칩의 금속 패드를 노출시키기 위하여 접합되는 각각의 칩보다 약간 작은 크기로서, 구조는 베이스 필름(3)의 일측 표면에 칩의 금속 패드와 와이어로 연결되며 외부와 전기적으로 연결하기 위한 금속제의 단자 패턴(1)이 형성되고 타측 표면에 칩과의 접합하기 위한 접착제층이 형성되는 것이다.The conventional metal terminal forming tape will be described in detail with reference to Fig. 1, which is slightly smaller in size than each chip bonded to expose the metal pad of the chip, the structure of the chip being formed on one surface of the base film 3; The metal terminal pattern 1 is connected to the metal pads and wires and electrically connected to the outside, and an adhesive layer for bonding the chip to the other surface is formed.
상기 테이프는 칩의 중심부에 맞추어 접촉되고 소정의 열과 압력을 가하는 열접합 방식으로 접합된다. 칩상에 형성되는 외부 단자와 칩의 가장자리부에 노출된 금속 패드를 와이어로 연결하며 솔더 볼을 접합하고, 본딩 부위 및 칩의 금속 패드를 보호하기 위하여 수지로 몰딩한다. 몰딩된 반도체 패키지는 상표 등을 마킹하고 각종 검사를 거쳐 완성된다.The tape is joined in a thermal bonding manner in contact with the center of the chip and applying predetermined heat and pressure. The external terminals formed on the chip and the metal pads exposed at the edges of the chip are connected by wires, the solder balls are bonded, and molded with resin to protect the bonding sites and the metal pads of the chip. The molded semiconductor package is completed by marking a trademark and the like and performing various inspections.
종래의 단자 형성용 테이프의 접합 공정은 각각의 개별 칩 단위로 일일이 실시해야 하며, 단자 형성용 테이프 역시 칩의 크기와 형상에 맞추어 사전에 낱개별로 제작, 커팅되어야 하기 때문에 단자 형성 공정의 생산성이 크게 저하되며 반도체의 제조 비용이 증가된다는 문제점이 있다.The conventional bonding process of the terminal forming tape should be performed by each individual chip unit, and the terminal forming tape also needs to be manufactured and cut individually in advance according to the size and shape of the chip, thus greatly increasing the productivity of the terminal forming process. There is a problem that the lowering and the manufacturing cost of the semiconductor is increased.
또한, 웨이퍼상에 설치된 칩과 단자 형성용 테이프와의 접합 면적이 작기 때문에, 접합 공정에서 웨이퍼에 가해지는 단위면적당의 응력이 커서 웨이퍼가 손상되기 쉽다. 따라서, 웨이퍼의 손상을 방지하기 위하여 두께 150㎛이상의 웨이퍼를 적용해야 하기 때문에 반도체의 두께가 증가된다는 문제점이 있다.In addition, since the bonding area between the chip provided on the wafer and the tape for forming the terminal is small, the stress per unit area applied to the wafer in the bonding step is large and the wafer is easily damaged. Therefore, there is a problem that the thickness of the semiconductor is increased because a wafer having a thickness of 150 μm or more must be applied to prevent damage to the wafer.
본 발명의 목적은 단자 형성용 테이프를 칩들이 설치된 미절삭 상태의 웨이퍼에 직접 접합되어 외부 단자 형성 공정을 단순화함으로서, 반도체의 생산성을 향상시키고 제조원가를 절감하는 외부 단자 형성용 테이프를 제공하는데 있다.An object of the present invention is to provide an external terminal forming tape which improves the productivity of the semiconductor and reduces the manufacturing cost by simplifying the external terminal forming process by directly bonding the terminal forming tape to the uncut wafer in which the chips are installed.
본 발명의 또다른 목적은 반도체 제조에 적용되는 웨이퍼의 두께를 감소시켜 반도체를 박형화하는 외부 단자 형성용 테이프를 제공하는데 있다.It is still another object of the present invention to provide a tape for forming an external terminal which reduces the thickness of a wafer applied to semiconductor manufacturing to reduce the thickness of the semiconductor.
도 1은 종래의 외부 단자 형성용 테이프의 개략적인 평면도이고,1 is a schematic plan view of a conventional external terminal forming tape,
도 2는 본 발명에 의한 외부 단자 형성용 테이프의 개략적인 평면도이고,2 is a schematic plan view of an external terminal forming tape according to the present invention;
도 3은 본 발명에 의한 외부 단자 형성용 테이프의 개략적인 단면도이고,3 is a schematic cross-sectional view of an external terminal forming tape according to the present invention;
도 4는 본 발명의 단자 형성용 테이프가 적용된 반도체 패키지의 개략적인 단면도이다.4 is a schematic cross-sectional view of a semiconductor package to which the tape for forming a terminal of the present invention is applied.
* 도면의 주요 부분에 따른 부호의 설명* Explanation of the symbols according to the main parts of the drawings
1 : 금속 단자 패턴,1: metal terminal pattern,
2 : 와이어 연결용 홀,2: hole for wire connection,
3 : 베이스 필름,3: base film,
4 : 접착제층,4: adhesive layer,
5 : 접착제층 보호 필름,5: adhesive layer protective film,
11 : 금속 단자 형성용 테이프,11: tape for forming a metal terminal,
12 : 칩상의 금속 패드,12: metal pad on the chip,
13 : 와이어,13: wire,
14 : 솔더 볼,14: solder ball,
15 : 칩.15: chip.
본 발명에서는 칩이 설치된 미절삭 상태의 웨이퍼상의 칩들의 표면에 전기적 연결을 위한 외부 단자를 일괄적으로 형성하는 외부 단자 형성용 테이프가 개시된다.Disclosed is an external terminal forming tape for collectively forming external terminals for electrical connection on surfaces of chips on a wafer in a non-cut state where chips are installed.
도 2를 참조하면, 단자 형성용 테이프는 접합되는 웨이퍼와 동일한 형상과 크기를 지니며, 칩들에 형성되는 외부 단자와 칩의 금속 패드를 와이어로 연결하기 위하여, 웨이퍼상의 칩의 금속 패드 부위과 일치되는 홀(2)이 형성되는 것을 특징으로 한다.Referring to FIG. 2, the terminal forming tape has the same shape and size as the wafer to be bonded, and is matched with the metal pad portion of the chip on the wafer to connect the external terminal formed on the chips with the metal pad of the chip by wire. The hole 2 is formed.
본 발명에 의한 단자 형성용 테이프의 구조를 도 3을 참조하여 상세히 설명하면, 수지제의 베이스 필름(3)의 일측 표면에 칩과 접합하기 위한 접착제층(4)이 형성되고 타측 표면에 금속제의 단자 패턴(1)이 형성된다. 금속제의 단자 패턴(1)은 일측 표면이 베이스 필름(3)의 표층에서 노출되는 형태로 삽입된다.The structure of the tape for forming a terminal according to the present invention will be described in detail with reference to FIG. 3. An adhesive layer 4 for bonding with a chip is formed on one surface of the base film 3 made of resin, and the metal surface is formed on the other surface. The terminal pattern 1 is formed. The terminal pattern 1 made of metal is inserted in such a manner that one surface thereof is exposed at the surface layer of the base film 3.
바람직하게, 베이스 필름(3)은 폴리이미드 수지를 적용하여 형성된다.Preferably, the base film 3 is formed by applying a polyimide resin.
바람직하게, 금속제의 단자 패턴(1)은 구리를 적용하여 형성되며, 반도체가 적용되는 다기능 디바이스에 대응하기 위하여 적어도 1개층 이상으로 구성된다.Preferably, the metal terminal pattern 1 is formed by applying copper, and is composed of at least one layer or more so as to correspond to the multifunctional device to which the semiconductor is applied.
바람직하게, 접착제층(4)은 소정의 열과 압력이 가해지면 접착력이 발생하는 감열성 접착제를 적용한다.Preferably, the adhesive layer 4 applies a thermosensitive adhesive that generates adhesive force when a predetermined heat and pressure are applied.
바람직하게, 접착제층(4)의 표층에 접착제층(4)을 보호하는 접착제층 보호 필름(5)이 형성되며, 접합 공정시에는 접착제층(4)과 분리된다.Preferably, the adhesive layer protective film 5 which protects the adhesive layer 4 is formed in the surface layer of the adhesive layer 4, and is isolate | separated from the adhesive layer 4 at the bonding process.
본 발명의 단자 형성용 테이프가 적용된 반도체 패키지의 외부 단자 형성 공정 및 외부 단자가 형성된 상태의 구조를 도 4를 참조하여 상세하게 설명한다.An external terminal forming process of the semiconductor package to which the terminal forming tape of the present invention is applied and a structure in which an external terminal is formed will be described in detail with reference to FIG. 4.
상기 단자 형성용 테이프는 접착층이 형성된 표면을 칩이 형성된 미절삭 웨이퍼상에 각각의 형상이 일치되도록 접촉되고, 소정의 열과 압력을 가하는 열 압착 방식으로 접합된다. 단자 형성용 테이프는 면적이 넓은 미절삭 상태의 웨이퍼에 접합되므로 웨이퍼에 가해지는 단위면적당의 응력이 작기 때문에 웨이퍼의 두께를 100㎛까지 박형화할 수 있다.The terminal forming tape is brought into contact with the surface on which the adhesive layer is formed on the uncut wafer on which the chips are formed so as to coincide with each other, and is bonded by a thermocompression method applying a predetermined heat and pressure. Since the terminal-forming tape is bonded to the wafer in a large uncut state, the stress per unit area applied to the wafer is small, so that the thickness of the wafer can be reduced to 100 mu m.
단자 형성용 테이프를 적용하여 금속제의 외부 단자 패턴(1)을 웨이퍼상의 칩들의 표면에 형성하면, 웨이퍼를 블레이드를 이용하여 개별 칩으로 절삭한다. 이후, 상기 금속 단자(1)와 칩(16)의 금속 패드(12) 사이를 테이프의 홀(2)을 통하여 와이어(13)로 연결하며 솔더 볼(14)을 접합하고, 본딩 부위 및 칩의 금속 패드(12)를 보호하기 위하여 수지로 몰딩한다. 몰딩된 반도체 패키지는 상표 등을 마킹하고 각종 검사를 거쳐 완성된다.When the external terminal pattern 1 made of metal is formed on the surface of the chips on the wafer by applying the terminal forming tape, the wafer is cut into individual chips using the blades. After that, the solder ball 14 is bonded between the metal terminal 1 and the metal pad 12 of the chip 16 with the wire 13 through the holes 2 of the tape, and the solder balls 14 are bonded to each other. In order to protect the metal pad 12, it is molded with resin. The molded semiconductor package is completed by marking a trademark and the like and performing various inspections.
본 발명에 의한 외부 단자 형성용 테이프는 미절삭 상태의 웨이퍼에 설치된 칩의 외부 단자 형성 공정을 단순화함으로서 반도체의 생산성이 향상되고 제조원가가 절감된다.The external terminal forming tape according to the present invention simplifies the external terminal forming process of the chip installed on the wafer in the uncut state, thereby improving the productivity of the semiconductor and reducing the manufacturing cost.
또한, 테이프 접합 공정시 웨이퍼에 가해지는 단위면적당의 응력이 감소됨으로 웨이퍼의 두께를 감소시켜 반도체를 박형화한다.In addition, since the stress per unit area applied to the wafer in the tape bonding process is reduced, the thickness of the wafer is reduced to reduce the thickness of the semiconductor.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990047365A KR20010039116A (en) | 1999-10-29 | 1999-10-29 | Tape for forming out terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990047365A KR20010039116A (en) | 1999-10-29 | 1999-10-29 | Tape for forming out terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010039116A true KR20010039116A (en) | 2001-05-15 |
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ID=19617551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990047365A KR20010039116A (en) | 1999-10-29 | 1999-10-29 | Tape for forming out terminal |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010039116A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100696581B1 (en) * | 2006-02-20 | 2007-03-19 | 코리아유니크 주식회사 | shock absorptionon devisce for cun paper shredder |
-
1999
- 1999-10-29 KR KR1019990047365A patent/KR20010039116A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100696581B1 (en) * | 2006-02-20 | 2007-03-19 | 코리아유니크 주식회사 | shock absorptionon devisce for cun paper shredder |
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