KR20010039026A - Field Emission Display - Google Patents

Abstract

PURPOSE: A field emission display (FED) is provided which removes residual image effect by reducing power consumption of data driving circuit and enables high speed operation of the data driving circuit, thereby increasing gray scale, and can be used in all voltage control methods such as PWM (pulse width modulation) and FRC (frame rate control). CONSTITUTION: The field emission display (FED) comprises a cathode data circuit (330) outputting data signals; a gate scan driving circuit (370) reducing power consumption by decreasing the number of Cgc, capacitance between gate and cathode in which the cathode data circuit is connected to a cathode line by using a method in which high impedance state is maintained after high voltage scanning by generating three states of output by a high voltage output stage; and a high voltage output stage controlling a voltage level excited to the concerned gate in three types of conditions between each output stages and corresponding each low lines in the gate driving circuit.

Description

Field Emission Display (FED) {Field Emission Display}

Field of the Invention The present invention relates to a field emission display (FED) and a driving method thereof. More specifically, the present invention provides a gate driving circuit having three output states, which enables a data driving circuit to operate at a high speed and consume power. It relates to a field emission display and a driving method thereof.

In general, the driving method of the FED is a method in which gate lines and cathode lines are orthogonal to control each pixel, and an appropriate signal is applied to each line to individually select and control pixels at crossing positions. Use the matrix method. As such, the matrix method requires a scan driving circuit and a data driving circuit.

1 shows a cross-sectional view of a FED tip showing parasitic capacitance components. The largest capacitance here is Cgc, the capacitance between the gate and the cathode, and thousands of tips form one pixel. At this time, the capacitance Cgc per pixel is about 1pF.

FIG. 2 shows an equivalent circuit diagram of an entire drive circuit for explaining a general voltage driving method, and FIG. 3 shows an equivalent circuit diagram illustrating a voltage driving method of a conventional field emission device.

2 shows an FED panel, a scan driving circuit 220 as a gate driving circuit, a PWM data driving circuit 230 for driving a cathode, and a control signal and data necessary for the two circuits, and sends external video. And an FED controller 210 connected to the PC device 215.

In FIG. 3, the field emission device has a constant capacitance between the gate and the cathode. The field emission display connected to the gate lines Row1, Row2, ..Rown and the cathode lines Col1, col2, col3, ... Coln or the capacitance Cgc between the gate and the cathode of the field emission device are connected in parallel. have. When the data is applied to the cathode when driving the FED, see the cathode data driving circuit, the cathode data driving circuit 230 of FIG. 2, and the cathode lines Col1, col2, col3, and the like while charging and discharging all the capacitances connected in parallel. ... apply a voltage to Coln). This applied capacitance is a very large value and a large value of current is required for charge-discharge, so power consumption is increased and the operation speed of the driving circuit is reduced.

The formula for calculating the power consumption required for charging and discharging this capacitance is as follows.

P _d = N Cgc V ² _{HVDDf clk} ..... (1)

Where N is the number of gate lines, Cgc is the capacitance between the gate and the cathode, V _HVDD is the high voltage applied to the cathode, and f _clk represents the operating frequency of the data driver circuit. According to the above formula (1) of the power consumption amount, the general capacitance Cgc value for one pixel is about 1 pF.

An FED having a resolution of 160 × 120 indicates the number of gate lines 120 and the number of cathode lines 160. In the case of color FED, the number of cathode lines is 480 lines of 160 × 3. When data is applied to the cathode when driving an FED having a resolution of 160 × 120, the cathode driving circuit applies a voltage to the cathode line while charging and discharging a capacitance of 120 pF. These capacitances are very large and require a large value of current when charging and discharging, so the power consumption is increased and the operating speed of the driving circuit is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and includes a control device for controlling a voltage level applied to a corresponding gate in three states between each output terminal and a corresponding row line in a gate driving circuit. After the voltage is applied to the high voltage Hdd and the gate driving circuit is switched to 0 volts, the gate driving circuit maintains the floating state, thereby lowering the capacitance connected to the cathode line so that the cathode driving circuit consumes power required for charging and discharging the capacitance. The purpose is to provide a field emission display that reduces the speed and operates at high speed.

1 is a cross-sectional view of a FED tip showing parasitic capacitance components;

2 is a circuit diagram illustrating a conventional voltage driving method of electric field emission;

3 is an equivalent circuit diagram of a conventional field emission display.

4A is an output waveform diagram of a gate driving circuit of a conventional field emission display;

4B is an output waveform diagram of the gate driving circuit proposed in the present invention;

5A is a circuit diagram of a high voltage output stage having an output of two general states;

5 (B) is a circuit diagram of a high voltage output stage having an output of three states for application to the present invention;

6 is a FED driving circuit diagram when used as a field emission display according to the present invention;

Fig. 7 is an equivalent circuit diagram of the entire drive circuit when data is applied.

<Explanation of symbols for the main parts of the drawings>

310: controller 330: data driving circuit

333: demodulator 335: shift register

370: gate driving circuit 52: buffer

According to the present invention for achieving the above object, in the field emission display, a cathode data circuit for outputting a data signal,

The output of the three states is generated by the high voltage output stage to perform a high voltage scan, and then maintains a high impedance state, thereby reducing the number of Cgc, the capacitance between the gate and the cathode of which the cathode data circuit is connected to the cathode line, Gate scan driving circuit to reduce power consumption,

It includes a high voltage output stage for controlling the voltage level applied to the corresponding gate in three states between each output terminal and the corresponding row line in the gate driving circuit.

In addition, in the gate driving circuit of the field emission display, a high voltage is applied to only the pixel to which data is applied, and the gate of the other FED pixel is maintained in a floating state, thereby reducing the capacitance connected in parallel to the cathode line, thereby reducing the power of the data driving circuit. Reduces consumption and speeds up

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B show the output waveforms of the conventional gate driving circuit and the driving circuit proposed in the present invention, respectively. 4A sequentially scans from the GND level to the high voltage HVdd level according to a clock cycle.

However, in the proposed scheme of FIG. 4B, the gate scan driving circuit 370 connected to the FED gate is set to the clock waveform voltage which is maintained at the HVdd and the ground level of the applied voltage in the floating state, and maintained at the high impedance in the floating state. Do a scan. The data driving circuit 330 is connected to the cathode to apply data to the cathode at a constant voltage.

4B scans the clock waveform in the high impedance state of the floating state from HVdd and GND levels of the gate driving circuit. That is, after a high voltage is applied to the gate, the gate is switched to the GND state, and is changed to the high impedance state. Accordingly, the period in which the capacitance Cgc is formed between the gate and the cathode is only a state in which HVdd and GND are applied to the gate.

FIG. 5A is a high voltage output stage having an output of two general states, and FIG. 5B is a high voltage output stage having three states of outputs for application to the present invention. In FIG. 5B, the HVout terminal, which is an output terminal, is connected to the gate lines Row1, Row2, ..Rown of the output terminal of the gate driving circuit to maintain a floating state when a low signal is applied to the control signal Control. When the high signal is applied to the control signal Control, the signal applied with the logic voltage applied to Vin is changed to HVdd level, which is a high voltage level, and sent to the output.

FIG. 6 is a FED driving circuit diagram showing a driving method when used as a field emission display with respect to FIG. 3 according to the present invention.

6 shows a gate drive circuit 370 having an FED panel and three voltage level outputs in a FED drive circuit, a voltage drive type data drive circuit 330 for driving a cathode, and a control signal required for these two circuits. And a FED controller 310 for sending data.

Referring to FIG. 2, the display of FIG. 6 has a large capacitance between the gate and the cathode, the capacitance Cgc between the gate and the cathode of the field emission device is connected in parallel, and the cathode data driving circuit 330 ) Applies a voltage to the cathode lines Col1, col2, col3, ... Coln while charging and discharging all capacitances connected in parallel.

In FIG. 6, the cathode data driving circuit 330 is connected to each cathode line of the panel to receive and drive a data signal of a predetermined bit (for example, 4 bits), and the data signal is a video signal based on the video device 315. do. In addition, the cathode data driving circuit 330 includes a shift register and a latch 335 and a demodulator 333 for temporarily transmitting and temporarily storing a signal output from the FED controller 310.

The gate driving circuit 370 receives a control signal input from the FED controller and receives a plurality of row lines Row1, Row2, Row3, ... Row n-1, Row connected to a plurality of gates in the panel 300. drive n). The gate scan driving circuit 370 is connected to a plurality of row lines Row1, Row2, Row3, ... Row n-1, Row n. The gate scan driving circuit 370 is connected to the gate lines Row1, Row2, ..Rown and the cathode lines Col1, col2, col3,... Coln and sequentially outputs a scan signal. A high voltage output terminal 52a, 52b, ... 52n, see the circuit diagram of FIG. 5B, is provided between each output terminal of the gate driving circuit and each gate row line corresponding thereto to control the voltage level flowing to the corresponding gate in three states. .

FIG. 7 is an equivalent circuit diagram illustrating a voltage driving method modeled by capacitance when data is applied in the field emission device of FIG. 6, and schematically illustrates a voltage driving method. 7 is an equivalent circuit of FIG. 6 connected to a plurality of row lines Row1, Row2, Row3, ... Row n-1, Row n and a scan driving circuit sequentially outputting scan signals. I can understand.

FIG. 7 shows a case where a high voltage is applied to the row line Row2 and data is applied. Fig. 7 shows a case where high voltage is applied to the row line Row2 and data is applied. At this time, the gate line of row line Row 1) is connected to GND. The gate line from row line Row 3 to row N maintains the floating high impedance state after the GND state. In this case, the parasitic capacitance component Cgc is not formed between the gate and the cathode. As a result, Cgc is formed only between the gate and the cathode of the FED tip of the portion connected to the row line Row 2, which is a pixel to which data is applied, and the row line Row 1 which is pulsed immediately before and maintains the GND state. This lowers the capacitance connected to the cathode line and reduces the power consumption required for the cathode drive circuit to charge-discharge the capacitance. At this time, the power consumption (Pd) is expressed as a formula.

P _d = 2 Cgc V ² _{HVDDf clk} ,

Where Cgc is the capacitance between the gate and the cathode, V _HVDD is the high voltage applied to the cathode, and represents the operating frequency of the f _clk data driving circuit. In addition, since the value of the capacitance of charge-discharge decreases, high-speed operation is performed.

According to the present invention as described above, when the present invention is used, the power consumption of the data driving circuit can be lowered and the gray scale can be increased since the data driving circuit can be operated at a higher speed as compared with the conventional method. I can eliminate it. In addition, it can be used for all voltage control methods such as pulse width modulation (PWM) and frame rate control (FRC).

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (4)

In a field emission display, A cathode data circuit for outputting a data signal; The output of the three states is generated by the high voltage output stage to perform a high voltage scan, and then maintains a high impedance state, thereby reducing the number of Cgc, the capacitance between the gate and the cathode of which the cathode data circuit is connected to the cathode line, Gate scan driving circuit to reduce power consumption, And a high voltage output stage controlling a voltage level applied to a corresponding gate in three states between each output stage and a corresponding row line in the gate driving circuit. The method of claim 1, And the high voltage output terminal applies a high voltage to a gate only to a pixel to which data is applied, and maintains a floating state of other FED pixels to reduce power consumption and speed up data driving circuits. The method of claim 1, And a high voltage output stage configured to control a voltage level flowing to a corresponding gate in three states between each output terminal of the gate driving circuit and each gate row line corresponding thereto. The method of claim 1, The high voltage output terminal is connected to the gate line of the output terminal of the gate driving circuit to maintain a floating state when a low signal is applied to a control signal, and a logic voltage applied to an input voltage when a high signal is applied to the control signal. A field emission display, characterized in that for outputting the signal applied to the high voltage level.