KR20010038470A - Apparatus for compatible multi-bit interfacing in application-specific integrated circuit - Google Patents

Abstract

PURPOSE: An interface device which is exchanged with a multi-bit bus of an ASIC(application-specific integrated circuit) is provided to allow the interface with respect to a CPU having a multi-bit mode. CONSTITUTION: An interface device comprises an address multiplying section(20) which outputs 24 bit address signal. A data multiplying section(30) is provided to create 32 bit data. A multiplexing section(40) is provided to selectively outputs 24 bit address signal. A control section(50) is provided to control the input/output operation of the address multiplying section(20) and the data multiplying section(30). The first logic multiplying device(60) outputs an address ready signal by logically multiplying the address signal of the address multiplying section(20). The second logic multiplying device(70) outputs a data ready signal by logically multiplying the data signal of the data multiplying section(30).

Description

Apparatus for compatible multi-bit interfacing in application-specific integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU interface device of an application-specific integrated circuit (ASIC), and in particular, an application-specific integrated circuit adapted to interface with a CPU having a multi-bit mode. An interface device compatible with multiple bit buses.

In general, application specific integrated circuits are designed to perform a specific function and have an interface for exchanging data with an external CPU.

The CPU interface of the conventional application specific semiconductor is described below.

First, Figure 1 is a block diagram of an interface device of a conventional application specific integrated circuit.

As shown in the drawing, the conventional interface device includes a decoder unit 11 that receives an 8-bit address signal and decodes an address to read / write corresponding data in a register, and an address output from the decoder unit 11. A first interface block including a register unit 12 for reading and writing corresponding data in accordance with an operation signal ENB, and a control unit 13 for controlling a read / write operation of the register unit 12;

A decoder unit 14 which receives a 16-bit address signal and decodes an address to read / write the corresponding data in the register, and reads / writes the data in accordance with the address operation signal ENB output from the decoder unit 14. The second interface block includes a register section 15 and a control section 16 that controls read / write operations of the register section 15.

The operation of the conventional application specific semiconductor interface device configured as described above is as follows.

First, in the case of the first interface block, when a signal is input through the 8-bit bus, the decoder unit 11 decodes the 8-bit address signal (8 BIT ADDRESS) to the register unit 12 that will read / write 8-bit data. The address operation signal (Adddress Enable, ENB) is output.

Then, the register unit 12 reads and writes data in parallel to the plurality of CPU addresses designated by the address operation signal ENB output from the decoder unit 11 through an 8-bit data bus. . At this time, the control unit 13 controls the data read / write operation of the register unit 12.

In addition, by processing the 16-bit data in the second interface block, as in the case of processing the 8-bit data in the first interface block, it is possible to speed up the read / write operation of the data. That is, when the 8-bit address signal 8 BIT ADDRESS is input, the decoder 14 decodes the corresponding address information and outputs the address operation signal ENB.

Then, the register unit 15 reads / writes data through the 16-bit data bus at the address designated by the address operation signal ENB according to the control signal of the controller 16. This results in faster data read / write operations than when using an 8-bit data bus.

As such, the conventional interface device exchanges data by interfacing with the CPU in 8 bits or 16 bits.

However, such a conventional device has a problem in that interoperability between CPUs using different 8-bit data buses and CPUs using 16-bit data buses is incompatible with each other.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is an application capable of enabling an interface with a CPU having a multi-bit mode when designing an application specific semiconductor. The present invention provides an interface device compatible with multiple bit buses of an application specific integrated circuit.

In order to achieve the above object, an interface device compatible with a multi-bit bus of an application specific integrated circuit according to the present invention includes an address multiplexer for generating and outputting a 24-bit address signal from an externally input multi-bit address signal. ; A data multiplexer for generating 32-bit data from multi-bit data input from the outside; A multiplexer for multiplexing a 24-bit address signal output from the address multiplexer and a 24-bit address signal directly input from the outside and selectively outputting a 24-bit address signal; A control unit controlling an input / output operation of the multi-bit data of the address multiplexer and the data multiplexer; A first AND product for performing an AND operation on the address signals of the address multiplexer to output an ADDRESS READY signal indicating whether a 24-bit address signal has been successfully constructed; The technical construction is characterized in that it consists of a second logical multiplication device for outputting a data ready (DATA READY) signal indicating that 32-bit data is correctly configured by performing a logical multiplication of the data signal of the data multiplexer.

1 is a block diagram of an interface device of a conventional application specific integrated circuit,

2 is a block diagram of an interface device compatible with the multi-bit bus of an application specific integrated circuit according to the present invention.

Explanation of symbols on the main parts of the drawings

20: address multiplexer 21: first demultiplexer

22: second demultiplexing unit 23: address register unit control unit

30: data multiplexer 31: third demultiplexer

32: fourth demultiplexer 33: data register

40: multiplexing unit 50: control unit

60: first logical product element 70: second logical product element

Hereinafter, an embodiment according to the technical concept of the interface device compatible with the application-specific semiconductor of the present invention, the CPU is as follows.

First, Figure 2 is a block diagram of an interface device compatible with the application specific semiconductor of the central processing unit according to the present invention.

As shown in the drawing, the interface device compatible with the application-specific semiconductor of the central processing unit according to the present invention includes an address multiplexer that generates and outputs a 24-bit address signal from a multi-bit address signal input from an external device. 20; A data multiplexer 30 for generating 32-bit data from multi-bit data input from the outside; A multiplexing unit (40) for selectively outputting a 24-bit address signal by multiplexing a 24-bit address signal output from the address multiplexer (20) and a 24-bit address signal directly input from the outside; A controller 50 for controlling input / output operations of the multi-bit data of the address multiplexer 20 and the data multiplexer 30; A first AND product 60 for performing an AND operation on the address signal of the address multiplexer 20 to output an address ready signal indicating whether the 24-bit address signal has been successfully constructed; A second logical multiplication device 70 outputs a data ready signal indicating whether 32-bit data is correctly configured by performing a logical AND operation on the data signal of the data multiplexer 30.

The address multiplexer 20 includes: a first demultiplexer 21 for demultiplexing data input through a 16-bit bus; A second demultiplexer 22 which demultiplexes data input through an 8 bit bus; The first demultiplexing unit 21 and the second demultiplexing unit 22 are composed of an address register unit 23 for generating and outputting a 24-bit address signal.

In addition, the data multiplexer 30 includes: a third demultiplexer 31 for demultiplexing data input through an 8 bit bus; A fourth demultiplexer 32 for demultiplexing data input through a 16 bit bus; And a data register 33 for generating and outputting 32-bit data according to the data output from the third demultiplexer 31 and the fourth demultiplexer 32, respectively.

The operation of the interface device compatible with the application-specific semiconductor of the central processing unit according to the present invention configured as described above is as follows.

First, the address multiplexer 20 receives multiple bits of address information through a 16 bit bus and an 8 bit bus, and demultiplexes the 24 bit address signal. 40).

That is, the address multiplexer 20 demultiplexes the data input through the 16-bit bus 16 bit bus in accordance with the control signal of the controller 50 in the first demultiplexer 21, the 8-bit bus 8 The second demultiplexer 22 demultiplexes data input through BIT BUS). The address register section 23 then generates a 24-bit address signal from the address data output from the first demultiplexing section 21 and the second demultiplexing section 22 and multiplexes it via a 24-bit bus. Output to the unit 40.

In this case, the first AND device 60 performs an AND operation on the address data of the address multiplexer 20 to output an address ready signal indicating whether the 24-bit address has been successfully generated to the CPU.

In addition, the data multiplexer 30 receives the data information through the 16-bit bus and the 8-bit bus from the outside, and demultiplexes the 32-bit data to the CPU.

That is, the third demultiplexer 31 demultiplexes the data input through the 8 bit bus according to the control signal of the controller 50, and is input through the 16 bit bus. The fourth demultiplexer 32 demultiplexes the data. Then, the data register unit 33 generates 32-bit data (32 BIT DATA) from the data signals output from the third demultiplexing unit 31 and the fourth demultiplexing unit 32, respectively, to read the control unit 50. Input / output to the CPU according to / write signal.

In this case, the second AND product 70 performs an AND operation on the data signal of the data multiplexer 30 to output a data ready signal indicating whether 32-bit data is correctly configured to the CPU.

Then, the multiplexer 40 multiplexes the 24-bit address signal output from the address multiplexer 20 and the 24-bit address signal directly input from the outside to selectively output the 24-bit address signal to the CPU. That is, when the direct / indirect selection signal DIRECT / INDIRECT indicates DIRECT, a 24-bit address signal input directly from the outside to the multiplexing unit 40 is output, and the direct / indirect selection signal DIRECT / INDIRECT is output. When indicating indirect, the 24-bit address signal input from the address multiplexer 20 is outputted.

Next, the controller 50 controls the data input / output operations of the address multiplexer 20 and the data multiplexer 30 according to the input mode selection signal WIDTH and the read / write signal READ / WRITE ENB. . That is, when the mode selection signal WIDTH is '0', it operates in 8 bit mode, and when the mode selection signal WIDTH is '1', it operates selectively in 16 bit mode. The address multiplexer 20 and the data multiplexer 30 perform a write operation when (READ / WRITE ENB) is '0' and a read operation when the read / write signal (READ / WRITE ENB) is '1'. Will be controlled separately.

The read / write operation of the multi-bit data of the interface device according to the present invention operating as described above will be described in detail as follows.

First, a read and write operation of 8 bits of data among multi-bit data that can be input will be described.

The write operation of the input 8-bit data may include a 24-bit address signal (24 BIT ADDRESS) through the multiplexing unit 40 when the least significant bit (LSB) of the CPU output address is '00'. ) And writes data in the first 8 bits of the data register section 33 operating in 32 bits in the data multiplexing section 30.

When the least significant bit LSB of the CPU output address is '01', the 24-bit address signal 24 BIT ADDRESS is output through the multiplexing unit 40, and the data multiplexer 30 operates in 32 bits. Data is written to the second 8 bits of the data register section 33.

In addition, when the least significant bit (LSB) of the CPU output address is '10', the 24-bit address signal 24 BIT ADDRESS is output through the multiplexing unit 40 and the data register unit is output from the data multiplexer 30. Write data to the third 8 bits of (33).

In addition, when the least significant bit LSB of the CPU output address is '11', the 24-bit address signal 24 BIT ADDRESS is output through the multiplexing unit 40, and the data register unit 30 in the data multiplexer 30 is output. Write data to the fourth 8 bits of (33).

As such, the data multiplexer 30 configures and outputs 32-bit data, thereby performing a write operation on 8-bit data.

Subsequently, a read operation on 8 bits of data is performed as follows.

First, when 32-bit data is input to the data multiplexer 30, when the least significant bit LSB of the CPU output address is '00', the data register unit 33 consisting of 32 bits The first 8 bits of the CPU can be read.

When the least significant bit of the CPU output address is '01', the CPU reads the second 8 bits of the data register unit 33 composed of 32 bits. When the least significant bit of the CPU output address is '10', the data register unit 33 If the CPU reads the third 8 bits of) and the least significant bit of the CPU output address is '11', the CPU can read the fourth 8 bits of the data register unit 33.

In this manner, read and write operations are performed on 8 bits of data.

The following describes the read and write operations for 16 bits of data.

First, a write operation on 16-bit data outputs a 24-bit address signal (24 BIT ADDRESS) through the multiplexing unit 40 when the least significant bit LSB of the CPU output address is "0x". In the data multiplexer 30, a data write operation is performed on the first 8 bits and the second 8 bits of the data register unit 33 through the second demultiplexer 30.

In addition, when the least significant bit of the CPU output address is "1x", the 24-bit address signal 24 BIT ADDRESS is output through the multiplexing unit 40, and the data multiplexer 30 supplies the second demultiplexer 30. Through this, 16-bit data can be processed by writing data to the third and fourth eight bits of the data register unit 33.

In this way, the data multiplexer 30 outputs 32-bit data to write to the CPU.

Subsequently, when the 32-bit data is input to the data multiplexer 30, the read operation on the 16-bit data is performed by the first of the data register unit 33 that operates in 32 bits when the least significant bit of the CPU output address is "0x". When the CPU reads the 8 bits and the second 8 bits, and the least significant bit of the CPU output address is "1x", the CPU reads the third 8 bits and the fourth 8 bits of the data register section 33 to make the data 16 bits. It will be possible to handle.

As such, the device according to the present invention enables an application-specific integrated circuit to be compatible with CPUs produced by different producers by enabling mutually intersecting interfaces between 8-bit CPUs and 16-bit CPUs.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the interface device compatible with the multi-bit bus of the application-specific integrated circuit according to the present invention, by designing the application-specific integrated circuit to each other by allowing the cross-interface interface between the 8-bit CPU and 16-bit CPU Application-specific integrated circuits can be made compatible with CPUs produced by other producers.

Claims (3)

In the interface device of the application specific semiconductor, An address multiplexer for generating and outputting a 24-bit address signal from an externally input multi-bit address signal; A data multiplexer for generating 32-bit data from multi-bit data input from the outside; A multiplexer for multiplexing a 24-bit address signal output from the address multiplexer and a 24-bit address signal directly input from the outside and selectively outputting a 24-bit address signal; A control unit controlling an input / output operation of the multi-bit data of the address multiplexer and the data multiplexer; A first AND device for performing an AND operation on the address signals of the address multiplexer to output an address ready signal indicating whether a 24-bit address signal has been successfully constructed; An interface compatible with the multiple bit bus of the application specific integrated circuit comprising a second logical multiplication device configured to perform an AND operation on the data signal of the data multiplexer and output a data ready signal indicating whether 32-bit data is correctly configured. Device. The method of claim 1, wherein the address multiplexer, A first demultiplexer for demultiplexing data input through the 16-bit bus; A second demultiplexer for demultiplexing data input through an 8-bit bus; The first demultiplexer and the second demultiplexer in the address register unit for generating and outputting a 24-bit address signal according to the demultiplexed and output data is composed of a multi-bit bus of the application-specific integrated circuit, characterized in that Interface device. The method of claim 1, wherein the data multiplexing unit, A third demultiplexer for demultiplexing data input through the 8-bit bus; A fourth demultiplexer for demultiplexing data input through the 16-bit bus; And a data register unit for generating and outputting 32-bit data according to data output from the third demultiplexer and the fourth demultiplexer, respectively.