KR20010034823A - Coplanar oscillator circuit structures - Google Patents

Abstract

The oscillator circuit 20 having the flip chip metallization pattern and the base substrate metallization pattern is formed such that a common drain oscillator having a structure including a common drain 38 inserted between the source 40 and the gate 36 terminals is formed. Is formed. The oscillator circuit provides an effective RF common reference to reduce eddy current inductance components that degrade oscillator power and phase noise at high frequencies.

Description

Coplanar Oscillator Circuit Structures {COPLANAR OSCILLATOR CIRCUIT STRUCTURES}

In almost all oscillators using three-terminal active elements, a single path from input to output is required. The input to the three-terminal active device oscillator includes an input current / voltage phase and two output current carrying terminals. The two output current carrying terminals have in phase or abnormal (inverting) current at low frequencies. Effectively it has a direct current. In the case of a microwave FET, the control input is a gate and the inverted output is a drain. In large common source FETs commonly used to provide large output power, a gate terminal is connected to the circuit, and the circuit has a reverse path extending over a large distance before returning to connect with the drain terminal. Any eddy current inductance or capacitance associated with the current path connected to the gate and inverting terminals can limit the available oscillator frequency response.

Conventional oscillator circuits have used wire bonds to connect active elements to feedback circuits and resonators formed on the substrate. At millimeter frequencies, the shortest wire bond can be one tenth of the wavelength. Wire bonds also act like loops with high vortex inductances. This is because they are relatively far from the conductor carrying the reverse current. Such a loop can inject unacceptable radiation losses.

The lead element has a lead of 600-2500 micron center. The lead of the device passes through a glass-metal, ceramic, or plastic seal that has a loss at microfrequency. In order to reduce losses and vortex inductance, it is an advantage to eliminate lead elements and wire bonds. Flip-chip or bump bond chips have very low uniform eddy current inductances.

Other existing circuit structures have used substrates in which associated striplines or microstrip conductor resonance and feedback circuits are to be connected to active three-terminal devices. Microstrip circuits generally have additional dielectric loss and stored magnetic energy in the electric field between the signal line on one side of the substrate and the ground plane on the other side of the substrate. One advantage is the elimination of microstrip circuits from high frequency oscillators. Coplanar circuits have low dielectric losses because less electric field is connected to the dielectric, and lower radiation losses because the electric field is concentrated between more closely spaced conductors.

Common-drain circuit structures are often used in high frequency circuits. This is because improved gain-frequency characteristics are provided. Vortex inductance and capacitance in the circuit path associated with the common terminal of the FET oscillator affect the inductance and large delay associated with the gate-drain circuit. This causes frequency limitations due to delay and inductance. Loss of the current path to the common terminal can cause excess phase noise.

Large FET devices placed from an array of small FET devices impart lower phase noise of the oscillator compared to small FET devices. This is because the signals that are anti-scanned from the elements of the FET array are statistically coherently combined. However, assembling large devices from an array of small FETs can result in a relatively long signal path from device terminals to device terminals. Long paths increase vortex inductance and increase radiation loss, reducing the gain of large structures.

Combined circuit structures are known, in which individual elements of an integrated circuit element array are each connected to one or more subsets of tuning / impedance matching circuits to combine input / output signals for impedance matching or power combination. Examples of repeating circuit subsets connected to the circuit are described in US Pat. No. 5,623,231 to Morhinkel et al.

Mohinkel et al. Show a common-source microwave amplifier chip having a number of FETs and a number of related terminals disposed at select locations on the chip's common surface. The associated circuit is formed on the substrate and has a plurality of terminals corresponding to the device terminals on the chip. An input signal line and an output signal line on the substrate are connected to related terminals, and multiple input and output lines are combined.

Mohinkel et al show a common-source amplifier with signal inputs from combination circuits connected to the gate terminals of multiple FET pairs. The signal output from the drain terminal of the FET pair is combined on the output signal line. If the metallization pattern is connected from drain to gate to fabricate an oscillator for this circuit, the pattern will have a long path.

Examples of common-drain microwave circuits are shown in US Pat. No. 4,135,168 to Wade et al. Wade shows a common-drain FET circuit having source and gate connections to associated circuitry around the substrate. The drain connection is made of large thermally eroded posts that are not coplanar but part of the metallization of the source-gate circuit. The extended reverse path for the current from gate to drain and from source to drain introduces significant series inductance and shunt capacitance.

In short, large conventional common-source devices have problems with losses and vortex inductances associated with large physical arrangements needed to connect resonators and feedback circuits to input and output terminals. In conventional common-drain circuits, long signal paths for reverse current from gate to drain and from source to drain are a feature of physical placement.

Conventional millimeter / microwave planar circuits have shown unnecessary bond wires or microstrip radiation losses related to inductance and capacitance of long RF connections in gate-drain and source-drain circuits. It would be advantageous to have a low vortex common-drain circuit structure that can be used to make oscillators with short connections and low eddy currents.

The present invention relates to an integrated circuit flip-chip circuit comprising multiple active elements mounted on a substrate having a metallization pattern connected to the integrated circuit. In particular, the present invention relates to millimeter-wave integrated oscillator circuits constructed with multiple interconnect repeating cells, including metallization patterns with reduced vortex connections to common terminals, and in particular coplanar oscillator circuit structures.

In order to understand the objects and advantages of the present invention, the following embodiments will be described with reference to the accompanying drawings.

1 is a plan view of a basic coplanar common-drain oscillator circuit according to the present invention;

2 is a plan view of an alternative embodiment of a basic coplanar common-drain oscillator circuit.

3 is a plan view of a pair of devices connected to a common-drain oscillator coplanar circuit array in accordance with the invention.

4 illustrates an embodiment of a combination cell oscillator circuit array 50 in accordance with the present invention.

5 is an optional example diagram of a coplanar common-drain oscillator array in accordance with the present invention.

6 is a diagram of another embodiment of a coplanar common-drain oscillator array in accordance with the present invention.

7 illustrates an embodiment of a common-drain oscillator circuit array in accordance with the present invention.

8 illustrates an embodiment of a common-drain oscillator circuit array in accordance with the present invention.

FIG. 9 is a circuit diagram of the gate-drain resonator circuit of FIG. 10. FIG.

10 is a plan view of a capacitor coplanar cavity resonator of a common-drain oscillator embodiment in accordance with the present invention.

11 is a diagram of a dual resonator embodiment of a common drain capacitor coplanar cavity resonator oscillator in accordance with the present invention.

The coplanar common-drain oscillator circuit structure of the present invention greatly reduces the eddy current inductance and capacitance associated with the reverse lines of the gate-drain and source-drain circuits. Given a particular three-terminal device form, the present invention produces oscillators that operate at higher frequencies with lower phase noise and wider tuning range than previous oscillators.

The first embodiment of the present invention is a single three-terminal flip-chip active element connected to a planar substrate. Resonance circuits (resonators) having first and second coplanar conductors are formed on the substrate. The first and second conductors are respectively connected to the gate (control) terminal and the drain (inverting) terminal by flip-chip bonds to the first and second adjacent ends in the connection region. Feedback circuits having third and fourth coplanar conductors are formed over the substrate. The third and fourth conductors are respectively connected to the source terminal and the common drain terminal by different flip-chip bonds to the third and fourth adjacent ends in the connection region. The first and third conductors are disposed on one side of the second and fourth conductors connected to the pain drain.

The second embodiment of the basic oscillator has first (gate), third (source) coplanar conductors disposed on opposite sides of the coplanar second and fourth conductors connected to a common drain.

The first and second conductors of both embodiments form part of the resonator connected to the gate / drain element terminals. The third and fourth conductors of both embodiments form part of a feedback circuit connected to the source / drain element terminals. In both examples, there is a minimum of vortex inductance and capacitance associated with connecting the resonance and feedback circuits to the gate / drain and source / drain terminal pairs.

A large oscillator can be assembled by duplicating a copy of the primary oscillator and joining the copies together on the adjacent side. FETs with large active gate widths are important for increasing output power and reducing phase noise. Impedance matching and power combinations are provided by combining the fundamental resonance and feedback circuits into a planar circuit coupling array on a substrate that is connected to a corresponding array of three-terminal flip-chip elements.

One embodiment of the invention is an array of flip-chip bonded common-drain FETs having source and gate electrodes of adjacent pair elements. Adjacent pairs of source and gate electrodes are connected apart from the common source and gate terminals on the opposite side of the array. Drain electrodes of the connected pair are disposed on opposite sides of the adjacent pair. The source and gate connection element pairs may be arranged in a linear array, each pair having one or more drain electrodes connected to device terminals common to the drain electrodes of adjacent pairs.

A combination circuit resonator and a feedback coplanar circuit are formed with a plurality of conductor terminals on an insulating substrate. Each combined resonator and feedback circuit may be constructed of multiple adjacent interconnect cells. The cells may be copied to each other or may be modified from a cell to an adjacent cell. The term cell means one of a number of interconnect subcircuit structures, including coplanar patterns formed on a substrate for this discussion.

Each cell of each coplanar circuit may have a single conductor terminal between adjacent single or common-drain reverse terminals. Thus each cell of each circuit has a common-drain reverse terminal between the cell and each adjacent cell.

The element terminals and conductor terminals are arranged as follows. That is, when the flip-chip array element terminal is connected to the substrate conductor terminal, the resonator terminal is connected to two corresponding gate / drain terminals. The feedback terminal of the corresponding feedback cell is connected to the corresponding source / drain terminal of each pair. The common-drain reverse terminals of the resonator and feedback cell are respectively connected to the common drain of the device pair.

Therefore, the resonator and feedback circuit cells of the individual device pairs can be arranged for impedance matching, power combination, or separation in the resonator or feedback circuit. Dividing the FET into small complex pairs that are connected to this combination circuit allows for high frequency performance. This is because the dimensions of the interconnect element pairs are smaller and therefore have smaller element-level vortex capacitances and inductances.

A common drain or common signal reverse line between adjacent cells acts as part of the impedance matching network for each pair of devices, providing the advantage of minimizing stray eddy current inductance and capacitance.

Specific examples of the invention are described in which common-drain terminals between adjacent pairs are separated or connected by common coplanar ground segments to substrates such as resonators and feedback circuits.

An example of a resonator and feedback circuit is described which may omit the connection to one common-drain terminal to form an associated resonator and feedback function having a different number of active pairs.

One embodiment of the common-drain oscillator of the present invention includes a gate resonator cell having an intertwined capacitor. A particular embodiment of one gate resonator of the present invention includes a coplanar frame that can be compared to a three dimensional cavity resonator. The term planar cavity or coplanar cavity is used herein as the two-dimensional counterpart of three-dimensional cavities well known in the field of high frequency oscillators. The coplanar frame forms a hole comprising a coplanar capacitor formed of elongated conductor segments arranged in two sets that are intertwined and charged together. One set of adjacent ends is individually connected to a separate input signal control terminal. Each input signal control terminal connects to a gate (controlling) electrode of adjacent FET pairs of the FET composite array. Each pair of source (controlled) electrodes of this gate connection FET is connected to one or more of the feedback terminals of the combination source-drain circuit.

Gate-source pairs connected to the device are arranged in an array as follows. That is, the drain (controlled) electrode of each pair of elements is offset from the pair to the opposite side perpendicular to the pair of gate-source terminals. The drain electrodes of the element adjacent pairs are connected to a common element drain terminal. Coplanar common-drain connection segments connect all common drain terminals. The drain segment is part of the coplanar cavity frame and forms part of the oscillator resonator.

Source terminals are disposed on one side of the common drain segment and gate terminals are disposed on the other side. The source terminal is spaced in parallel with the coplanar source reverse conductor of the source circuit and connected to the coplanar feedback signal conductor. The source reverse conductor is connected to a common-drain segment that forms a controlled impedance function for the source circuit with minimal vortex.

A central coplanar conductor forming an inductive element in the interesting frequency range is connected to one electrode of the tuning varactor and the junction eye of the second set end of the capacitor segment. The other electrode of the varactor is connected to the cavity frame.

Capacitors, inductive elements, varactors, and FET inputs form resonators down to the ground-drain oscillator circuit.

Capacitor segments, FETs, and frames provide resonant coplanar cavities at select frequencies and provide the same signal current separation between the center conductor and the gate electrode. Parallel splitting of signal current from the central conductor by connected charging segments provides improved oscillator output power and phase noise performance for the composite array.

Mode for carrying out the invention

The present invention provides a circuit structure in which a portion of the first conductor is connected to the control input of the active element and located adjacent to another conductor connected to the inverting terminal of the active element. Another portion of the first conductor is located adjacent to another conductor connected to the non-inverting terminal of the active element. This structure 20 is shown in FIG. 1. The circuit structure 20 includes an insulating substrate 22 having a planar surface 22A. The flip-chip integrated circuit 24 forms a connection region 24a indicated by a dotted line in the periphery of the circuit 24. The circuit 24 comprises a three-terminal active element 26 which is a flip-chip bonded to the surface 22a.

These continuous coplanar conductors are formed on the substrate 22a and are connected between the terminals, respectively. The second conductor 32 is disposed adjacent to one side of the first conductor 30. The first conductor 30 extends from the adjacent flip-chip connection 30a of the flip-chip element terminal 38 to the opposite end portions 30b, 30c on the opposite side of the element 26. Conductor 32 extends from adjacent portion 32 to distal portion 32b in the same direction as distal portion 30b of first conductor 30.

Another conductor 34 is disposed adjacent the conductor 30. Conductor 34 extends from proximal portion 34a adjacent to terminal 30a to distal portion 34b in the same direction as distal portion 30c of conductor 30. Adjacent portion 34a is flip-chip bonded to element terminal 40 in connection region 24a. Conductors 32, 34 are disposed on the same side of conductor 30.

Element 26 includes an input signal control electrode 26a, an inverted signal carrier electrode 26b controlled by electrode 26a, and a non-inverted signal carrier electrode 26c controlled by a control signal of electrode 26a. It includes. The inversion electrode 26b carries a signal having an inverse relationship with the control signal of the electrode 26a. Electrodes 26a, 26b, 26c are connected to device terminals 36, 38, 40, and device terminals 36, 38, 40 are flip-chip connected to conductor terminals 32a, 30a, 34a, respectively.

Device 26 may be a GaAs FET, bipolar junction transistor, PBT, HTB, or the like. In the case where element 26 is a FET, input signal control terminal 36 is a gate, inverting terminal 38 is a drain, and non-inverting terminal 40 is a source. GaAs FET is assumed in the following.

The present invention is described on the basis of a control electrode that controls the current in the inverting and non-inverting electrodes. Since the electrical circuit can appear as a voltage or current source using the Thebinin's theorem, explanations are made using voltage control ("Circuits" by Kuh and Paterson, New York, McGraw-Hill Publishers, USA). Synthesis Principles, 1959, 51).

Terminals 36, 38 and 40 are located in the connection area 24a. The outer periphery of the flip-chip device forms an area where flip-chip bonding of the device is made.

The size, shape, and spacing of the coplanar conductors 30, 32, 34 may be arranged to provide control impedance characteristics to the device terminal pairs 36, 38, 38, and 40. Terminal 38 is a common terminal of a coplanar circuit formed by adjacent pairs of conductors 30a, 30b, 32a, 32b, 30a, 30c, 34a, 34b. Therefore, there is a minimum vortex inductance and capacitance associated with the coplanar circuit path from the abutments 30a, 32a to the distal ends 30b, 32b, and from the abutments 30a, 34a to the distal ends 30c, 34b.

Two coplanar conductor circuits 42 and 44 are disposed on the substrate 22 by conventional means such as plating, masking, and etching, or by deposition and patterning. The first circuit 42 is connected to the extensions of the coplanar conductor ends 30b, 32b. The second circuit 44 is connected to the extensions of the coplanar conductor ends 30c, 34b.

In a common drain FET oscillator embodiment of the present invention, circuit 42 may be a resonator circuit, and circuit 44 may be a feedback circuit having a common drain connection to terminal 30a. This provides the minimum eddy inductance and capacitance between element 26 and the two circuits 42, 44 by arranging the coplanar connecting conductors 30, 32, and 30, 34 as part of the coplanar circuit.

Bias connections may be achieved with bond wires or air bridges or other conducting traces having an RF blocking circuit element between the terminal and a suitable power source, although not shown.

Coplanar conductors 30, 32, and 30, 34 are electromagnetically connected to each other to form resonators and feedback circuits 42, 44, respectively. The connected portions 30, 32, and 30, 34 may comprise simple coplanar straight conductors of uniform width and space and combinations thereof. Additional components such as chip capacitors, resistors, or inductors may be included. The additional component is mounted on the substrate 22 and connected by bond wires, air bridges, or other coplanar flip-chip terminal connections.

Drain terminal 38 forms a common RF connection between resonator 42 and feedback circuit 44 at connection point 30a. Conductors 30, 32, and 30, 34 may be randomly short for a given source drain, and gate terminal arrangement, so between resonator circuit 42 and gate-drain connections, and with feedback circuit 44 Minimize eddy inductance between the source and drain connections.

The vortex element of the active element is not shown, but is known to form part of the equivalent circuit of the oscillator. Flip-chip active devices have very low induced vortex elements compared to light lead or wire bond devices. The most important vortex element is the terminal-to-terminal capacitance. That is, capacitance between gate-drain, gate-source, and drain-source.

Since the dimensions of the CPW are adjusted to connect the coplanar circuit and the small active device, the impedance characteristics of the coplanar transmission line or the coplanar waveguide (CPW) can be kept constant. It is a feature of the present invention to separate the three terminals into a resonator pair and a feedback pair and to have a common drain (inverting) terminal. This minimizes eddy current inductance and radiation losses in the connection to three-terminal flip-chip active devices.

2, an alternative embodiment 20 'of the present invention is shown. At this time, the same element is indicated by the same number. Oscillator 20 'includes all elements of the oscillator of FIG. In addition, a segment 30d of the conductor 30 passes between the terminals 36, 40 and is connected to the feedback circuit 44 at the distal end 30c ′ on the side opposite the conductor 34. In this case, there is a minimum vortex inductance in the conductors 30, 32, and 30, 34.

The resonator and feedback circuits 42 and 44 are groups of circuits having coplanar slot line circuits, slot strip circuits, coplanar waveguide circuits, coplanar strip circuits, coplanar transmission line circuits, and other circuits using coplanar conductors. May be selected from, and combinations thereof.

Large array circuits can be built by iterating and combining adjacent mirror images of the basic circuits shown in FIGS. 1 and 2. 3 shows an example of combining a pair of elements as an example of repeating and combining a mirror image copy of the pattern of FIGS. 1 or 2. 4-6 are examples of repeating and combining mirror image copies of the pattern of FIGS. 1 or 2 as described below.

In Fig. 3, another embodiment 20 "of the circuit structure shown in Fig. 1 is shown. An additional three-terminal element 28 is formed in the flip-chip circuit 24. The element 28 is the same. A gate electrode 28a and a source electrode 28c are respectively connected to the control terminal 36 and the non-inverting terminal 40. The inverting or drain electrode 28b of the element 28 has a second common drain flip- Is connected to the chip terminal 39.

The fourth common conductor 30 'has opposing distal ends 30c', 30b 'that are joined at a common adjacent point 30a'. The distal end 30c 'is connected to the feedback circuit 44, and the distal end 30b' is connected to the resonator 42. Conductor 30 'is connected to flip-chip terminal 39 at a common point 30a'. Conductor segment 30d is positioned between gate terminal 36 and source terminal 40 to connect two common drain terminals 38, 39.

The structures of the coplanar circuit terminals, the coplanar conductors, and the element electrodes and terminals can be arranged symmetrically as shown in FIG. The symmetrical structure divides the signal currents and sums equally at the relevant device terminals and conductors. The gate signal current is equally divided from the gate conductor 32 to the gate electrodes 26a and 28a and from the drain and source electrodes 26b, 28b, 26c and 28c to the drain and source conductors 30, 30 'and 34. It is generally necessary to sum the drain and source signals equally, respectively.

The resonator 42 of FIG. 3 may have a structure of a combination circuit including conductors 30, 32, and 30 ′, 32. The feedback circuit 44 of FIG. 3 may have a structure of a combination circuit including conductors 30, 34, and 30 ′, 34. The size, shape, and space of the electrodes of the elements 26, 28 and the conductors 30, 32, 34, 30 'are combined with the circuits 42, 44 to allow direct current flow to the gate, drain, and source electrodes equally. Can be arranged to

Large arrays of devices can be constructed in accordance with the invention. 4, an embodiment of a basic circuit array for forming a common drain oscillator circuit 50 fabricated in accordance with the present invention is shown. Oscillator 50 is shown an embodiment of a basic circuit array to form a high Q gate-drain oscillator circuit 50 that is connected to the gate-drain side of the FET array. Oscillator 50 includes flip-chip integrated circuit 54 with flat surface 56. Circuit 54 includes longitudinal arrays 52 (1, 2, ..., 2j-1, 2j, ... 2J) of adjacent three-terminal active elements of the J-pair. J is an integer selected for the desired output power, magnitude, or phase noise for the oscillator 50 signal, and j is an indicator representing up to 1-J.

For the purposes of this description, an active device can be considered a GaAs FET. Other devices may of course be used. For illustration purposes, another integer indicator I assigns a number to each device and ranges from 1-2J. Each pair j corresponds to an individual element 52I, 52 (I + 1). Where I = 2j-1. Each device I includes a gate or current control electrode 57I, a spaced drain or inverted phase current-carrying electrode 59I, and a spaced source or in-phase current-carrying electrode 64I. The device gate, drain, and source electrode are connected to the gate terminal 58j of the corresponding gate terminal array 58, the drain terminal 62j of the drain terminal array 62, and the source terminal 66j of the source terminal array 66. Each is connected. Gate, source, and drain terminals 58, 62 66 are formed on the surface of the array 56 and described below.

In the description below, the FET array terminals may be coplanar and mounted to corresponding substrate conductor terminals disposed on adjacent planar surfaces such as the mounting surface of the substrate using intermediate weld bumps, balls, and the like.

The boundary of the circuit 54a forms a connection region covering the FET electrode and the FET terminal. The circuit 54a is rectangular with both opposite sides and adjacent portions.

The first pair of elements 52 (1), 52 (2) has respective gate electrodes 57 (1), 57 (2) connected to electrically shared gate terminals 58 (1). The second pair of elements has gate electrodes 57 (3) and 57 (4), respectively, connected to the shared gate terminal 58 (2). The pair of elements 52 (2j-1), 52 (2j) connects the gate electrodes 57 (2j-1), 57 (2j) connected to the shared gate terminal 58 (j) disposed between the elements, respectively. Have each. Gate terminal 58 (j) is arranged as follows. That is, the gate terminal array 58 is disposed in parallel on one side of the FET array 52. Although the output power of the oscillator can be obtained from the gate side or the source side, the gate electrode 57 (I) is regarded as an input electrode. One side of the element array 52 having the gate terminal array 58 is considered the resonator side.

Source electrodes 64 (2j-1) and 64 (2j) of adjacent elements 52 (2j-1) and 52 (2j) are shared source terminals 66 (aligned to form source terminal array 66). j)). The source terminal array 66 is aligned in parallel with the array 52 and is disposed on the bar side or feedback side of the array 52.

The pair of drain electrodes 59 (2j-1), 59 (2j) of the gate and source, respectively, connected to the elements 52 (2j-1), 52 (2j) are offset therefrom between the gate and source electrodes. And positioned toward the opposite end of the element array 52.

The first drain electrode 59 (1) is disposed at one end of the array 52, and the final drain electrode 59 (2J) is disposed at the opposite end of the array 52. The first drain electrode 59 (1) is connected to the first drain terminal 62 (1) disposed at the lower end of the array 52. The final drain electrode 59 (2J) is connected to the final drain terminal 62 (J + 1) disposed at the opposite end of the array 52.

Adjacent pairs j, j + 1 of the elements are the drain electrode 59 (2j) of the second element 52 (2j) of the first pair j, and the first of the second pair j + 1. Drain electrode 59 (2j + 1) of element 52 (2j + 1) is connected adjacent to shared drain terminal 62 (j + 1) between adjacent pairs j, j + 1.

When 1 ≦ k ≦ J + 1, the drain terminals 62 (k) are aligned to form the drain terminal array 62 in parallel with the sides of the array 52. The array 62 of drain terminals is disposed in the connection region 54 between the gate terminal array 58 and the source terminal array 66.

The insulating substrate 82 having the flat surface 86 is formed of the gate conductor segment 90 (j), the drain conductor segment 92k, and the source, which correspond to the J pair of terminal arrays 58, 62, 66 of the device. Three interlaced longitudinal arrays 90, 92, 94 of conductor segment 94 (j), wherein 1 ≦ k ≦ J + 1 and 1 ≦ j ≦ J.

Each drain conductor segment 92 (j) includes a drain conductor terminal 96 (j) located in a connection region 54a centered between opposing distal ends 92a, 92b. Each gate and source conductor segment 90j, 94j has a proximal and distal end, respectively. Each gate and source conductor segment 90j and 94j includes a gate conductor terminal 98j and a source conductor terminal 100j respectively connected to adjacent portions in the connection region 54a, respectively. Gate conductor terminal 98j and source conductor terminal 100 (j) are respectively disposed adjacent between drain conductor terminal 96j and drain conductor terminal 96 (j + 1). The common drain conductor segment 92c (j) may be connected between the shared drain terminals 96 (j) and 96 (j + 1) of each pair j to form a continuous backbone 92c.

Each of the drain conductor terminal 96j, the gate conductor terminal 98j, and the source conductor terminal 100j is located as follows. That is, when the surface 56 of the flip-chip circuit 54 is deep and aligned with the surface 86 of the 82, the gate to the conductive contact between the conductor terminal and the chip terminal (eg, the gate electrode terminal 58j) Conductor terminal 98j, drain conductor terminal 96j to drain electrode terminal 62j, and source conductor terminal 100j to source electrode terminal 66j) may be constructed by conductor interconnection such as conductive bumps or balls. Can be.

Each gate conductor segment 90j and source conductor segment 94j extend oppositely from the gate conductor terminal 98j and the source conductor terminal 100j to their respective ends.

The array of drain conductors 92 are arranged as follows. That is, the terminal portion 92a (j) of the conductor 92j extends in one direction from the center terminal 96j to the gate terminal 90j and the gate terminal 98j. The distal end 92b (j) of the conductor 92j extends in the opposite direction from the center terminal 96j to the source conductor 94j and the source terminal 66j. The gate conductor array 90 and the source conductor array 94 are arranged such that the gate conductor 90j and the source conductor 94j are spaced apart between the drain conductors 92j and 92 (j + 1).

A first coplanar combination resonator circuit 102 is formed over the substrate surface 82 and connected to the gate segment distal end 90j and the drain segment distal end 92a (j). A second coplanar combination feedback circuit 104 is formed over the substrate surface 82 and connected to the distal end 94j and the drain segment distal end 92b (j) of the source segment.

Each gate segment 90j in combination with the drain segment 92j forms part of the combination circuit 102. Each gate segment 90j in combination with drain segment 92 (j + 1) forms another portion of combination circuit 102.

Each source segment 94j in combination with the drain segment 92j forms part of the combination circuit 104. Each source segment 94j in combination with drain segment 92 (j + 1) forms another portion of combination circuit 104.

Each conductor segment of the arrays 90, 92, 94 has a width Wi and a length Li. Between each adjacent pair of segments I, j, there is a space Sij. The dimensions Li, Wi of the individual segments of the arrays 90, 92, 94 and the spatial Sij for the adjacent segments provide the desired impedance inversion (matching), a series of self inductances, coupling inductances and capacitances, and shunt capacitances in the adjacent segments. And may be selected to provide adjacent common drain segments, and may be incorporated into each of the gate-drain 102 or source-drain 104 circuitry.

The gate terminal array 58 is disposed on one side of the drain terminal array 62, and the source terminal array 66 is disposed on the opposite side of the drain terminal array 62. Therefore, conductive access to the common-drain terminal 62j along the substrate surface is available from one of the sides of the drain terminal array 62. This is important for minimizing eddy inductance and capacitance in communication with the impedance reversal circuit connected to the gate-drain or source-drain terminals of the array 52 transistors, or the common-drain terminals connected as part of the tuning common-drain connection. .

Circuits 102 and 104 may be selected from a group of circuits including coplanar slotline circuits, coplanar slotline strip circuits, coplanar waveguide circuits, coplanar strip transmission line circuits, and other circuits using coplanar conductors. It may be a combination thereof.

The dimensions and spacing of the circuits 102 and 104 and the conductor segments can be selected to provide nearly equal amplitude and phase current signals to each gate electrode 57I such that the common-drain connection 62j is effectively in phase.

In the oscillator embodiment 50 of the present invention, the gate resonator circuit 102 determines the frequency and applies input impedance inversion to the gate segment pairs 90j, 92a (j), 90j, 92a (j + 1), respectively. Can be arranged to provide. Source circuit 104 is a drain-source feedback combination circuit that provides feedback and drain-source capacitance increase between source and drain segment pairs 94j, 92j, 94j, 92 (j + 1).

The output power may be derived from the oscillator 50 by inductive and charging connection of one or more conductor segments 90j, 92j, or 94j, or by connecting leads to one or more segments. Parallel or push-pull combinations of the multiple pair elements 52I can be achieved by adding interconnect resistance between adjacent pairs, and by properly combining the Wilkinson combiner and output power of the adjacent pair. FETs with symmetrical source and drain structures, that is, FETs with the same channel dimensions and doping concentrations between the gate and drain as the source and gate, are made of a central terminal pad represented by a source pad located between the gate and drain pad. Is common. To use this FET in an embodiment of the present invention, the voltage bias to the FT actuates the center pad with common-drain instead of common-source.

Some FETs may have an asymmetric source and drain structure. That is, it can have a modified lateral shape or doping profile to increase drain-source voltage breakdown without increasing source resistance. The metal arrangement of such asymmetrical FETs is arranged as follows. That is, the drain electrode may be centrally located with respect to the gate and source terminals so as to be connected to the substrate conductor terminal.

Drain conductor segment 92c (j) may be omitted if it is desired that a reduced connection capacitance occur between the drain and gate or between the drain and source.

The drain backbone provided by the continuous connection of the segments 92c (j) provides a shared conductor to the gate circuit 102 and the source circuit 104 to suppress unwanted vibration modes. One or more intermediate drain conductor segments 92c (j) may be deleted as required by the frequency determining circuits 102 and 104.

By properly combining the signals of the feedback source circuit 104, a push-pull or series output can be obtained. By repeating this combination to build an oscillator with better phase noise, a large array can result.

The common-drain terminal connection 96j, inserted between the gate and source terminal connections 98j and 100j and connected to the drain conductor segment 92j that extends distal with the gate and source conductor segments 90j and 94j, The common-drain transistors are connected from the source-drain and gate-drain connections to the tuning, combining, and matching circuits at the source-drain and gate-drain connections with a minimum loss and delay influenced by the excess-drain conductor segments.

In FIG. 5, oscillator 300, which is a variation of oscillator 50 of FIG. 4, is shown. Oscillator 300 includes integrated circuit chips 302 disposed in adjacent pairs of FET linear arrays. The array 302 has opposite ends forming opposite source-drain sides and gate-drain sides between opposite ends, forming a connection region 302a.

The substrate 301 having the flat surface 301 includes a coplanar gate-drain tuning circuit 305 and a source-drain feedback circuit 307. Gate-drain tuning circuit 305 connects coplanar drain conductors 312 (1) and 312 (3) to shared drain terminals 306 (1), 306 (3) and 306 (5) in connection region 302a. ), 312 (5)). Opposite distal ends 312 (1) a, (2) a, 3 (a), 312 (1) b, (2) b, (3) b) are connections 306 (1), (3), (5) ) In the other direction.

Drain conductors 312 (1), 312 (3), and 312 (5) are separated by gate conductors 314 (1) and 314 (2), respectively. Gate conductors 314 (1) and 314 (2) have abutments and distal ends, each of which has opposite branches 318 (1) a, 318 (1) b, 318 (2) a and 318 (2). is connected to one of the shared ends of b). The other ends of branches 318 (1) a, 318 (1) b, 318 (2) a, and 318 (2) b are shared gate terminals 308 (1), 308 (2), and 308 (3). , 308 (4), respectively. Coplanar tuning element T1 is located between conductors 312 (1) and 314 (1), 312 (3) and 314 (1), 312 (3) and 314 (2), 314 (2) and 312 (5). Is placed. Coplanar drain conductors 312 (1), 312 (3), 312 (5) and gate conductors 314 (1), 314 (2) may form part of a multiconductor coplanar waveguide gate-drain circuit 305. Form.

Drain conductors 312 (1), 312 (3), and 312 (5) extend toward end 312 (1) b, 312 (3) b, 312 (5) b toward source-drain circuit 307 do. Two additional drain conductors 312 (2), 312 (4) are connected at the adjacent ends to additional shared drain terminals 306 (2), 306 (4) in the connection region 302 (a). Conductors 312 (2) and 312 (4) extend in the direction of source circuit 307 to form a portion thereof.

Coplanar source conductors 316 (1,2,3,4) having adjacent and distal ends are coplanar drain conductor pairs 312 (1) and 312 (2), 312 (2) and 312 (3), 312. (3) is spaced apart between 312 (4), 312 (4) and 312 (5), respectively. A spatially spaced tuning element T2 is disposed between the coplanar source conductors 316 (1, 2, 3, 4). Adjacent portions of the source conductors 316 (1, 2, 3, 4) are connected to the shared source terminal 310 (1, 2, 3, 4) in the connection region 302a. The distal end of the source conductor 316 is connected to the shared field metal 320. Coplanar drain conductor 312 (1, 2, 3, 4, 5) and source conductor 316 (1, 2, 3, 4), field metal 320, and tuning element T2 provide multiple coplanar waveguide feedback Part of the circuit 307 is formed.

Coplanar chip array 302 has four pairs of FETs, shared gate-source terminal pairs 308 (1) and 310 (1), 308 (2) and 310 (2), 308 (3) and 310 (3) 308 (4) and 310 (4), respectively, with a shared gate and a shared source flip chip. Each FET pair is an adjacent drain terminal pair 306 (1) and 306 (2), 306 (2) and 306 (3), 306 (3) and 306 (4), 306 (4) and 306 (5) Each has a drain flip chip connected to it.

The coplanar common drain backbone 312 is connected between the coplanar drain conductors 312 (1), 212 (2), 312 (3), 312 (4), and 312 (5). This forms an effective RF common from the oscillator circuit 300.

The output power Po may be connected to a printed trace, lead wire or air bridge, transmission line segment, or the like, and connected to the gate circuit 305 or the source circuit 307.

The dimensions W, L, S of the segments 312, 314, 316, 318 and the tuning elements T1, T2 can be selected to obtain the desired feedback and the desired tuning frequency.

An optional tuning circuit may be used in place of the multiple coplanar waveguide 305 of FIG. 5 in another embodiment of the present invention, such as a single open circuit half wave or quarter wave transmission line or a shorted quarter wave resonator. .

An alternative example of coplanar common drain oscillator 400 according to the present invention is shown in FIG. 6, with elements similar to FIG. 5 being denoted by like numerals.

An adjacent end of the gate conductor 314 terminates in a conducting frame 320 'having an interior surrounding the gate resonator circuit 305', the FET array 302, and the source circuit 307 '.

Longitudinal outer drain conductor segments 312 '(1) a, b) and 312' (3) a, b replace the previous outer drain segment 312 (1), 312 (5) of FIG. . Opposite distal ends of segments 312 '(1) a and 312' (3) a are respectively disposed between the opposite ends of vertical end segment 320'a and the drain terminals 306 (1) and 306 (5), respectively. Connected. Opposite distal ends of segments 312 '(1) b and 312' (2) b are connected between the opposite ends of vertical end segment 320'b and drain terminals 306 (1) and 306 (5), respectively. . This forms a continuous conductive frame 320 '.

Gate conductors 314 (1) and 314 (2) also have distal ends terminating in end segment 320 ′ a. The center drain conductor segment 312 (3) also has a distal end terminating at the end segment 320'a, such that adjacent gate segments 314 (1) and 314 (2) and outer drain segment 312 '(1) ), together with 312 '(3) a), forms a short quarter-wave multiple coplanar waveguide resonator.

The source circuit 307 'is surrounded by the interior of the outer drain conductor segments 312' (1) b, 312 '(3) b, each having a distal end connected to the opposite end of the frame segment 320'b. Source terminals 310 (1), 310 (2) are connected to adjacent portions of source branches 322 (1) a, 322 (1) b, and source terminals 310 (3), 310 (4) Are connected to adjacent portions of the source branches 322a (2) b and 322 (2) b, respectively.

The distal ends of branches 322 (1) a and 322 (1) b are connected together in the vicinity of the source conductor 316 '(1). The distal ends of branch 322 (2) a are connected together adjacent to the source conductor 316'2. Source conductor 316 '(1) is uniformly distributed in the center between outer ground drain segment 312' (1) b and center drain segment 312 '(2). Source conductor 316 '(2) is uniformly distributed in the center between drain segment 312' (3b) and center drain segment 312 '(2).

The source tuning element T2 is linearly spaced between the distal end of the source segments 316 '(1), 316' (2) and the interior of the frame segment 320'b. This forms a source-drain capacitance feedback circuit 307 'in which multiple coplanar waveguides are increased.

The source circuit 307 'may be implemented with shorted coplanar strip transmission lines or shorted or open parallel slot lines, with a length adjusted to provide the desired capacitance between source and drain at the desired oscillation frequency.

In the above example, it can be seen that various structures of the common-drain oscillator circuit can be developed by modifying the gate and source circuits. It is also apparent that additional subsections may be added to the FET array with corresponding circuit subsections to improve phase noise or increase power output.

Connection elements such as T1, T2 can be used to regulate and remove power from the oscillator. The common drain oscillator of the present invention can be operated in push-pull with similar coupling as shown, or it can be operated with in-phase locking the two hemispheres by in-phase coupling, as is well known.

Also included in the invention is an optional coplanar common-drain structure capable of receiving an FET array having an electrode source terminal located between the gate electrode and the drain electrode. Two examples are described with reference to FIGS. 7 and 8.

FIG. 7 shows a portion of a coplanar common drain oscillator 500 having a FET array 501 connected to a conductive pattern substrate 503 as described above. Array 501 forms a connection region 501 thereon. Oscillator 500 includes a coplanar waveguide gate resonator circuit having an open circuit termination.

FET array 501 has source, drain, and gate electrode arrays 510, 512, 514 connected to corresponding array terminals 510 ', 512', 514 '. The array terminals are connected by welding bumps or balls to the source, drain, and gate conductor terminals 510, 512, 514 mounted to the substrate 503.

Source conductor terminals 510 (1, 2, 3) are connected to adjacent portions of parallel coplanar source conductor segments 504 (1, 2, 3), respectively. Segments 504 (1, 2, 3) extend outwardly from array 501 to terminate at open circuit ends of equal length.

Drain conductor terminals 512 (1, 2) are disposed along one side of array 501 and are connected to adjacent coplanar drain conductor segments 506 (1, 2) b. Drain conductor segments 506 (1, 2) b are symmetrically disposed between source segments 504 (1, 2) and 504 (2, 3), respectively. Drain conductor segment 506 (1, 2) b extends in one direction from the array.

Source conductor segment 504 and drain conductor segment 506b form a source-drain multiple coplanar waveguide feedback circuit for oscillator 500. The increase in drain-source capacitance can be provided by microwave integrated circuit (MMIC) chip capacitors or by additional lengths of conductors 504 and 506.

The drain conductor terminals 512 (1, 2) are connected to adjacent ends of the y-type coplanar conductor branches 508a, b in the connection region 501a. Branches 508a, b include branching arms 508 (1,2) a, 508 (1,2) b having distal ends, which extend the other side of the array 501 from the base ends 508a, b. Radiates toward

Branches 508 (1) a and 508 (2) a are disposed between the gate terminal 514 (1) and the source terminal 510 (1), 510 (2), respectively. Branches 508 (2) and 508 b (2) are connected between the gate terminal 514 (2) and the source terminals 510 (2) and 510 (3), respectively. The distal end of branch 508 (1) a is connected to an adjacent portion of the drain conductor segment 506 (1) a in the connection region 501a. The distal end of branch 508 (2) a is connected to an adjacent portion of drain conductor segment 506 (2) a. The distal end of branch 508b (1) is also connected to the distal end of segment 506 (2) a. The distal end of branch 508b (2) is connected to the distal end of drain conductor segment 506a (3).

Gate terminals 514 (1,2) are connected to adjacent portions of parallel gate conductor segments 502 (1,2), respectively. Segment 502 (1,2) extends outward from the other side of the array.

Conductor segment 506 (1, 2) a is disposed around gate conductor segment 502 (1). Conductor segment 506 (2, 3) a is disposed around gate conductor segment 502 (2). Segment 506 (1, 2, 3) a extends from an adjacent end outward from array 501.

Segments 506 (1, 2, 3) a and 502 (1, 2) form part of an open circuit terminated multiple coplanar waveguide gate conditioning circuit for common drain oscillator 500.

Adjacent conductor structures 512, 508, 506 form a common drain connection to the FETs of array 501 and isolate the gate and source terminals from each other. The inverted phase RF signals provided by the drain electrodes of the array 501 FETs are combined to turn to the gate or source circuit at minimum path length and minimum vortex inductance and capacitance, respectively.

The circulating gate-drain currents for each gate-drain conductor pair 506 (1) a, 506 (2) a, 502 (1) are each source-drain conductor pair 504 (1), 512 (1). Have only a short drain conductor segment 508 (1) a, b connecting to the circulating source-drain current for 504 (2).

8, an embodiment of a common drain oscillator circuit 600 in accordance with the present invention is shown. The circuit 600 has an RF short-circuit terminated gate control circuit, with similar numbers to FIG. 7 indicating like parts.

End conductor segment 522 engages the distal end of drain conductor segment 506 (1, 2, 3) a. The end conductor segment 522 is connected to the distal end of the gate conductor segment 502 (1, 2) by an RF connection capacitor 520 (1, 2). Capacitor 520 may be a chip capacitor, thin film capacitor, or the like that may provide a tuning element or zero RF impedance between segment 502 (1, 2) and conductor segment 522.

The drain-source circuit can be a resonator circuit, so that when the drain-source resonator is in the non-resonant state, when the abnormal resonance in parallel resonance, and below the resonance in series resonance, the charge feedback between the source and the drain is Is provided.

Varactor tuning of the common drain oscillator 600 may be accomplished by electromagnetic coupling of the varactors in a gate-source tuning circuit or a source drain tuning circuit.

A wider range of tuning ranges can be achieved by tuning in both the gate-drain circuit and the source-drain circuit. In the common-drain structure of the present invention, low inductance connections from gate or source conductors and common-drain conductors to single or multiple varactors are easily achieved.

Another embodiment of the present invention is described with reference to FIGS. 9 and 10 showing a common drain oscillator having an intertwined capacitor resonator gate circuit. 9 is an equivalent circuit diagram 700 of the oscillator of FIG. 10. Equivalent circuit 702 represents the gate-drain (input) resonator of FIG. Equivalent circuit 704 represents the gate-drain circuit of the FET of FIG. 10, with the source drain feedback circuit connected and is also described below.

C1 is the capacitance of the intertwined coplanar cavity resonator capacitor described below, and Cg is the equivalent capacitance of the equivalent input (gate-drain) combination 704 of the FETs connecting the source-drain circuits (the combination is shown in FIG. 10, shown as 803, 825 (1-5), 826 (1-4), 830 (1-4), 845 (1-4).

The oscillation conditions of the circuit 700 are as follows. That is, the equivalent loss resistance r _e of the gate resonator input circuit 702 consisting of C v, Le q, r _e , and C 1 must be less than the equivalent small signal series negative resistance of the active element input 704.

Cv represents the capacitance of the tuning varactor connected between the gate circuit, the common drain Leq, and the series inductance of the input circuit 702. C1 is the capacitance of the intertwined coplanar cavity resonator capacitor described below, and Cg is the capacitance of the equivalent input 704 of the FET connected to the source-drain circuit of FIG.

If is too small, the capacitance of C1, burrs would be too small tuning range provided by the varactor Cv, Cv is the ground made too small for the tuning range is increased, the increase in the series resistance of the varactor r _i than r _e a further significant Can be. So it prevents the rash.

If the capacitance C1 is too large such that the resonator 702 is connected too tightly to the input 704 to the FET, the noise induced response flow of Cg will cause a large flow at the oscillation frequency causing the excess phase noise.

The Leq of the input circuit 702 should be small enough to allow high frequency operation. If the reverse path to the current circuit of the input circuit is too long, the series inductance will be too large to achieve a high tuning frequency when C1 is in the desired range.

A coplanar entangled capacitor “coplanar cavity” resonator oscillator circuit 800 is shown in FIG. 10. The term coplanar cavity is used synonymously for the existing cavity known as the oscillator. A two-dimensional synonym for regular three-dimensional cavities. The shape of the oscillator is similar to the cross section taken along the axis of the reentrant cylindrical cavity resonator, which has an inner center center projecting from the inner wall as far from the interior of the opposite inner wall.

A varactor 807 is connected to a reentrant post equivalent to the inner wall of the coplanar cavity. Coplanar entangled capacitor 802 and series FET input correspond to a charge gap between equivalent posts and equivalent opposite inner walls. Circuit 800 provides low series resistance and inductance of FET input 702 and provides sufficient series capacitance C1 in common drain oscillator operation.

Coplanar intertwined capacitance coplanar cavity resonator circuit 801 is coupled to one side of FET array 822. The second coplanar circuit 803 is connected to the opposite side of the FET array 822. The common-drain connection of the two circuits 801, 803 is arranged between the circuits 801, 803. By patterning the conductive sheet over the insulating substrate 816 in a conventional manner, circuits 801 and 803 are formed as described above.

Gate circuit 801 includes coplanar entangled capacitor 802 in coplanar conducting frame 806. In this case, the frame includes an internal parameter 804. The source circuit 803 is one of a number of coplanar circuits, such as an open circuit, and is a transmission line, such as an approximately quarter wave long, suitable for providing sufficient charging feedback between the source and drain of the associated FET.

Frame 806 includes two opposite outer legs 808 and 810. The legs 808 and 810 are adjacent the pair of opposite ends with drain terminal common conductor segment 812 and adjacent the opposite ends of the opposite pair with varactor conductor segment 814.

Coplanar capacitor 802 is surrounded by an internal parameter 804 of coplanar conductor frame 806. The parameter 804 forms a coplanar cavity section 804a and a varactor inset section 804b. The parameter 804 portion of the coplanar cavity section 804a takes the form of a slightly elongated hexagon that includes a capacitor 802. The aspect ratio of height to width for the coplanar cavity 804a shown in FIG. 10 is about 1.3: 1. The dimension and aspect ratio of the coplanar cavity section 804a can vary over a very large range. The dimension and aspect ratio of the coplanar cavity section 804a is selected to provide resonance at the appropriate frequency.

Varactor insec section 804b may be rectangular formed in segment 814 to receive tuning varactor 807 having cathode 807a and anode 807b.

In another embodiment of the invention, the resonator may be other than hexagonal, and the varactors do not necessarily have to be inset. The aspect ratio of the resonator coplanar cavity 804a can vary greatly. When spatial constraints are not a big problem, an aspect ratio of approximately 1: 1 is desirable for minimizing losses.

The parameter space of the coplanar cavity section 804a and the parameter space from the capacitor 802 can be selected using a commercial electromagnetic simulation software package. An example is the "IE3D" of Zealand software, which is subject to the desired tuning frequency and constraints of sufficiently low losses.

Coplanar capacitor 802 consists of a set of spaced apart coplanar gate conductor segments 820 (1: 4) intertwined with spaced conductor branch subsets 840a, b, c (1: 4 is index number 1,2 , Then 3, 4). Branches 840a, b, c are connected to a common central conductor input junction 840e in the vicinity of the base conductor segment 840. Conductor 840 has contact 840d at its distal end. Branch 840b is located between branches 840a and c. Contact 840d extends to varactor inset 804b and connects to varactor anode 807b. Conductor 840 and conductor branches 840a, b, c are arranged symmetrically along line AA passing through branch 840b and contact 840d, so that oppositely adjacent gate conductors 820 (1), (2) Branch 840a extends distal to the length L1 between adjacent ends of the sq, and branches 840b distal to the length L2 between adjacent ends of the oppositely adjacent parallel uniform gate conductors 820 (2) and 820 (3). ) Extends, and branch 840c extends to length L3 between adjacent ends of oppositely adjacent parallel uniform gate conductors 820 (3) and 820 (4).

The portion of conductor 840 between junction 840e and contact 840d forms an inductive response connecting element that contributes to the portion of inductance Leq in FIG. 10 in the interesting frequency range.

Adjacent branch 840 and conductors such that the signal current of the central conductor 840 is equally divided by the charging and electromagnetic connection to the individual gate electrodes 832 (1,2) a, 832 (1,2) b. Expanded dimensions L1, L2, L3 and spaces between 820 are arranged. The choice of space and dimensions for interesting frequency ranges can be made using commercially available electromagnetic simulation tools.

At the adjacent ends of the coplanar gate conductor segments 820 (1: 4) are formed coplanar gate conductor terminals 818 (1: 4) spaced apart. 1: 4 indicates the order of index numbers 1,2,3,4. Terminals 818 (1: 4) are connected to FET gate terminals 818 '(1: 4) of the FET array 822, respectively.

Spatially spaced coplanar common drain conductor terminals 824 (1: 5) are formed in coplanar common-drain terminal common conductor segments 812. Terminal 824 (1: 5) is coupled to the simultaneous FET common drain terminal 824 '(1: 5) in FET array 822. The FET common drain terminal 824 '(1: 5) has a drain electrode 828 (1: 1 in 1, 2 in 2, 3, 3 in 4, 5, 4 in 6, 7, 5 through 8). 8)). In this case, the first index is a drain terminal index number and the second index is a drain electrode index number.

FET array 822 includes two C-type FET gate metallization segments 832a, b. The segments 832a and b extend to connect the gate fingers that control the current of the drain electrodes 828 (1,2), 828 (3,4), 828 (5,6), 828 (7,8). Arms 832 (1,2) a and 832 (1,2) b.

The signals from drain electrode 828 are combined by common connection through common drain segment 812.

In the FET array 822 are formed in the source conductor segment 830 (1: 4) to connect to the FET source terminal 826 (1: 4).

A varactor electrode connector layer 842 is disposed in the inset 804b and is connected to the redundant conductor tab 809 from the inset section 804b parameter of the frame 806. The tuning voltage is applied to the varactor anode 807a by an RF choke 844 coupled to the variable power supply.

Coplanar source circuitry 803 is coupled to source terminal 826 to provide adequate source-drain feedback to the FET as needed. Circuit 803 may be a combination circuit connected to the FET by multiple source conductor segments 845 (1: 4) between adjacent drain segments 825 (1: 5).

The entangled capacitor 802 of the present invention adds an optimum amount of input series capacitance with minimum vortex series inductance to minimize the deleterious effects of capacitance flow of the FET at the operating frequency of the oscillator circuit. This minimizes the phase noise of the output signal from the oscillator.

In FIG. 9, capacitance Cv corresponds to the capacitance of varactor 807, r _e corresponds to the series resistance of the resonator, -r _i corresponds to the equivalent negative resistance of the FET input at resonance, and Leq is the capacitor. 802, varactor 807, and the inductive component of central conductor leg 840 between branches 840a, b, c and contact 840d, together with its own inductance of frame reverse legs 808, 810. .

The simple nature of the entangled capacitor 802 and the resulting short segment 820 (1: 4), 840a: c provides a minimum eddy current inductance and therefore a higher obtainable tuning frequency for oscillator performance. .

By connecting inductive legs 840 which are connected to parallel multiple conductors 820 (1: 4) with parallel branches 840a, b and c, in many cases, the parallel inductance and the series inductance of the conductors The total length of the conductors is smaller than if it were as a single parallel conductor pair.

It is a further advantage of entangled capacitor 802 to have multiple conductor terminal pads 818 that can be interconnected to corresponding multiple FET terminals to obtain increased power output and low phase noise.

In Fig. 11, a dual resonator embodiment 900 of a common drain entangled capacitor coplanar cavity resonator oscillator in accordance with the present invention is shown.

First and second coplanar cavities 902a and 902b are formed in the coplanar conductor frame 908. Frame 908 is deposited and patterned on the substrate 910 by the previous conventional process. The frame 908 may be circular or rectangular and define two opposite ends 908a, b connected to the vertical opposite sides 908c, d.

The first and second entangled capacitors 904a and b are symmetrically disposed around the center line B in the cavities 902a and b which are symmetrically disposed, respectively.

The cavities 902a and b are formed by the internal parameters 912a and b of the frame 908 surrounding the capacitors 904a and b. The parameters 912a and b are spaced far enough away from the capacitors 904a and b to minimize the harmful charging effect, but are limited enough to achieve high tuning frequencies. The coplanar cavity center conductor 914 has opposite ends 914a, b that are symmetrically arranged around the center line B, the ends 914a, b having the parameters 912a, b of the tuning cavities 902a, b. b) form part.

Intertwined capacitors 904a, b include capacitor conductor segments 917a, b spaced apart from optional gate conductor segments 919a, b, c.

The central capacitor conductor 906a of the first capacitor 904a branches at the junction 916a to the branching capacitor conductor segments 917a and b. Segments 917a and b extend adjacently toward FET array 922 and extend distal towards varactor anode connections 924 and between optional adjacent gate capacitor conductor segments 919a, b and c, respectively. Extend evenly and in parallel.

Gate capacitor conductor segments 919a, b, c extend adjacently toward FET array 922, which is connected to one end of gate conductor terminals 918a, b, c, respectively. Segment 919 extends distal between optional segments 917 and terminates at an open circuit end. Terminals 918a, b, c are connected to gate terminals 918'a, b, c of FETs 920a, b, c, respectively, to half of flip chip FET array 922.

A bias can be provided to the gate of the FET by a connection from a bias power source located at one of the segments 919 to the pad, such as the distal end of the segment 919a. Gate bias cross connection 921 on the chip connects the three terminals 918a, b, c together. Separate connections can be made independently to each segment in exchange for additional pads and bonding wires. Cross connection 921 can help to suppress abnormal mode oscillations between connected FETs.

The intersecting order of segments 917 and gate segments 919 that are chargeably connected at opposite adjoining and distal ends are connected to form an intertwined capacitor structure.

Expanded dimensions and spacing between adjacent branching segments 917 and gate conductor segments 919 allow the signal currents of the central conductors 906a and b to be charged / electromagnetically divided into gate currents of equal magnitude and in phase to each FET. do.

The second capacitor 904b is a mirror image of the capacitor 904a and divides the signal current from the conductor 906b into the FETs 920d, e, f of the array 922 in equal magnitude and phase.

FET source connection 923 consists of a source-drain entangled capacitor feedback circuit structure as described above to add an optimal amount of source-drain feedback capacitance to optimize oscillation in the tuning range.

FET drain terminals 934a, b, c, d of FETs 920a, b, c, d, e, f are provided on opposite sides 908b of frame 908 that form a common drain RF ground at the drain of the FET. Connected. Displacement of the common drain 908b between the gate terminal 918 and the source terminal 923 provides a common point for signal currents common to the gate-drain and gate-source circuits in a controlled manner that provides a minimum of vortex inductance and capacitance. It works to send.

Capacitor conductors 906a and b extend and connect at their ends to contact the flip mounted tuning varactor anode 924. Conductors 906a and b inductively connect capacitors 904a and b through varactor 924 and return to common drain conductor 908b through frames 908 and 914.

In order to obtain a high resonance Q of wide tunability dependent on the negative resistance limit of the FET array 922, the inductance of the resonator 900 should have a minimum distribution capacitance and a minimum conductor resistance. If the coplanar cavity center reverse conductor 914 is too narrow, the resistance contributing to r _e becomes too large. If the conductor 914 is too wide, the distribution capacitance becomes too large. The width of the conductor 914 should be optimized for optimal performance.

Conductive tab 926 extending from one side 908 of frame 908 is connected to conductive electrode layer 930 of varactor 935. An RF choke 932 connected to another varactor electrode layer 924 provides a bias voltage to tune the varactor from an external power source.

In FIG. 11, the dual resonator 900 functions similar to the single resonator of FIG. 10. However, the gate current of the FET is split into two parallel in-phase paths above a portion of the resonator 900 between the varactor 924 and the FET array 922. That is, the two capacitors 904a and b are separated by the conductors 906a and b, and are returned by the coplanar cavity frame 908 and the coplanar cavity center conductor 914.

The coplanar common drain entangled capacitor dual coplanar cavity oscillator of the present invention using a high pseudomorphic electron flow transistor (PHEMT) has a phase noise of about 76 dBc per Hz or more at a frequency of 100KHz, which is spaced from the center frequency of the oscillation. A tuning range of more than 2 GHz can be obtained at a center frequency of about 40 GHz. The PHEMT has a gate length of about 0.15 microns and a total gate length of about 900 microns. The PHEMT is divided into six cells with two gate fingers per cell, each cell having a unique gate pad and a unique source pad, and the source / drain has a series of seven pads. One source pad is located between each pair of cells, and one source pad is located at each end of the array. The source, drain, and gate pads have a sufficiently large structure at a flip chip boundary of about 2 millimeters in diameter.

The PHEMT was combined with a resonator controlled by an electrostatic barrier varactor for oscillator formation as described in recent application S / N 08 / 555,777, which is incorporated herein by reference.

In alternative embodiments of the invention, coplanar entangled capacitors 904a, b and coplanar cavity 908 may be located on the surface of FET array 922 with proper conductor coating and patterning capabilities. Placing the capacitor 904 and coplanar cavity 908 on the surface of the GaAs FET entanglement circuit results in a small oscillator circuit at the same or higher operating frequency. The improved performance is due to the high dielectric constant of GaAs and due to the low vortex of the resulting capacitor when patterned on the chip with the same bond connection between the FET and the capacitor / plane cavity.

Capacitors 904a and b may also be implemented by metal insulator-metal (MIM) instead of intertwined circuits. The source-drain capacitor can be located on the surface of the FET chip and can be made of MIM capacitor. Other flip mount components, such as inductors, capacitors, multiple diodes, and the like, may be mounted on the substrate to implement optional oscillators in accordance with the present invention.

Other active elements can be used in alternative embodiments of the invention. Examples include bipolar transistors, heterojunction transistors, field effect transistors, bipolar transistors, resonant tunneling transistors, real space transition devices, permeable base transistors, solid state triodes, vacuum triodes, control avalanche triode elements, and There is a superconducting triode device. Two terminal elements, such as a gun diode and a tunnel diode, can be used in embodiments of the present invention without a feedback circuit.

In accordance with the present invention, it should be appreciated that the invention as disclosed is for the purpose of description and not of limitation. It may be possible to include or exclude various elements within the spirit and scope of the invention, or to modify the method, size, shape, appearance of the various elements of the invention. Therefore, the invention should be limited only by the claims appended hereto.

Claims (20)

Millimeter-wave and microwave circuit structures, The structure includes an insulating substrate surface 22a, first, second, third coplanar conductors 32, 34, 30, and one or more active elements 26, The insulating substrate surface 22a has a connection region 24a, The coplanar conductors 32, 34, 30 are mounted on the surface, each conductor having adjacent portions 32a, 34a, 30a extending into the connection area, and the first, second conductors 32, 34 are connected. The third conductor 30 has a distal end 34b extending in the other direction from the region, and the third conductor 30 extends adjacent the distal end 32b of the first conductor and the distal end 34b of the second conductor. Has a second end portion 30c extending adjacent to), the first and second end portions 30b, 30c of the third conductor are isolated from the ground, and The active element 26 includes an input signal control terminal 36, an inverted output signal-carrying terminal 38, and a non-inverted output signal carrying terminal 40, and an output signal according to the input signal of the input signal control terminal. The signal of the carrying terminal is influenced, and the active element is the input signal control terminal 36 connected to the first conductor 32, the non-inverted output signal carrying terminal 40 connected to the second conductor 34, and the third Millimeter-wave and microwave circuit structure, characterized in that it is located in the connection area with an inverted output signal carrying terminal (38) connected to the conductor (30). 2. Millimeter-wave and microwave circuit structure according to claim 1, characterized in that the first conductor (32) and the second conductor (34) are disposed on one side of the third conductor (30). 2. The first conductor 32 and the second conductor 34 are disposed on opposite sides of the third conductor 30, and the third conductor is between the control terminal 36 and the non-inverting terminal 40. Millimeter-wave and microwave circuit structures characterized by passing in. The method of claim 1, The structure includes a fourth coplanar conductor 30 'and a second active element 28, The fourth coplanar conductor 30 'has a proximal portion 30a' mounted to the surface 22a and extending into the connection region 24a, the fourth conductor extending in a different direction from the connection region. And second end portions 30b 'and 30c', respectively, wherein the fourth conductor is adjacent to the first end portion 30b 'and the second end portion 34b of the second conductor extending adjacent to the end portion 32b of the first conductor. A second end portion 30c 'extending protrudingly, and The second active element 28 includes a second input signal control terminal 36, a second inverted output signal carrying terminal 39, and a second non-inverted output signal carrying terminal 40, and a second output signal. The signal of the carrying terminal depends on the signal of the second input signal control terminal, the second input signal control terminal 36 is connected to the first conductor 32, and the second non-inverted output signal carrying terminal 40 Millimeter-wave and microwave circuit structure, characterized in that it is connected to a second conductor (34), and the second inverted output signal carrying terminal (39) is connected to a fourth conductor (30 '). 5. The third and fourth coplanar conductors (30, 30 ') are connected by another coplanar conductor (30d) passing between the first and second conductors (32, 34). Millimeter-wave and microwave circuit structures. 5. Millimeter-wave and microwave circuit structure according to claim 4, characterized in that the fourth conductor (30 ') and the third conductor (30) are connected. 7. Millimeter-wave and microwave circuit structure according to claim 6, characterized in that the fourth conductor (30 ') is located adjacent to the third conductor (30). 2. Millimeter-wave and microwave circuit structure according to claim 1, characterized in that the distal end (32b) of the first conductor and the distal end (30b) of the third conductor are connected to the resonator circuit (42). 9. Millimeter-wave and microwave circuit structure according to claim 8, characterized in that a part of the first conductor (32) and the distal end of the third conductor (30) consist of part of the tuning circuit (42). 2. Millimeter-wave and microwave circuit structure according to claim 1, characterized in that the distal end of the second conductor (34b) and the distal end of the third conductor (30c) are connected to the feedback circuit (44). 11. Millimeter-wave and microwave circuit structure according to claim 10, characterized in that part of the second conductor (34) and one end (30c) of the third conductor consist of part of the feedback circuit (44). 2. The distal end 32b of the first conductor and the distal end 30b of the third conductor are connected to the tuning circuit 42, and the distal end 34b of the second conductor and the other end 30c of the third conductor. Millimeter-wave and microwave circuit structure, characterized in that is connected to the feedback circuit (44). 13. Millimeter-wave and microwave circuit structure according to claim 12, characterized in that the resonator circuit (42) and the feedback circuit (44) are arranged as if the structure is an oscillator. 14. Millimeter-wave and microwave circuit structure according to any of claims 10, 11, 12, 13, characterized in that the feedback circuit (307) comprises a coplanar capacitor (312, 316). 5. The conductors 30, 32, 34 of claim 4, wherein the conductors 30, 32, 34 connected to the first element 26 are made up of part of the first oscillator circuit and are connected to the second element 28. ) Is a part of the second oscillator circuit, the millimeter-wave and microwave circuit structure. 16. The millimeter-wave and microwave circuit structure of claim 15, wherein the signals of the first and second oscillators are locked so that the oscillators oscillate in phase. 16. The millimeter-wave and microwave circuit structure of claim 15, wherein the first and second oscillator circuits are connected such that the oscillators oscillate in a push-pull fashion. The method of claim 1, wherein the field effect transistor, the dipolar transistor, the dipolar transistor, the heterojunction transistor, the resonance tunneling transistor, the real space transition device, the permeable base transistor, the solid state triode, the vacuum triode, the control avalanche triode Millimeter-wave and microwave circuit structure, characterized in that an active element is selected from the group comprising elements, and superconducting triode elements. 2. The millimeter-wave and microwave circuit structure of claim 1, wherein the circuit is a common drain oscillator (20). 11. A resonator or feedback circuit (42, 44) is selected from the group comprising coplanar slot line circuits, coplanar waveguide circuits, coplanar transmission line circuits, and coplanar feedback circuits. Millimeter-wave and microwave circuit structures.