JP2002513229A - Coplanar oscillation circuit structure - Google Patents

Abstract

(57) Abstract: An oscillator circuit (20) having a flip-chip metallization pattern and a base substrate metallization pattern has a common-drain oscillator interrupted between a source (40) and a gate (36) terminal. Drain (38), defined to provide a reduced parasitic inductance element to the working RF common reference that would otherwise degrade oscillator power and phase noise at high frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to an integrated circuit flip-chip circuit including multiple active devices mounted on a base substrate having a metallization pattern connected to the integrated circuit. More particularly, it relates to a millimeter wave integrated oscillator circuit, and more particularly to a coplanar oscillator circuit structure comprised of a plurality of interconnected repeating cells including a metallized pattern having reduced parasitic coupling to a common terminal end.

[0002]

[Background Art]

Almost all oscillators using three-terminal active devices require a signal path from input to output. The inputs to the three terminal active device oscillator define the input voltage or current phase and two output current carrying terminals. These terminals generally have either in-phase or out-of-phase (inverting) current at low frequencies, in fact, direct current (DC). In the case of a microwave FET, the control input is its gate and the inverted output is its drain. In large common source FETs, which are commonly used to provide significant output power, the gate terminal is
Typically, it is connected to a circuit having a return path extending over a significant distance before returning to connect to the drain (inverting) terminal. Any parasitic inductance or capacitance associated with the current path connected to the gate and the inverting terminal is:
It can limit the achievable oscillator frequency response.

[0003] Prior art oscillators have used wire bonds to connect active devices to resonators and feedback circuits defined on a substrate. At millimeter frequencies, even the shortest wire bond can be 1/10 of the wavelength. This acts like a loop with a relatively high parasitic inductance because the wire bonds are spaced relatively far away from the conductor or conductors carrying the return current. This type of loop can introduce unacceptable radiation losses.

[0004] Leaded devices typically have leads with a center distance of 600 to 2500 micrometers. The leads of these devices also pass through glass, metal or ceramic or plastics seals, which produce losses at microwave frequencies. It is advantageous to eliminate leaded devices and wire bonds to reduce losses and parasitic inductance. Flip chips or bump bonded chips have extremely low and uniform parasitic inductance.

[0005] Other circuit structures according to the prior art use a substrate on which an associated stripline or microstrip conductor resonance and feedback circuit to be connected to an active three-terminal device is defined. Microstrip circuits typically have extra dielectric loss and magnetic energy (ie, parasitics) stored in the field between the signal lines on one side of the substrate and a ground plane on the other side of the substrate. Inductance). For high frequency oscillators, it is advantageous to eliminate the microstrip circuit. In a coplanar circuit, the dielectric loss is generally low because the field loss combines with the dielectric loss, and the radiation loss is low because the field is concentrated between more closely spaced intervals.

[0006] Common drain circuitry is often used in high frequency circuits because it provides improved gain-frequency characteristics. Parasitic inductance and capacitance in the circuit path associated with the common terminal of the FET oscillator will affect the large delay and inductance associated with the gate-drain circuit. This creates a frequency limit due to delay and inductance. Losses in the current path connected to the common terminal can also result in excessive phase noise.

[0007] Due to the fact that on the one hand noise is statistically coupled, on the other hand the radiation-fixed signals from one FET array element are coherently coupled, the oscillator has a small It is known that large FET devices constituted by an array of FET devices provide lower phase noise than small FET devices generate alone. However, assembling a larger device from an array of small FETs can result in a relatively long signal path to the device terminals. The longer the path, the higher the parasitic inductance, the higher the radiation losses, and the less the benefits of a larger structure.

In the combined circuit structure, the individual devices of the integrated circuit device array are connected to one or more subsets by tuning or impedance matching circuits, respectively, for impedance matching or power coupling, It is known to combine input and / or output signals. An example of a subset of connected repetitive circuits within one circuit is described in U.S. Patent No. 5,623,231 issued to Mohwinkel et al. And incorporated herein by reference.

Mohwinkel et al. Show a common source microwave amplifier chip with a plurality of FETs and a plurality of associated terminals located at selected locations on a common surface of the chip. The related circuit is formed on a basic substrate having a plurality of terminals corresponding to device terminals on a chip. The input and output signal lines on the board are connected to associated terminals having a plurality of combined input and output lines.

[0010] Mohwinkel et al. Show a common source amplifier with signal inputs from a combinational circuit connected to the gate terminals of a plurality of FET pairs. The signal outputs from the drain terminals of the FET pair are combined on the output signal line. If a metallization pattern is connected from drain to gate to make an oscillator of this type of circuit, the pattern could have a very long path.

An example of a common drain microwave circuit is disclosed in US Pat. No. 413, issued to Wade.
No. 5,168. Wade indicates a common drain FET circuit having source and gate connections to related circuits on a nearby substrate. Drain connections are made to the large heat sink posts that are neither part of, nor flush with, the metallization of the source and gate circuits. The extended return path of the current flowing from the gate to the drain and from the source to the drain results in considerable series inductance and shunt capacitance.

In summary, conventional large common source devices address the problems associated with losses and parasitic inductances associated with physically large layouts that require connecting resonators and feedback circuits to input and output terminals. Have. In conventional common drain circuits as well, the physical layout is characterized by long signal paths for current returning from the gate to the drain and from the source to the drain.

Prior art millimeter or microwave planar circuits exhibit undesired bond wires and / or microstrip radiation losses associated with the inductance and capacitance of long RF connections in gate-drain and source-drain circuits. It is an advantage to have a low parasitic common drain circuit structure that can be used to create oscillators with shorter connections and lower parasitics.

[0014]

DISCLOSURE OF THE INVENTION

The coplanar common drain oscillation circuit structure of the present invention provides significantly reduced parasitic inductance and capacitance associated with the return lines of the gate-drain and source-drain circuits. Given the determination of a particular three-terminal device type, the present invention allows the construction of oscillators that operate at higher frequencies with a wider voltage tuning range and lower phase noise than previously realized oscillators.

A first embodiment of the present invention is a basic, single-terminal flip-chip active device bonded to a planar substrate. A resonance circuit (resonator) including the first and second coplanar conductors is formed on a substrate. The first and second conductors are respectively coupled to a gate (control) terminal and a drain (inverted) terminal by flip chip bonding to respective first and second proximal ends in the connection region. A feedback circuit having third and fourth coplanar conductors is also formed on the substrate. The third and fourth conductors are connected to a source (non-inverting) terminal and a common drain terminal, respectively, by flip chip bonding to respective third and fourth proximal ends in the connection region. The first and third conductors are disposed on one side of the second conductor and a fourth conductor joined to the common drain.

A second embodiment of the basic oscillator comprises first (gate) and third (source) coplanar conductors located opposite the coplanar and fourth conductors joined to a common drain.

The first and second conductors of both embodiments form part of a resonator coupled to the gate / drain device terminals. The third and fourth conductors of both embodiments form part of a feedback circuit coupled to the source / drain device terminals. In both cases, there is a minimum parasitic inductance and capacitance associated with coupling the resonant and feedback circuits to the respective gate / drain and source / drain terminal pairs.

Larger oscillators can be assembled by copy iteration and mirroring of the basic oscillator and coupling of these copies to adjacent sides. FETs with large active gate widths are important to increase output power and reduce phase noise. Impedance matching and power coupling are provided by combining the basic resonance and feedback circuitry with a coupled array of coplanar circuits on a substrate that is connected to a corresponding array of three terminal flip chip devices.

One embodiment of the present invention is an array of flip-chip bonded common drain FETs with adjacent pairs of source and gate electrodes of the device. Adjacent pairs of source and gate electrodes are connected to spaced common source and gate terminals, respectively, on opposite sides of the array. The electrodes of the connected pair of drains are located on opposite sides of an adjacent pair. The pairs of source and gate connected devices can be arranged as a linear array with each pair having at least one drain electrode connected to a device terminal common to an adjacent pair of drain electrodes.

The combinational circuit resonator and the feedback (gate / drain and source / drain) coplanar circuits are formed on an insulating substrate, each having a plurality of conductor terminals. Each combination resonator and feedback circuit can be assembled with several adjacent interconnect cells. The cells may be duplicates or repeats of each other, or may be modified from cells to neighboring cells. In this discussion, the term cell refers to one of a number of interconnected sub-circuit structures that include a coplanar pattern formed on a substrate.

Each cell of each coplanar circuit has one between an adjacent signal or a common drain return terminal.
It is also possible to provide one signal conductor terminal. Thus, each cell of each circuit has a common drain return terminal between it and each adjacent cell.

The device terminals and the conductor terminals are arranged such that the resonator terminals are connected to two corresponding gate / drain terminals when the flip-chip array device terminals are joined to the substrate conductor terminals. The feedback terminals of the corresponding feedback cells are connected to the corresponding source / drain terminals of each pair. The common drain return terminals of the resonator and the feedback cell are connected to respective common drains of respective device pairs.

Thus, the resonators of the individual device pair and the cells of the feedback circuit can be arranged for impedance matching or power coupling or power splitting purposes in either the resonator or the feedback circuit. Splitting the FETs into smaller composite pairs connected to such a combinational circuit may require higher frequencies because the dimensions of the interconnected device pairs are smaller and, therefore, the parasitic capacitance and inductance at the device level are lower. Enable performance capabilities.

In this situation, the common drain or common return line between adjacent cells acts as part of the impedance matching network for each device pair, providing the benefits of stray parasitic inductance and capacitance minimization.

A particular example of the present invention is shown in which the common drain terminal between adjacent pairs is separated or connected by a common coplanar ground segment on the same substrate as the resonator and the feedback circuit.

There are also examples of associated resonators with different numbers of active pairs and resonators and feedback circuits which allow the connection to one or more common drain terminals to be alternately omitted to form a feedback function. Is shown.

One embodiment of the common drain oscillator of the present invention includes a gate resonator cell with intricate capacitors. One particular embodiment of one gate resonator cell of the present invention includes a coplanar frame that allows comparison with a three-dimensional cavity resonator. The term flat cavity or coplanar cavity is used herein as a two-dimensional analog of a three-dimensional cavity well known in the high frequency oscillator art. The coplanar frame defines an opening (a coplanar analog to a three-dimensional cavity) that houses a coplanar capacitor formed by spaced apart elongated conductor segments arranged as two intricate capacitively coupled sets. I do. One set of proximal ends is individually connected to a separate input signal control terminal. Each input signal control terminal connects to the gate (ie, controlling) electrode of one adjacent FET pair in the composite array of FTTs. The source (ie, controlled) electrode of each pair of such gated FETs is coupled to at least one of the feedback terminals of the associated source-drain circuit.

The pair of gate and source connected devices is such that the drain (ie, controlled) electrode of each device in the pair is offset in the opposite direction from the pair and the gate and source terminals of the pair are It is arranged and arranged as an array that is generally orthogonal. The drain electrodes of adjacent pairs of devices are connected to a common device drain terminal between them. The coplanar common drain connection segment connects all common drain terminals. Thus, the drain segment is part of the coplanar cavity frame and forms part of the oscillator resonator.

The source terminal is located on one side of the common drain segment, and the gate terminal is located on the other side. The source terminal is connected to a coplanar feedback signal conductor that is parallel to and spaced from the coplanar source return conductor of the source circuit. The source return conductor is connected to a common drain segment that forms a controlled impedance function for the source circuit with minimal parasitic elements.

The central coplanar conductor forming the inductive element in the frequency range in question is connected between the junction of the distal end of the second set of capacitor segments and one electrode of the tuning varactor. The other electrode of the varactor is connected to the cavity frame.

Thus, the capacitors, inductive elements, varactors, and FET inputs form a resonator to a grounded drain oscillator circuit.

The capacitor segments, FETs, and frame are configured to provide a resonant coplanar cavity at a selected frequency, and are further configured to provide an equally divided signal current between the center conductor and the gate electrode. Is done. The signal current split in parallel from the center conductor by the coupled capacitive segments provides improved oscillator output power and phase noise performance for the arrangement.

[0033]

[Mode of the Invention]

The present invention provides a circuit structure in which one portion of a first conductor is connected to a control input of an active device and is located adjacent to another conductor connected to an inverting terminal of the active device. Another portion of the first conductor is located adjacent to another conductor connected to the non-inverting terminal of the active device. This type of structure is shown generally at 20 in FIG. The circuit structure 20 includes an insulating substrate 22 having a flat surface 22a. Flip chip integrated circuit 24 (illustrated as transparent)
Defines a connection region 24a located within the periphery of the circuit 24 and indicated by a dashed line. The circuit 24 includes a three-terminal active device 26 configured to be a flip chip bonded to the surface 22a.

[0034] Three continuous coplanar conductors are formed on surface 22a and connected between the respective terminals. The second conductor 32 is spaced from the first conductor 30 and is disposed adjacent to one side thereof. The first conductor 30 is connected to the flip-chip device terminal 3.
At 8, extending from the proximal flip chip connection 30a to opposite distal ends 30b and 30c on the opposite side of the device 26. The conductor 32 extends from the proximal end 32a to the distal end 32b in the same direction as the distal end 30b of the first conductor 30.

Another conductor 34 is arranged adjacent to the conductor 30. The conductor 34 extends from a proximal end 34a adjacent and spaced from the terminal 30a to a distal end 34b in the same direction as the distal end 30c of the conductor 30. The closer end end 34a is a flip chip bonded to the device terminal 40 in the connection region 24a. Conductor 3
2 and 34 are located on the same side of conductor 30.

The device 26 includes an input signal control electrode 26a, an inverted signal carrying electrode 26b controlled by the electrode 26a, and a non-inverted control signal carrying electrode 26c controlled by a control signal at the electrode 26a. The inversion electrode 26b carries a signal that is inversely related to the control signal of the electrode 26a. The electrodes 26a, 26b, and 26c are connected to device terminals 36, 38, and 40, which are flip chips bonded to the conductor terminals 32a, 30a, and 34a, respectively.

The device 26 includes a GaAs FET, a bipolar junction transistor, a PBT, an HB
T or the like. If the device 26 is a FET, the input signal control terminal 36 is a gate, the inverting terminal 38 is a drain, and the non-inverting terminal end 40 is a source. In the following discussion, it is assumed to be a GaAs FET.

The present invention is described with reference to control electrodes that control current at inverting and non-inverting electrodes. Thevenin's theorem "Principles of circuits"
hesis "(Principles of circuit synthesis) (Kuh and Pederson, page 5)
1, 1959, McGraw-Hilt Book Company, New
This description is equally applicable to voltage control, because, according to York), an electrical circuit can be equivalent whether it is a voltage source or a current source.

The terminals 36, 38, and 40 are located in the connection region 24a. The outline of the flip-chip device defines the area over which the flip-chip bonding of the device can be achieved throughout.

The size, shape, and spacing of the coplanar conductors 30, 32, and 34 can be configured to present controlled impedance characteristics to the device terminal pairs 36, 38, and 38, 40, respectively. is there. Terminal 38 is connected to an adjacent pair of conductors (30a
, 30b), (32a, 32b), and (30a, 30c), (34a, 3
4b) is a common terminal to the coplanar circuit formed by 4b). Thus, there is a minimum parasitic inductance and capacitance associated with the coplanar circuit path from the proximal end 30a, 32a to the distal end 30b, 32b and from 30a, 34a to the distal end 30c, 34b.

The two coplanar conductor circuits 42, 44 are formed on the substrate 22 by conventional means, for example, plating, masking and etching or deposition and patterning. The first circuit 42 includes coplanar conductor ends 30b and 32
b is connected as an extension. The second circuit 44 is connected as an extension of the coplanar conductor ends 30c and 34b.

In the common drain FET oscillator embodiment of the present invention, circuit 42 may be a resonator circuit and circuit 44 may be a feedback circuit with a common drain connection at terminal 30a. This provides minimal parasitic inductance and capacitance between the device 26 and the two circuits 42, 44 by arranging the coplanar connection conductors 30, 32 and 30, 34 as part of the coplanar circuit.

The bias connections are not shown, but can be achieved by bond wires or air bridges or other conductive traces with RF blocking elements between the respective terminals and a suitable power supply.

The coplanar conductors 30, 32 and 30, 34 can be electromagnetically coupled to form respective resonators and feedback circuits 42, 44. The combined 30, 32 and 30, 34 include simple coplanar straight conductors with uniform width and spacing and combinations thereof. For example, chip capacitors, resistors, or inductors, mounted on the substrate 22, may include additional components such as bond wires or air bridges or other coplanar flip chip terminal connections.

The drain terminal 38 forms a common RE connection between the resonator 42 and the feedback circuit 44 at the connection point 30a. The conductors 30, 32 and 30, 34
Arbitrarily short for a given source, drain and gate terminal layout,
Thereby, the parasitic inductance between the resonator circuit 42 and the gate drain connection part and between the feedback circuit 44 and the source drain connection part can be minimized.

Although not shown, the parasitic elements of the active device are known to form part of an equivalent circuit of the oscillator. Flip chip active devices have inherently very low inductive parasitic elements compared to beam lead or wire bond devices. The most important parasitic elements are, for example, terminal-to-terminal capacitances such as gate-drain, gate-source and drain-source, not shown here but well known to those skilled in the art.

Since the dimensions of the CPW can be scaled up or down to connect between the coplanar circuit and the small active components, the impedance characteristics of the coplanar transmission line or coplanar waveguide (CPW) are constant. Can be kept in state. Minimizing parasitic inductance and radiation losses at the connection to the three-terminal flip-chip active device, along with separating the three terminals into a resonator pair and a feedback pair with a common drain (inverting) terminal, together with this characteristic It is.

With reference to FIG. 2, equivalent elements are given the same reference number,
An alternative embodiment of the present invention is indicated by reference numeral 20 '. Oscillator 20 'includes all the elements of the oscillator of FIG.
Passes between terminals 36 and 40 and connects to feedback circuit 44 at distal end 30c opposite conductor 34. Also, in this case, conductors 30, 32 and 30, 34 have minimal parasitic inductance.

The resonator and feedback circuits 42, 44 are from a group of circuits including coplanar slot line circuits, slot strip circuits, coplanar waveguide circuits, coplanar strip circuits, coplanar transmission line circuits, and other circuits using coplanar conductors. It can be elected or elected and combined.

Larger arrays of circuits can be made by copying the basic circuits shown in FIGS. 1 and 2 and joining adjacent mirror images. FIG. 3 shows an example of a combination of device pairs when the pattern of FIG. 1 or 2 is copied and a mirror image is joined, which will be described below. FIGS. 4 to 6 are examples of copying and mirror image copying of the pattern of FIG. 1 or 2 as described below.

Referring to FIG. 3, there is shown another embodiment 20 ″ of the circuit structure shown in FIG. 1 with the same elements numbered with the same reference number. The device 28 includes a gate electrode 28a.
And a source electrode 28c connected to the same control terminal 36 and non-inverting terminal 40, respectively. The inversion or drain electrode 28b of device 28 connects to a second common drain flip chip terminal.

[0052] The fourth common conductor 30 'has opposite distal ends 30c' and 30b 'at a common proximal point 30a. Distal end 30c 'connects to feedback circuit 44,
Distal end 30b 'connects to resonator 42. The conductor 30 'is connected to the flip chip terminal 39 at the common point 30a. Conductor segment 30d includes a gate terminal 36 and a source terminal 40 for joining the two common drain terminals 38,39.
It is also possible to be located between. The topology of the coplanar circuit terminals, coplanar conductors, and device electrodes and terminals can be arranged symmetrically as shown in FIG.

The symmetry of the topology seeks to split and sum the signal current evenly at the relevant device terminals and conductors. This is to equally divide the gate signal current from gate conductor 32 into gate electrodes 26a and 28a, and to separate the drain and source signal currents from drain and source electrodes 26b, 28b and 26c, 28c into drain and source signals. It is generally necessary to evenly join the conductors 30, 30 'and 34 respectively.

The resonator 42 shown in FIG. 3 is constituted by a combination circuit including the conductors 30 and 32 and 30 ′ and 32. The feedback circuit 44 of FIG.
34, and a combination circuit including 30 'and 34. Circuit 42,
44 in combination with conductors 30, 32, 34, 30 'and device 2
The size dimensions, shape, and spacing of the six and twenty-eight electrodes can be determined to allow current to flow evenly to the respective gate, drain, and source electrodes.

Larger arrays of devices can be configured according to the present invention. Referring to FIG. 4, there is shown one embodiment of an array of basic circuits for forming a common drain oscillation circuit 50 in accordance with the present invention. Oscillator 50 has a high Q gate drain resonator 102 circuit connected to the gate-drain side of the FET array. Oscillator 50 includes a flip-chip integrated circuit 54 having a flat surface 56. The circuit 54 has J adjacent 3
A terminal end active device pair includes a longitudinal array 52. Here, each device has 1, 2,. . , 2j-1, 2j,. . . . Add 2J number. J is
For example, for the signal of the oscillator 50, it is an integer selected for required output power, size, or phase noise or an item to be considered in design, and j is an index varying from 1 to J.

For this description, the active device can be considered a GaAs FET. Other devices can be used as well.

For illustrative purposes, another integer index I indicates each device and varies from 1 to 2J. Each pair j corresponds to an individual device 52 (I), 52 (I + 1). Where I
= 2j-1 Deal. Each device I has its own gate or current control electrode 57 (
I), including spaced drain or inverted phase current carrying electrodes 59 (I), and spaced negative rejection source or in-phase current carrying electrodes 64 (I). Each device gate, drain, and source electrode is associated with a corresponding gate terminal 58 (j) of the gate terminal array 58, a drain terminal 62 (j) of the drain terminal array 62,
And, it is connected to the source terminal 66 (j) of the source terminal array 66. Gate,
Source and drain terminals 58, 62 and 66 are defined on the face of array 56 and are described further below.

In the following description, FET array terminals will be referred to as having their array terminals connected to corresponding substrate conductor terminals located on adjacent flat surfaces, such as the mounting plane of the substrate, by intermediate solder bumps, balls, etc. Coplanar is defined as being attachable.

The boundaries of the circuit 54 a define a connection area that houses the FET electrodes and FET terminals. Circuit 54a is generally rectangular with symmetrically facing sides and adjacent ends.

A first pair of devices 52 (1) and 52 (2) has a respective gate electrode 57 (1) connected to an electrically shared gate terminal 58 (1) disposed therebetween. 57
(2). A second pair of devices (not shown) has each gate electrode 57 (3) and 57 connected to an electrically shared gate terminal 58 (2) located therebetween. Each successive pair of devices 52 (2j-1) and 52 (2j) has a respective gate electrode 57 (2j-i) connected to a shared gate terminal 58 (j) located between the respective devices. 57 (2j).

Gate terminals 58 (j) are arranged so that gate terminal array 58 is parallel to one side of FET array 52. Although the output power of the oscillator can be extracted from either the gate side or the source side, generally, the gate electrode 57 (1) is regarded as an input electrode. One side of the device array 52 having the gate terminal 58 is regarded as the resonator side.

The source electrodes 64 (2j-1) and 6 of the adjacent devices 52 (2j-1) and (2j)
4 (2j) is similarly connectable to a shared source terminal 66 (j) arranged to form a source terminal array 66. The source terminal array 66 is arranged in parallel with the array 52 and is arranged on the opposite side of the array 52, that is, on the feedback side.

A pair of the drain electrode 59 (2j-1) and 59 (2j) of each pair of gate and source connected to the devices 52 (2j-1) and 52 (2j) And is positioned toward the opposite end of the device array 52.

The first drain electrode 59 (1) is located at one end of the array 52, and the last drain electrode 59 (2 J) is located at the opposite end of the array 52. The first drain electrode 59 (1) is connected to a first drain terminal 62 (
Connected to 1). The last drain electrode 59 (2J) is connected to the last drain terminal 62 (J + 1) located at the opposite end of the array 52.

The drain electrode 59 (2 j) of the second device 52 (2 j) of the first pair j and the second
The adjacent pair of devices j and j + 1 is connected such that the drain electrode 59 (2j + 1) of the first device 52 (2j + 1) of the pair j + 1 is connected adjacent to the shared drain terminal 62 (j + 1) between the adjacent pair j and j + 1. Spacing is maintained.

The drain terminals 62 (k), 1 <k <J + 1 are arranged to form a drain terminal array 62 parallel to the sides of the array 52. The drain terminal array 62 is disposed in a connection region 54a between the gate terminal array 58 and the source terminal array 66.

The insulating substrate 82 with the flat surface 86 is used to connect the terminal array 58 of the device pair J,
Gate conductor segments 90 (j) corresponding to 62 and 66, drain conductor 9
2 (k) and three intricate longitudinal arrays 90, 92 and 94 of source conductor segments 94 (j). Here, as before, 1 <k <
J + 1 and 1 <j <J.

[0068] Each drain conductor segment 92 (1) generally has opposite distal ends 92a and 92b.
And a drain conductor terminal termination 96 (j) located in the central connection region 54 between the two. Each gate and source source conductor divides 90 (j) and 9
4 (j) have respective proximal and distal ends. Each gate and source conductor 90 (j) and 94 (j) includes a gate conductor terminal 98 (j) and a source conductor terminal 100 (j) connected to a respective proximal end in the connection region 54, respectively.
The respective gate conductor terminals 98 (j) and source conductor terminals 100 (j) are arranged adjacent to between the drain conductor terminals 96 (j) and the drain conductor terminals 96 (j + 1). A common drain conductor segment 92c (j) is connectable between the shared drain terminals 96 (j) and 96 (j + 1) of each pair j to form a continuous spine 92c. J = 1 to J for all device pairs.

The drain conductor terminal 96 (j), the gate conductor terminal 98 (j), and the source conductor terminal 100 (j)
Between the respective conductor terminals and the chip terminal ends (eg, the gate conductor terminal 98 (j) to the gate electrode terminal 58 (j), the drain to the drain electrode terminal 62 (j) The conductor terminal 96 (j) and the source electrode terminal 66
A conductive contact can be made to the source conductor terminal 100 (j) to (j) by a conductor interconnect such as, for example, a conductive bump or a ball (not shown) placed therebetween. , Is arranged.

Each gate conductor segment 90 (j) and source conductor 94 (j) segment has a respective gate conductor terminal 98 (j) and source conductor terminal 100 (j
) To their respective distal ends in a direction away from).

The array of drain conductors 92 comprises a gate conductor 90 (j) and a gate terminal arrangement 9 such that the distal end 92a (j) of the conductor 92 (j) moves away from the central terminal 96 (j).
8 (j) so as to be spaced apart and spaced apart. Conductor 92 (
j) distal end 92b (j) in the opposite direction away from central terminal 96 (j),
It extends in a direction away from the source conductor 94 (j) and the source terminal 66 (j) and adjacent thereto. In the gate conductor array 90 and the source conductor array 94, the gate conductor 90 (j) and the source conductor 94 (j) have the drain conductors 92 (j) and 92 (
j + 1).

A first coplanar combinatorial resonator circuit 102 is formed on the substrate surface 82 and includes a distal end of a gate segment 90 (j) and a distal end of a drain segment 92a.
(J). A second coplanar combination feedback circuit 104 is formed on substrate surface 82 and is connected to the distal end of source segment 94 (j) and the distal end of drain segment 92b (j).

Each gate segment 90 (j) associated with a drain segment 92 (j)
Form part of the combinational circuit 102. Each gate segment 90 (j) combined with drain segment 92 (j + 1) forms another part of combination circuit 102.

Each source segment 94 (j) combined with a drain segment 92 (j)
Form part of the combinational circuit 104. Each source segment 94 (j) combined with the drain segment 92 (1 + 1) forms another part of the combination circuit 104.

The dimensions of each conductor segment of the array arrays 90, 92, 94 are width Wi and length Li. There is an interval Sij between each pair of adjacent segments I, j. The dimensions Li and Wi of the individual segments of the arrays 90, 92, 94 and their respective spacings Sij to adjacent segments are determined by the required impedance transformation (matching), series self-inductance, coupling inductance and capacitance, and adjacent segment and adjacent common drain. It provides shunt capacitance for the segments and is selectable to be incorporated as part of the respective gate drain 102 or source drain 104 circuitry.

The gate terminal array 58 is arranged on one side of the drain terminal array 62, and the source terminal array 66 is arranged on the opposite side of the drain terminal array 62. Thus, conductive access along the surface of the substrate to any common drain terminal 62 (1) is freely available from either side of the drain terminal array 62. This minimizes capacitance and parasitic inductance that conducts with the common drain terminal connected as part of the tuning or impedance conversion circuit common drain connection connected to either the gate drain or source drain terminals of the transistors in the array 52. Is important for

The circuits 102 and 104 are selected from a group of circuits including coplanar slot line circuits, coplanar slot line strip circuits, coplanar waveguide circuits, coplanar strip transmission line circuits, and other circuits that use coplanar conductors, Alternatively, it can be selected and assembled.

The dimensions and spacing of the circuits 102 and 104 and the conductor segments are such that each gate electrode 57 (I) has substantially equal amplitude and phase so that the common drain connection 62 (j) is effectively in phase. Selectable to provide a current signal.

In the oscillator embodiment 50 of the present invention, the gate resonator circuit 102 determines the frequency and the respective gate drain segment pairs 90 (j), 92a (j) and 90 (j), 92a (1 + 1). ) Can be arranged to provide an input impedance transformation. The source circuit 104 includes a drain source feedback combination that provides each source and drain segment pair with feedback between 94 (j), 92 (j) and 94 (j), 92 (1 + 1) and drain source capacitance increase. Circuit.

The output power can be either the conductive segments 90 (j), 92 (j), or 94 (j)
Perform inductive or capacitive or both coupling to one or more of the two or join the leads of one or more segments (not shown)
It can be taken from zero. Multiple device 52 (I) paired side-by-side or push-pull combinations can be activated by adding cross-coupled resistors between adjacent pairs and by properly combining the power of adjacent pairs with a Wilkenson combiner or the like. Can be

FETs with symmetrical source and drain structures, ie, structures having a predetermined channel size and a doping concentration between the source and gate equal to the doping concentration between the gate and the drain, have a gate and drain pad structure. It is typically made with a central terminal pad, such as an intervening source pad. In order to use this type of FET in embodiments of the present invention, the voltage bias on the FET must be changed so that the center pad is operated as a common drain instead of a common source.

Some FETs can have asymmetric source and drain structures.
That is, the lateral geometry and doping profile can be modified to increase the drain-source breakdown voltage without increasing the source resistance. The metal layout (design) in this type of asymmetric FET can be arranged and configured such that the drain electrode is located at the center with respect to the gate and source terminals to be joined to the respective substrate conductor terminals.

If it is desired to reduce the coupling capacitance between the drain and the gate or between the drain and the source, the drain conductor segment 92c (j) can be omitted.

The drain spine, provided by the continuous connection of segments 92 c (j), provides both gate circuit 102 and source circuit 104 with a shared conductor that suppresses unnecessary emission modes. One or more intermediate drain conductor segments 92c (j) can likewise be eliminated by frequency determination circuits 102 and 104 as needed.

A push-pull or serial output is obtained by appropriately combining the signals in the feedback source circuit 104 as is well known in the art. Larger arrays can be constructed by successively duplicating such combinations to make oscillators with better phase noise.

The respective gate and source conductor segments 9 arranged in an interrupt manner between the gate and source terminal connections 98 (j), 100 (j) and equipped according to the invention
0 (j), drain conductor segment 9 extending in the direction away with 94 (j)
The common drain terminal connection 96 (j), which is connected to the common drain conductor segment 2 (j), allows multiple cells of common drain transistors to be connected to the source with minimal loss and delay affected by excess circuit paths along the common drain conductor segment. -Drain and gate-
At the drain connection, connection to a tuning, combination, and matching circuit is enabled.

Referring to FIG. 5, an oscillator 300 that is a variation of the oscillator 50 of FIG. 4 is shown. The oscillator 300 includes an integrated circuit chip 30 arranged as an adjacent linear array of FET pairs.
2 inclusive. Array 302 has an opposite end defining an opposite source-drain side between the gate-drain side and the opposite end, and defines a connection region 302a.

The substrate 301 having the flat surface 301 a is provided with a coplanar gate drain tuning circuit 3.
05 and a source drain feedback circuit 307. Gate-drain tuning circuit 305 is connected to shared drain terminals 306 (1), 30
6 (3) and coplanar drain conductor 312 (1) connected to 306 (5)
, 312 (3) and 312 (5). Opposite distal end 312 (1)
a, (2) a, (3) a, and 312 (1) b, (2) b, (3) b move in different directions away from the contacts 306 (1), (3), (5). Distract.

The drain conductors 312 (1), 312 (2), and 312 (5) are connected to the gate conductor 31.
4 (1) and 314 (2), respectively. Gate conductor 314 (1
), 314 (2) have proximal and distal ends, the proximal end being a shared end of opposite branches 318 (1) a 318 (1) b and 318 (2) a, 318 (2) b, respectively. Coupled to one of the parts. Branches 318 (1) a, 318 (1) b, 31
8 (2) a and the other end of 318 (2) b are shared gate terminals 308 (1).
, 308 (2) and 308 (3), 308 (4). Coplanar tuning element T1 includes conductors 312 (1), 314 (1) and 312 (3
), 314 (1), and 312 (3) 3114 (2) and 314 (2), 312
It is arranged between (5). Coplanar drain conductor 312 (1), 312 (3)
, 312 (5) and gate conductors 314 (1) and 314 (2) form part of a multi-conductor coplanar waveguide gate-drain circuit 305.

The drain conductors 312 (1), 312 (2), 312 (5) have their distal ends 312 (1) b, 312 (3) b, 312 (5) toward the source-drain circuit 307.
) Stretch to b. Two additional drain conductors 312 (2) and 312 (4) at the proximal end have additional shared drain terminals 306 (2) and 306 in connection region 302a.
Connected to (4). Conductors 312 (2) and 312 (4) extend away from a portion of source circuit 307.

The coplanar source conductors 316 (1, 2, 3, 4) having proximal and distal ends are coplanar drain conductor pairs 312 (1), 312 (2) and 312 (2), 312
An interval is maintained between (3) and 312 (3), 312 (4) and 312 (4), 312 (5). The spacing tuning element T2 is a coplanar source conductor 31.
6 (1, 2, 3, 4). Source conductor 316 (1, 2, 3, 4)
Are connected to the shared source terminals 310 (1, 2) in the connection region 302a, respectively.
, 3, 4). The distal end of source conductor 316 is a common field metal 3
20. Coplanar drain conductors 312 (1, 2, 3, 4, 5) and source conductors 316 (1, 2, 3, 4), field metal 320, and tuning element T2 form part of multiple coplanar waveguide feedback circuit 307. I do.

The flat chip array 302 comprises four pairs of FETs, each pair having a shared gate and a respective shared gate-source terminal pair 308 (1), 310 (1) and 308 (
2), 310 (2) and 308 (3), 310 (3) and 308 (4), 310 (4)
) Connected to each other. Each pair of FETs has an adjacent drain terminal pair 306 (1), 306 (2) and 306 (2), 306 (
3) and 306 (3), and 306 (4) and 306 (4), and 306 (5), respectively.

The coplanar common drain spine 312 is a coplanar drain conductor 312 (1)
, 312 (2), 312 (3), 312 (4), and 312 (5).
This forms a common execution RF for the oscillator circuit 300.

The output power Po is decoupled by printed traces, lead wires or air bridges, transmission line segments, etc., coupled to the gate circuit 305 or the source circuit 307.

The segments 312, 314, 316, 318 and the tuning elements T1, T2
Can be chosen to achieve the required feedback and the required tuning frequency.

An alternative tuning circuit is shown in FIG. 5 for another embodiment of the invention, such as a single open circuit half-wave or quarter-wave transmission line or a shortened quarter-wave resonator (Colpitts style). It can be used instead of multiple coplanar waveguide 305.

An alternative example of a coplanar common drain oscillator 400 according to the present invention is shown in FIG.
Here, as in the case of FIG. 5, equivalent elements are given the same reference numerals.

[0098] The proximal end of the gate conductor 314 is connected to the gate resonator circuit 305'PET array 302.
And a conductive frame 320 having an internal structure for accommodating the source circuit 307.

The longitudinal outer drain conductor segments 312 ′ (1) a, b and 312 ′ (
3) a and b are the previous outer drain segments 312 (1) and 312 (5
). Opposite distal ends of segments 312 '(1) a and 312' (3) a connect between the opposite ends of vertical end segment 320'a and drain terminals 306 (1) and 306 (5). . Segments 312 '(1) b and 312' (2
B) connects the opposite end of the vertical end segment 320′b to the drain terminals 306 (1) and 306 (5), respectively. This forms a continuous conductive frame 320.

The gate conductors 314 (1), 314 (2) have a distal end shorted to the end segment 320′a. Also, the central drain conductor segment 312 (3) has a distal end shorted to the end segment 320'a and the adjacent gate segment 3 (3).
14 (1), 314 (2) and outer drain segment 312 ′ (1) a,
And 312 '(3) a to form a shorted 1/4 wavelength multiplexed coplanar waveguide resonator.

The source circuit 307 ′ includes an outer drain conductor segment 312 ′ (1) b with a respective distal end that connects to the opposite end of the frame segment 320′b, and the interior of 312 ′ (3) b. Is stored in. Source terminals 310 (1) and 3
10 (2) is connected to the proximal end 322 (1) b of the source branch 322 (1) a, and the source terminals 310 (3) and 310 (4) are connected to the source branch 322 (1) a.
a (2) b and 322 (2) b, respectively.

The distal end of branch 322 (1) a, 322 (1) b is connected to source conductor 316 ′.
Joined together at the proximal end of (1). Branch 322 (2) a, 322
(2) The distal ends of b are joined together at the proximal end of source conductor 316 '(2). Source conductor 316 '(1) is connected to outer ground drain segment 312' (
1) b and are centrally and evenly spaced between the central drain segments 312 (2). Source conductors 316 '(2) are evenly spaced centrally between drain segment 312' (3) b and center drain segment 312 '(2).

The source tuning element T2 includes source segments 316 ′ (1) and 316 ′ (
The distance between each distal end of 2) and the interior of the frame segment 320'b is maintained and is collinear. This forms a multiple coplanar waveguide enhanced source-drain capacitance feedback circuit 307 '.

[0104] The source circuit 307 'may be a shorted coplanar strip transmission line or a shorted or open and parallel length adjusted to provide the required capacitance between the source and the drain at the required transmission frequency. It can be implemented as a slot line.

From the foregoing examples, it can be seen that various configurations of the common drain oscillation circuit can be developed by modifying the gate and source circuits. It is also apparent that additional subsections can be added to the FET array with corresponding circuit subsections to increase power output and / or improve phase noise.

[0106] Coupling elements such as T1 and T2 can be used for tuning and power removal from the oscillator. The common drain oscillator of the present invention can operate in push-pull with the same coupling as shown here, or, as is well known,
In-phase operation is also possible by injection locking of two half-waves by in-phase coupling.

FET having an electrode source terminal located between a gate electrode and a drain electrode terminal
Alternative coplanar common drain structures that can accommodate the array are also included in the present invention. 2
One example is shown in FIGS.

FIG. 7 shows an F bonded to a conductive patterned substrate 503 as previously described.
5 shows a portion of a coplanar common drain oscillator 500 having an ET array 501.
Array 501 defines a connection region 501 thereon. Oscillator 500 includes a coplanar waveguide gate resonator circuit with open circuit termination, described below.

The FET array 501 has a corresponding array terminal 510 ′, 512 ′, 514 ′ (
Source, drain and gate electrode arrays 510, 51 connected to
2, 514. The array terminals are connected to respective source, drain, and gate conductor terminals 510, 512, 514 attached to the substrate 503 by solder bumps or solder balls.

The source conductor terminals 510 (1, 2, 3) are connected to the proximal ends of the parallel coplanar source conductor segments 504 (1, 2, 3), respectively. Segment 504 (
1,2,3) are arrays 5 to terminate at equal length open circuit distal ends.
Extend outward in one direction away from 01.

The drain conductor terminals 512 (1,2) are located along one side of the array 501 and are connected to the proximal ends of the parallel coplanar drain conductor segments 506 (1,2) b, respectively. The drain conductor segments 506 (1,2) b are symmetrically arranged between the source segments 504 (1,2) and 504 (2,3). Drain conductor segment 506 (1,2) b extends in one direction away from the array.

The source conductor segment 504 and the drain conductor segment 506b form a source-drain multiplexed coplanar waveguide feedback circuit for the oscillator 500. The increase in drain-source capacitance is due to conductors 504 and 506
Additional length can be provided or provided by a microwave integrated circuit (MMIC) chip capacitor, or the like.

The drain conductor terminals 512 (1,2) are coupled to the proximal base ends of the y-shaped coplanar conductor branches 508a, b in the connection region 501a. Branches 508a, b branch arm 508 (1,2) with a distal end that branches away from base end 508a, b in a direction away from the other side of array 501.
A) and 508 (1,2) b.

The branches 508 (1) a and 508 (2) a are located between the gate terminal 514 (1) and the respective source terminals 510 (1) and 510 (2). Branch 5
08 (2) a and 508b (2) are located between the gate terminal 514 (2) and the respective source terminals 510 (2) and 510 (3). Branch 508 (1) a
Is connected to the drain conductor segment 506 (1) in the connection region 501a.
) Join the proximal end of a. The distal end of branch 508 (2) a joins the proximal end of drain conductor segment 506 (2) a. Also, the branch 508b (
The distal end of 1) joins the proximal end of segment 506 (2) a. Branch 5
The distal end of 08b (2) joins the proximal end of drain conductor segment 506a (3).

The gate terminals 514 (1, 2) are respectively connected to the parallel gate conductor segments 502 (1
2) connected to the proximal end. Segment 502 (1,2) extends away from the other side of the array.

The conductor segment 506 (1,2) a is arranged around the gate conductor segment 502 (1). The conductor segment 506 (2,3) a is arranged around the gate conductor segment 502 (2). The segments 506 (1,2,3) a extend away from their proximal ends away from the array 501.

The segments 506 (1,2,3) a and 502 (1,2) form part of an open circuit terminated multiple coplanar waveguide gate tuning circuit with respect to the common drain oscillator 500.

The continuous conductor structures 512, 508, 506 define a common drain connection for the FETs of the array 501 and separate the gate and source terminals from each other. Thus, the inverted phase RF signal provided by the drain electrode of the array 501 FET is intermingled with minimum path length, minimum parasitic inductance, and capacitance for return to the respective gate or source circuit.

Each gate such as 506 (1) a, 506 (2) a and 502 (1)
The circulating gate-drain current for the drain conductor pair is, for example, 504 (1), 5
12 (1) and a short drain conductor segment 508 (1) a that couples to a circulating source-drain current for each source-drain conductor pair, such as 504 (2).
b only.

With reference to FIG. 8, like elements will be designated with like reference numbers as shown in FIG. 7, and RF will include one of the common drain oscillating circuits 600 according to the present invention with a short circuit terminating gate tuning circuit. An embodiment is shown.

The end conductor segment 522 includes the drain conductor segment 506 (1, 2, 3)
Join the distal end of a. The end conductor segment 522 is connected to the RF coupling capacitor 5.
20 (1, 2) is connected to the distal end of the gate conductor segment 502 (1, 2). Capacitor 520 may be a tuning element or a capacitor capable of providing substantially zero RF impedance between the distal end of segment 502 (1, 2) and conductor segment 522, such as a chip capacitor, thin film capacitor, etc. Absent.

Similarly, the drain-source circuit is above resonance for parallel type resonance and below resonance for series type resonance. When the drain-source resonator is not resonating, the capacitive feedback between source and drain is May be implemented in the resonator circuit.

[0123] Varactor tuning of the common drain oscillator 600 may be achieved by electromagnetic coupling of varactors in either the gate-source tuning circuit or the source-drain tuning circuit.

A wider tuning range is achieved by tuning in both the gate-drain circuit and the source-drain circuit, in the common-drain configuration of the present invention from gate or source conductors and common-drain conductors to single or multiple varactors. The low inductance connections are easily made.

Another embodiment of the present invention is illustrated by FIGS. 9 and 10 of a common drain oscillator with intricate capacitor resonator gate circuits. FIG. 9 is an equivalent schematic diagram 700 of the oscillator of FIG. The equivalent circuit 702 is the gate-drain (
Input) represents a resonator. Equivalent circuit 704 represents the gate-drain circuit of the FET of FIG. 10 with the connected source-drain feedback circuit and is described further below.

C1 is the capacitance of the intricate coplanar cavity capacitors described below, and Cg is 803, 525 (1-5), 826 (1
-4), 630 (1-4), and equivalent input (gate-drain) of FET with source-drain circuit connected combinations shown as 645 (1-4)
It is an equivalent capacitance of the combination body 704.

[0127] call condition of the circuit _700, C _v, L eq, _{r e,} and the magnitude of the equivalent loss resistance represented by the _{r e} of composed gate resonator input circuit 702 by the _{C 1} active device ( In this case, the input signal 704 of the FET) is smaller than the small equivalent signal series negative resistance. C _v represents the capacitance of the tuning varactor connected between the gate circuit and the common drain. _Leq is the series inductance of the input circuit 702. C ₁ is the capacitance of the coplanar cavity resonator capacitor convoluted one another as described below, Cg is the source of 10 - is the capacitance of the equivalent input 704 of the FET connected to the drain circuit.

If the capacitance of C ₁ is too small, the tuning range provided by the varactor C _v is too small, or if the C _v is relatively small to increase the tuning range, the varactor increasing the series resistance, the magnitude of r _e r _{i (source} of FIG. 10 - equivalent negative input resistance of the connected FET to drain circuit)
It could even increase, thereby preventing outgoing calls.

If the capacitance of C ₁ is too large, Cg caused by noise will cause resonator 702 to couple too strongly to input 704 to the FET.
Reactance fluctuations will increase the oscillating frequency fluctuations and will result in excessive phase noise.

The L _{eq of the} input circuit 702 must be appropriately low to allow for high frequency operation. If the return path of the current circulating in the input circuit is too long, series inductance, when the C ₁ is within the required range, should too large to achieve high tuning frequency.

Intricate Coplanar Capacitor “Coplanar Cavity” Resonant Oscillator 80
0 is shown in FIG. Here, the term "coplanar cavity" is used as an analog of a conventional cavity known to be used in oscillators. It is a two-dimensional analog of a normal three-dimensional cavity. The shape of the resonator is a cross section cut along the axis of a concave cylindrical cavity resonator having an internal center post (located on-axis) protruding from one inner wall spaced from the inside of the opposite inner wall. Minutes similar.

The varactor 807 connects the equivalent of the concave post to the equivalent of one of the inner walls of the coplanar cavity. Intricate coplanar capacitors 802 arranged in series
And the FET input correspond to the capacitive gap between the equivalent post and the equivalent facing inner wall. Circuit 8
00 provides a low series resistance and inductance to the FET input 702 (see r _e , L _eq , FIG. 9) while at the same time allowing for sufficient series capacitance C ₁ for successful operation of the common drain oscillator. is there.

An intricate coplanar capacitor-coplanar cavity circuit 801 is connected to one side of the FET array 822. The second coplanar circuit 803 has F
It is connected to the opposite side of the ET array 822. A common drain connection to both circuits 801 and 803 (described further below) is located between circuits 801 and 803. As already mentioned, the circuits 801 and 803 are formed by molding a conductive sheet on an insulating substrate 816 in a conventional manner.

Gating circuit 801 includes intricate coplanar capacitors 802 in coplanar conductive frame 606. This frame has an inner circumference 804. The source circuit 803 is one of a number of coplanar circuits, such as an open circuit, approximately a quarter wavelength transmission line, etc., suitable for providing sufficient capacitive feedback between the source and drain of the associated FETs. It does not matter.

The frame 806 contacts the drain terminal common conductor segment 812 at a pair of opposite ends, and the two facing outer legs 808 and the varactor conductor segment 814 at a pair of opposite ends. 810.

The coplanar capacitor 802 is connected to the inner periphery 80 of the coplanar conductive frame 806.
Surrounded by four. Perimeter 804 defines a coplanar cavity section 804a and a varactor insertion section 804b. Coplanar cavity section 804
A portion of the perimeter 804 of a is molded as a slightly elongated hexagon that houses the capacitor 802. The width to height aspect ratio for the coplanar cavity 804a shown in FIG. 10 is about 1.3: 1. The dimensions and aspect ratio of the coplanar cavity section 804a can vary over a considerable range. The dimensions and aspect ratio of coplanar cavity section 804a are selected to produce resonance at the appropriate frequency.

The varactor plug-in section 804b may be generally rectangular or rectangular in shape at a segment 814 for receiving a tuning varactor 807 with a cathode 807a and an anode 807b (not shown).

In another embodiment of the present invention, the resonator may have a shape other than hexagonal (eg, circular, polygonal, etc.), and no varactor need be inserted. The aspect ratio of the resonator coplanar cavity 804a can vary considerably. If space constraints are not an issue, the aspect ratio should be about 1 to minimize losses.
: 1 is desirable.

The dimensions and perimeter of the coplanar cavity section 504a and the capacitor 802
Is adapted to the constraint of the required tuning frequency (i.e., decreases as the frequency increases), and the loss is sufficiently low (i.e., the loss decreases as the size increases), for example, "Zeland Software's". "IE3D""
Selected using a commercial electromagnetic simulation software package such as Zeland Software's "IE3D".

The coplanar capacitor 802 is composed of a pair of spacing coplanar gate conductor segments 820 (1: 4) interleaved with the spacing branch conductors 840a, b, c. (1: 4 indicates the sequence 1, 2, 3, 4 of the index). The branch conductors 840a, b, c are joined at a common center conductor input joint 840e at the proximal end of the base conductor segment 640. Conductor 840 has a contact 840d at the distal end. Branch conductor 840b is arranged between branch conductors 840a and 840c. Contact 840d extends away from varactor plug 804b and connects to varactor anode 807b (not shown). Conductor 840 and branch conductor 84
0a, b, c are lines AA passing through the branch conductor 840b and the contact 840d.
Are symmetrically arranged along. Here, the branch conductor 840a extends in the direction away from the length L1 between the proximal ends of the adjacent gate conductors 820 (1) and 820 (2), and the branch conductor 840b moves away from the length L2. Gate conductors 820 (2) and 820 that face each other and are parallel to each other at equal intervals.
The branch conductor 840c extends between the proximal ends of (3), and the branch conductor 840c faces the adjacent gate conductor 820 facing the length L3 at a generally parallel and uniform distance in a direction away from the length L3.
Distraction between (3) and the proximal end of 820 (4).

The portion of conductor 840 located between junction 840e and contact 840d provides an inductive reactance coupling element that affects a portion of inductance L _eq of FIG. 10 over the entire frequency range of interest. Form.

The dimensions L 1, L 2, L 3 of the extension and the distance between the adjacent branch conductor 840 and the conductor 820 are determined by the signal current in the center conductor 840 due to the capacitive and electromagnetic coupling, and the individual gate electrodes 832 (1, 2) a , And 832 (1, 2) b. The selection of the spacing and dimensions for the frequency range in question can be performed using commercially available electromagnetic simulation tools.

The spaced coplanar gate conductor terminals 818 (1: 4) are defined on the respective proximal ends of the coplanar gate conductor segments 820 (1: 4). The notation 1: 4 indicates the sequence 1, 2, 3, 4 of the index. Terminal 818 (
1: 4) correspond to the respective FET gate terminals 818 ′ (1:
4) (not shown).

The spaced coplanar common drain conductor terminals 824 (1: 5) are defined on the coplanar common drain terminal common conductor segments 812. Terminal 824 (1
: 5) is the matching FET common drain terminal 824 ′ (1:
5) (not shown). The FET common drain terminal 824 '(1: 5) connects to the drain electrode 828 (1: 8) in the following order. That is, 1 becomes 1 and 2 becomes 2
To 3, and 3 to 4 and 5, 4 to 6 and 7, 5 to 8. Here, the first index is a drain terminal index number, and the second index is a drain electrode index number.

The FET array 822 includes drain electrodes 828 (1, 2) and 828 (3,
4) 2 with extension arms 832 (1,2) a and 832 (1,2) b that connect to gate fingers that control the current in 828 (5,6) and 828 (7,8) Includes two C-shaped FET gate metallized segments 832a, b.

Signals from drain electrodes 828 are combined by a common connection via a common drain segment 812.

A spacing coplanar source conductor terminal 826 (1: 4) for bonding to a FET source terminal 826 (1: 4) on FET array 822 is defined on source conductor segment 830 (1: 4). .

A varactor electrode (cathode or anode) connector layer 842 is disposed within the inset 804 b and connects to a conductor tab 809 stacked from around the inset section 604 b of the frame 606.

The tuning voltage is supplied to a varactor anode 807 (not shown) by an RF choke 844 connected to a variable power supply (not shown).

The coplanar source circuit 803 is connected to a source terminal 826 to provide source drain feedback to the FET as needed. Circuit 803 generally includes a multi-source conductor segment 8 between adjacent drain segments 825 (1: 5).
45 (1: 4) may be a combinational circuit connected to the FET.

The intricate capacitor 802 of the present invention adds an optimal amount of input series capacitance with minimal parasitic series inductance to minimize the deleterious effects of intra-FET capacitance variations at the operating frequency of the oscillator circuit. . This minimizes the phase noise of the output signal from the oscillator.

[0152] and referring again to FIG. 9, the capacitance _{C v} (including capacitor 802, the series resistance of the inductor 840e and varactor 807) the capacitance of the varactor 807, the series resistance in the resonator _{r e,} FET in the resonance state input equivalent negative resistance -r _i, and the branch conductors 840a, b, c and the capacitor 802, the inductive component Leq central conductor leg 840 between the contact 840d having the self-inductance of the varactor 807 and the frame return legs 808, 810 Corresponding.

The intricate capacitors 802 and consequently short segments 620 (1:
4) and 840a: c, the compact nature of which minimizes parasitic self-inductance,
In turn, it provides a higher achievable tuning frequency with respect to oscillator performance.

In many cases, the parallel branch conductor and conductor series inductance is smaller than the inductance where the total length of the parallel branch conductor and the conductor corresponds to a single parallel conductor pair capacitively coupled together. This can be shown by joining inductive legs 840 to parallel branch conductors 840a, b, c that are capacitively coupled to parallel multiconductors 820 (1: 4).

Having multiple conductor terminal pads 818 that allow interconnection of corresponding multiple FET terminals to obtain increased power output and reduced phase noise is a further advantage of capacitors 802 intertwined with each other.

Referring to FIG. 11, a dual-resonator embodiment 900 of a common-drain combination capacitor coplanar cavity oscillator according to the present invention is shown.

The first and second coplanar cavities 902 a and 902 b are defined in a coplanar conductive frame 908. As described above, the frame 908 is deposited or patterned on the substrate 910 by a conventional process. The frame 908 can be circular or generally rectangular, with the orthogonal opposite sides 908c, d
To define two opposite ends 908a, b.

The intricate first and second capacitors 904a and 904b are symmetrically arranged around the center line B in the symmetrically arranged cavities 902a and 902b, respectively.

The cavities 902a and 902b correspond to the inner periphery 9 of the frame 908 surrounding the capacitors 904a and 904b.
12a and 12b respectively. The perimeters 912a, b are spaced sufficiently apart from the capacitors 904a, b to minimize deleterious capacitive coupling effects, but the spacing is sufficiently limited to achieve high tuning frequencies. Is done. The coplanar cavity center conductor 914 has opposing edges 9 symmetrically disposed about the center line B.
14a and b. These edges form part of the perimeters 912a, b of the tuning cavities 902a, b.

The interdigitated capacitors 904a and 904b include interleaved capacitor conductor segments 917a, b spaced from the interleaved gate conductor segments 919a, b, c.

[0161] The central capacitor conductor 906a of the first capacitor 904a forks like a branch capacitor conductor segment 917a, b at the junction 916a.
The segments 917a, b extend closer to the FET array 922 and further away from the varactor anode connection 924, generally with respect to the interleaved adjacent gate capacitor conductor segments 919a, b, c. And extend in parallel, and equally spaced between them.

The gate capacitor conductor segments 919a, b, c
It extends in a direction approaching the FET array 922 so as to connect at one end of a, b, and c. Segment 919 includes interleaved segments 917
Between and extend away from each other and terminate at the open circuit end. Terminal 918
a, b, c are the FETs 920 in half of the flip chip FET array 922
Connected to respective gate terminals 918'a, b, c of a, b, c (not shown).

A bias can be supplied to the FET, eg, at the distal end of segment 919a by a connection from a bias power supply (not shown) to a pad located on one of the segments 919. The gate bias cross connection 921a on the chip connects to three terminals 918a, b, c. Independent individual connections to each segment can be made by using additional pads and bonding wires. Also, the cross connection part 92
1a can assist in suppressing abnormal mode transmission between connected FETs.

The interleaved sequence of capacitively coupled segments 917 and gate segments 919 are connected at opposite proximal and distal ends to form an intricate capacitor structure.

The extension dimensions and spacing between adjacent branch segments and the gate conductor segment 919 are such that the current signals in the center conductors 906a, b are capacitive and responsive to gate currents of substantially equal magnitude and phase to each respective FET. It is selected to be electromagnetically split.

The second capacitor 904b is a mirror image of the capacitor 904a, and divides the signal from the conductor 906b to the FETs 920d, e, and f of the array 922 equally in magnitude and phase.

[0167] The FET source connection 923 provides an optimized source-drain capacitor feedback circuit structure (not shown) as described above, such as to optimize transmission over the entire tuning range. Created to add an amount of source-drain feedback capacitance.

The FET drain terminals 934a, b, c of the FETs 920a, b, c, d, e, f
, D are connected to the opposite portion 908b of the frame 908 forming a common-drain RF ground at the drain of the FET. Gate terminal 918 and source terminal 92
Placing the common-drain 908b between the three will direct a common signal current to the gate-drain and gate-source circuits in a controlled manner to provide minimal parasitic inductance and capacitance to the common point. Act on.

The capacitor conductors 906 a, b extend in a direction away from each other and are joined so as to be in contact with the tuned varactor anode 924 installed in the flip. Conductors 906a, b couple to capacitors 904a, b via varactor 924 and
4 to return to the common drain conductor 908b.

To achieve a high resonance Q with wide tunability and meet the negative resistance limit of the FET array 922, the inductance of the resonator 900 must have a minimum distributed capacitance and a minimum conductor resistance. No. If coplanar hollow center return conductor 914 is too narrow, the resistance affecting the r _e is too high. If the conductor 914 is too wide, the distributed capacitance will be too high. The width of conductor 914 must be optimized for best performance.

A conductive tab 926 extending from one side 908 in the frame 908 is connected to the conductive electrode layer 930 of the varactor 935. Another varactor electrode layer 92
The RF choke 932 connected to 4 supplies a varactor adjustment bias voltage from an external power supply (not shown).

Referring to FIG. 11, double resonator 900 includes varactor 924 and FET array 92.
The gate current to the FET over a portion of the resonator 900 between the two is split into two parallel in-phase paths, that is, split by the two conductors 906a, b into two capacitors 904a, b. 10 functions in a manner similar to the single resonator of FIG. 10 except that it is returned by the coplanar cavity frame 908 and the coplanar cavity center conductor 914.

The coplanar common-drain combination capacitor dual coplanar cavity oscillator of the present invention using a virtual high electron mobility transistor (PHEMT: femto) provides about 76 dBc per hertz at 100 kHz excursion from the oscillator center frequency ( The measured results show that it has better phase noise than the carrier (decibel below carrier) and can achieve a tuning range greater than 2 GHz at a center frequency of about 40 GHz. The PHEMT gate length is about 0.15 microns and the total gate width is about 900 microns. The PHEMT is divided into six cells with two gate fingers per cell, each cell has its own gate pad and its own source pad, the source / drain has a series of seven pads, One source pad is located between the cell pairs, and one source pad is located on each end of the array. The source, drain, and gate pads are about 2 mils in diameter and are configured to be large enough for flip chip bounding.

Patent application S / N08 / 55, recently filed and incorporated herein by reference.
This PHEMT was combined with a resonator tuned by an electrostatic barrier varactor to form an oscillator, as described in US Pat.

In an alternative embodiment of the present invention, with appropriate conductor coating and patterning capabilities, the intricate coplanar capacitors 904a, b and coplanar cavity 908 can be located on the surface of the FET array 922. Please pay attention to. Placing the capacitor 904 and the coplanar cavity 908 on the surface of the GaAs FET integrated circuit should result in a smaller oscillator circuit at the same frequency and / or at a higher operating frequency. Improved performance involves the higher dielectric constant of GaAs and the elimination of some junction connections (eg, balls or bumps) between the FET and the capacitor / flat cavity, with the GaAs being patterned on the chip. Sometimes due to the resulting reduction in the parasitics of the capacitor.

The capacitors 904a, b can be realized by a metal insulator-metal (MIM) structure instead of an intricate circuit. Source-drain capacitor is FE
It can also be arranged on a T-chip and / or made as a MIM capacitor. Other flip-mounted components, such as, for example, inductors, capacitors, multiple diodes, etc., can be attached to the substrate to implement an alternative oscillator according to the present invention.

For example, a bipolar transistor, a heterojunction transistor, a field effect transistor, a bipolar transistor, a resonant tunneling transistor, a real space transmission device, a magnetically permeable base transistor, a solid state triode, a vacuum triode, a controlled Other active devices such as electron avalanche triode devices and superconducting triode devices can be used in alternative embodiments of the present invention. For example, it is also contemplated that two-terminal devices, such as Gunn diodes, tunnel diodes, etc., can be used in embodiments of the present invention without feedback circuitry.

It is to be understood that the above description is by way of example only and is not limiting of the disclosed invention. Within the scope and spirit of the present invention, it is possible to modify the size, shape and appearance of the various elements of the present invention, and the manufacturing method, or to include or exclude various elements. It should be understood. Accordingly, the invention should be limited only by the claims as set forth herein.

[Brief description of the drawings]

For a better understanding of the objects and advantages of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings, in which like parts are designated with like reference numerals.

FIG. 1 is a simplified plan view of a basic coplanar common-drain oscillator circuit according to the present invention.

FIG. 2 is a plan view of another embodiment of a basic coplanar common-drain oscillation circuit.

FIG. 3 is a plan view of a pair of devices connected in a common-drain oscillator coplanar circuit array in accordance with the present invention.

FIG. 4 illustrates one embodiment of a combined cell oscillator circuit array 50 in accordance with the present invention.

FIG. 5 illustrates an alternative embodiment of a coplanar common-drain oscillator array in accordance with the present invention.

FIG. 6 illustrates yet another alternative embodiment of a coplanar common-drain oscillator array in accordance with the present invention.

FIG. 7 illustrates an alternative embodiment of a common-drain oscillator circuit array with an RF open circuit termination gate-drain resonator in accordance with the present invention.

FIG. 8 illustrates one embodiment of a common-drain oscillator circuit array with RF short circuit termination gate-drain resonators in accordance with the present invention.

FIG. 9 is a schematic diagram of an equivalent circuit of the gate-drain resonator circuit of FIG.

FIG. 10 is a plan view of an intricate capacitor coplanar cavity resonator of one embodiment of a common-drain oscillator according to the present invention.

FIG. 11 illustrates one embodiment of a double resonator of a common-drained assembled capacitor coplanar cavity resonator oscillator in accordance with the present invention.

──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J006 HB01 5J081 AA02 AA19 BB06 CC43 DD04 MM06 MM07 MM09

Claims (20)

[Claims] 1. An insulating substrate surface (22a) having a connection region (24a), and first, second and third coplanar conductors (32) mounted on said surface.
, 34, 30), and a proximal portion (32a, 32a,
34a, 30a), wherein the first and second conductors (32, 34) comprise respective distal portions (32b, 34b) extending in different directions from the connection area, and wherein the third conductor (30) comprises A first distal portion (30b) extending adjacent to the distal portion (32b) of the first conductor and a second distal portion (30b) extending adjacent to the distal portion (34b) of the second conductor. 30c), wherein the first and second distal portions (30b, 30c) of the third conductor are separated from ground, an input signal control terminal (36), an inverted output signal carrying terminal (38), and a non-inverted output. And at least one active device (26) with a signal carrying terminal (40), wherein the signal at the output signal carrying terminal depends on the input signal at the input signal control terminal, and The non-inverted output signal carrying terminal (40) is disposed in the connection area with the input signal control terminal (36) coupled to the first conductor (32) and coupled to the second conductor (34). A millimeter wave and microwave circuit structure wherein said inverted output signal carrying terminal (38) is coupled to said third conductor (30). 2. The millimeter wave and microwave circuit according to claim 1, wherein the first conductor (32) and the second conductor (34) are both arranged on one side of the third conductor (30). Construction. 3. The first conductor (32) and the second conductor (34) are connected to the third conductor (34).
The millimeter wave and microwave circuit according to claim 1, wherein the third conductor is arranged on the opposite side of the conductor (30) so that the third conductor passes between the control terminal (36) and the non-inverting terminal (40). Construction. 4. A proximal portion (30a) further comprising a fourth coplanar conductor (30 ') mounted on said surface (22a), said fourth conductor extending into said connection region (24a). '), Wherein the fourth conductor comprises respective first and second distal portions (30b, 30c) extending in different directions from the connection region;
The first conductor extending the fourth conductor adjacent a distal portion (34b) of the second conductor.
A first distal portion (30b) extending adjacent to a conductor and the distal portion (32b) of the second distal portion (30c), a second portion comprising a second input signal control terminal (36). 2 active devices (28),
A second inverted output signal carrying terminal (39) and a second non-inverted output signal carrying terminal (40), wherein the signal at the second input signal control terminal depends on the signal at the second output signal carrying terminal. , The second input signal control terminal (36) is connected to the first conductor (3
2), wherein the second non-inverted output signal carrying terminal (40) is connected to the second conductor (3).
4), wherein the second inverted output signal carrying terminal (39) is connected to the fourth conductor (30).
The millimeter-wave and microwave circuit structure of claim 1 coupled to '). 5. The third and fourth coplanar conductors (30, 30 ') are connected by another coplanar conductor (30d) passing between the first and second conductors (32, 34). 5. The millimeter wave and microwave circuit structure according to 4. 6. The millimeter wave and microwave circuit structure according to claim 4, wherein the fourth conductor (30 ′) and the third conductor (30) are connected. 7. The millimeter wave and microwave circuit structure according to claim 6, wherein said fourth conductor (30 ') is in contact with said third conductor (30). 8. The millimeter of claim 1, wherein the distal portion (32b) of the first conductor and one distal end (30b) of the third conductor are connected to a resonator circuit (42). Wave and microwave circuit structure. 9. The tuning circuit according to claim 8, wherein a portion of the first conductor and one distal end of the third conductor are configured as a portion of the tuning circuit. Millimeter and microwave circuit structure. 10. The distal end of the second conductor (34b) and one distal end (30c) of the third conductor are connected to a feedback circuit (44).
The millimeter wave and microwave circuit structure according to 1. 11. A part of said second conductor (34) and one distal end (30c) of said third conductor are configured as part of said feedback circuit (44). The described millimeter wave and microwave circuit structure. 12. A distal end (32b) of said first conductor and one distal end (30b) of said third conductor are connected to a tuning circuit (42) and a distal end of said second conductor. The millimeter wave and microwave circuit structure according to claim 1, wherein the portion (34b) and the other distal end (30c) of the third conductor are connected to a feedback circuit (44). 13. The resonator circuit (42) and a feedback circuit (44).
13. The millimeter wave and microwave circuit structure of claim 12, wherein the is configured such that the structure is an oscillator. 14. The millimeter-wave and microwave circuit structure according to claim 10, 11, 12, or 13, wherein said feedback circuit (307) includes a coplanar capacitor (312, 316). 15. A conductor (30, 32) connected to said first device (26).
And the conductor (30, 32, 34) connected to said second device (28) comprises a portion of a second oscillator circuit. Microwave circuit structure. 16. The millimeter wave and microwave circuit structure according to claim 15, wherein said signals of said first and second oscillators are locked such that said oscillator oscillates in phase. 17. The millimeter wave and microwave circuit structure according to claim 15, wherein said first and second oscillation circuits are coupled so that said oscillators perform push-pull oscillation. 18. The active device (26) may be a field effect transistor, a bipolar transistor, a heterojunction transistor, a resonant tunneling transistor, a real space transmission device, a magnetically permeable base transistor, a solid state triode,
The millimeter wave and microwave circuit structure of claim 1, wherein the millimeter wave and microwave circuit structure is selected from the group consisting of a triode vacuum tube, a controlled electronic avalanche triode device, and a superconducting triode device. 19. The millimeter wave and microwave circuit structure according to claim 1, wherein said circuit is a common drain oscillator (20). 20. The resonator or feedback circuit (42, 44)
11. The millimeter wave and microwave circuit structure of claim 8 or 10, wherein the millimeter wave and microwave circuit structure is selected from the group consisting of a coplanar slot line circuit, a coplanar waveguide circuit, a coplanar transmission line circuit, and a coplanar feedback circuit.