KR20010028503A - Auto analog/digital convertor - Google Patents

Abstract

PURPOSE: An automatic analog/digital converting circuit is provided to improve the efficiency in the use of a CPU by making the CPU operate independently with that the analog/digital signal converting progress isn't controlled by the order of the CPU. CONSTITUTION: An automatic analog/digital converting circuit includes a MUX portions(50, 53, 56, 60), a sample/hold portion(65), an analog/digital converting portion(70), a RAM(90), an automatic analog/digital converting control instrument(75). The MUX portions(50, 53, 56, 60) select and output an analog signal from many analog signals. The sample/hold portion(65) carries out the sampling/holding operation of the analog signal. The analog/digital converting portion(70) converts the output of the sample/hold portion(65) into the digital signal. The RAM(90) stores the output of the analog/digital converting portion(70). The automatic analog/digital converting control instrument(75) controls the operation of the MUX portions(50, 53, 56, 60), the sample/hold portion(65), the analog/digital converting portion(70) and the RAM(90) totally.

Description

Auto analog / digital convertor

The present invention relates to an automatic analog-to-digital conversion circuit, and more particularly, to a central processing unit that performs a different function while converting an analog input signal into a digital signal in a system requiring high-speed signal processing. It relates to an analog / digital conversion circuit.

An analog / digital conversion circuit is a device that converts an analog input signal into a digital signal. Many electronic devices including computers, which are recently produced, have their own analog / digital conversion circuits. Therefore, even if the external peripheral performs the signal processing by the analog method, it is possible to input the analog output signal of the peripheral device to convert itself into a digital signal by the internal analog / digital conversion circuit, and then perform the necessary signal processing.

In addition, digital signal processing has spread rapidly in recent years, and in the past, almost all signal processing methods were analog signal processing methods. That is, since many electronic devices already used use the analog signal processing method, it is necessary to be compatible with the analog signal processing method and the digital signal processing device provided while adding new functions.

In accordance with such a requirement, it has become essential to have an analog / digital conversion function in a system, and thus, many devices have been proposed to perform analog / digital conversion more conveniently and faster.

1 illustrates an analog / digital conversion circuit for automatically performing analog / digital conversion in a system of a conventional electronic device.

In the conventional automatic analog / digital conversion circuit, a mux (MUX) 10 for inputting a plurality of analog signals from the outside and selecting and outputting one of the signals is sampled, and the output of the mux 10 is sampled and the digital signal is output. A sample / hold unit (S / H: 15) to hold a predetermined amount until being converted into a signal, an analog / digital conversion unit 20 for converting the output of the sample / hold unit 15 into a digital signal, and the analog / A buffer 25 that temporarily stores the digital signal converted by the digital conversion unit 20, and controls to control the operation of the mux 10, the sample / hold unit 15, the analog / digital conversion unit 20 Circuit 30.

When an analog / digital conversion command is applied to the control circuit 30 and an analog / digital conversion completion signal is output from the analog / digital conversion unit 20, the converted digital signal is read from the buffer 25. And a central processing unit (CPU: not shown) that performs the necessary signal processing.

Next, the conventional analog / digital conversion operation by the above configuration will be described.

2 is an operation timing diagram according to a conventional analog / digital conversion operation.

The control circuit 30 operates the clock signal as shown in FIG. 2A as a reference clock signal. The control circuit 30 is in a standby state for controlling the analog / digital conversion operation until the analog / digital conversion command signal is applied from the central processing unit.

The I / O write signal #IOWR shown in FIG. 2B output from the CPU is an analog / digital conversion command signal. Therefore, when the I / O write signal #IOWR is applied from the central processing unit, the control circuit 30 performs analog / digital conversion control. At this time, the CPU writes the data (no data meaning) to a specific address while outputting the I / O write signal #IOWR (FIG. 2C).

The control circuit 30 outputs one analog signal selection signal to the mux 10 when an analog / digital conversion command is input from the central processing unit (FIG. 2D). The mux 10 selects and outputs one analog signal based on the input signal.

The analog signal output from the MUX 10 is input to the sample / hold unit 15, and the sample / hold unit 15 is a signal of the signal input by the sample / hold signal applied from the control circuit 30. After the sampling is performed, it is temporarily held (FIG. 2E).

The signal output from the sample / hold unit 15 is input to the analog / digital converter 20. The analog / digital converting unit 20 converts an input signal when the analog / digital converting signal (FIG. 2f) is applied from the control circuit 30 after the signal processing of the sample / hold unit 15 is completed. do. When the digital conversion of the input signal is completed, the analog / digital conversion unit 20 outputs a signal according to the completion of the analog / digital conversion (FIG. 2G).

The analog / digital conversion completion signal output from the analog / digital conversion unit 20 is applied to the central processing unit, and the central processing unit performs digital conversion to read the signal stored in the buffer 25.

That is, in the conventional analog / digital signal processing method, after the analog / digital conversion command is applied from the central processing unit, the analog / digital conversion operation is performed under the control of the control circuit 30. Subsequently, the central processing unit reads the necessary digital signal only after the analog / digital conversion unit 20 receives a signal corresponding to the completion of the conversion to the central processing unit. At this time, the CPU is in a standby state after the analog / digital conversion command is output until the analog / digital conversion completion signal is input.

Therefore, in the conventional analog / digital signal processing method, a difference may occur depending on the processing speed of the converter. However, since the central processing unit must maintain the standby state for several tens of microseconds while the analog / digital conversion operation is performed, The problem is that the operation is not efficient.

In addition, in the conventional analog / digital signal processing method, since the conversion operation starts only after the analog / digital conversion command is applied from the central processing unit, a problem occurs that the processing speed due to the analog / digital conversion becomes slow.

Accordingly, an object of the present invention is to provide an automatic analog / digital conversion circuit that can increase the use efficiency of the central processing unit by allowing the central processing unit to independently operate regardless of the analog / digital signal conversion process.

Another object of the present invention is to provide an automatic analog / digital conversion circuit that can increase the analog / digital signal conversion speed by allowing the analog / digital signal conversion process to be automatically performed without being controlled by the command of the central processing unit. .

It is also an object of the present invention to provide an automatic analog-to-digital conversion circuit capable of performing analog / digital signal conversion under the control of a central processing unit as necessary.

1 is a block diagram of an automatic analog / digital conversion circuit according to the prior art,

2 is an operation timing diagram of a prior art;

3 is a configuration diagram of an automatic analog / digital conversion circuit according to the present invention;

4 is an operation timing diagram according to the present invention.

Explanation of symbols on the main parts of the drawings

10,50,53,56,60: MUX 15,65: Sample / hold part

20,70: Analog / Digital Converter 25,80,85: Buffer

30: control circuit 90: RAM

75: automatic analog / digital conversion control circuit

According to an aspect of the present invention, there is provided an automatic analog / digital conversion circuit including a mux unit for selectively outputting one analog signal from a plurality of analog signals; A sample / hold unit which performs sampling and holding operations of an analog signal; An analog / digital converter for converting the output of the sample / hold unit into a digital signal; A RAM for storing an output of the analog / digital converter; And an automatic analog / digital conversion control means for automatically controlling the operation of the mux, the sample / hold unit, the analog / digital conversion unit, and the RAM so that the analog / digital conversion operation is automatically performed.

The automatic analog / digital conversion control means of the present invention is characterized by being capable of selectively controlling the analog / digital conversion operation under the control of the central processing unit.

Hereinafter, an automatic analog / digital conversion circuit according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an automatic analog / digital conversion circuit according to the present invention.

The automatic analog-to-digital conversion circuit of the present invention includes a plurality of muxes (MUX: 50, 53, 56) for inputting a plurality of analog signals from the outside, and selecting and outputting one of the signals. Another mux 60 that selects one signal from the outputs of (53, 56), and a sample / hold part (S / H) for holding a predetermined amount until sampling and outputting the output of the mux (60) 65), and an analog / digital converter 70 for converting the output of the sample / hold unit 65 into a digital signal, and temporarily storing the digital signal converted by the analog / digital converter 70. Buffers 80,85.

That is, the mux, the sample / hold unit, the analog / digital converter, and the buffer are configured in the same manner as in the prior art, and the operation of each component is also controlled by the control signal applied by the automatic analog / digital conversion control circuit 75 as in the prior art. Is done.

In addition, the automatic analog-to-digital conversion circuit of the present invention includes a RAM 90 that stores the outputs of the buffers 80 and 85, the plurality of muxes 50, 53, 56, and 60, and a sample / hold unit ( 65, an analog-to-digital conversion unit 70, buffers 80 and 85, and an automatic analog-to-digital conversion control circuit 75 for controlling the operation of the RAM 90. The RAM 90 uses dual port RAM.

That is, the automatic analog / digital conversion control circuit 75 of the present invention selects one analog signal from the muxes 50, 53, 56, and 60 by itself. In addition, the sampling / holding unit 65 controls the sampling / holding of the sample / hold unit 65 using the output of the mux 60 and controls the signal conversion of the analog / digital conversion unit 70. At this time, the operation control according to the digital conversion of the input signal is performed by the automatic analog / digital conversion control circuit 75 itself. Therefore, when an analog signal is input, the automatic analog / digital conversion control circuit 75 automatically controls the operation according to the digital conversion.

If necessary, the central processing unit applies an analog / digital conversion command to the automatic analog / digital conversion control circuit 75 and outputs an analog / digital conversion completion signal from the analog / digital conversion unit 70. The digital signal stored in the RAM 90 is read and necessary signal processing is performed.

Next, an automatic analog / digital conversion operation according to the present invention having the above configuration will be described.

The automatic analog / digital conversion control circuit 75 determines whether the current analog / digital conversion operation control is automatic control or manual control based on the FRUN signal. If the FRUN signal input to the automatic analog / digital conversion control circuit 75 is high, the automatic analog / digital conversion control by self control is performed. If the FRUN signal is low, manual control by the central processing unit is performed. Perform analog / digital conversion control.

First, the case where the FRUN signal is high will be described.

The automatic analog / digital conversion control circuit 75 controls the operation in synchronization with the reference clock signal (Fig. 4A). First, a control for selecting one analog signal from a plurality of muxes 50, 53, 56, and 60 is performed. When a signal as shown in FIG. 4D is input to each mux, the selection operation of the muxes 50, 53, 56, and 60 is controlled, and one analog signal is output from the final mux 60.

The analog signal output from the mux 60 is input to the sample / hold unit 65. The automatic analog / digital conversion control circuit 75 outputs a control signal according to the sampling and holding operations to the sample / hold unit 65 (FIG. 4E). When the control signal is applied, the sample / hold unit 65 samples the input signal and holds the digital signal until digital conversion.

The output of the sample / hold unit 65 is input to the analog / digital converter 70. The automatic analog / digital conversion control circuit 75 outputs a control signal (FIG. 4F) for signal conversion to the analog / digital conversion unit 70 at the time when the operation of the sample / hold unit 65 is completed. When the signal conversion control signal is applied from the automatic analog / digital conversion control circuit 75, the analog / digital conversion unit 70 performs digital conversion of the input signal and outputs a conversion completion signal (Fig. 4G).

When the signal (FIG. 4G) is outputted according to the signal conversion completion from the analog / digital conversion unit 70, the automatic analog / digital conversion control circuit 75 buffers the lower 8-bit signal of the converted signal. Outputs a control signal (FIG. 4I) for storage in the terminal. The lower 8-bit signal, signal-converted by the control signal, is temporarily stored in the buffers 80 and 85. When the storing operation is completed, the automatic analog / digital conversion control circuit 75 outputs a control signal (FIG. 4J) for storing the remaining four bit signals of the converted signals in the buffers 80 and 85. The upper 4-bit signal, signal-converted by the control signal, is stored in the buffers 80 and 85. That is, the signal output from the analog-to-digital converter 70 is a 12-bit signal. However, since the RAM 90 uses 8 bits, the RAM 90 divides the converted signal twice and performs the storage operation.

On the other hand, when performing digital conversion of the analog signal, the automatic analog / digital conversion control circuit 75 designates a RAM address for storing the converted digital signal in the RAM 90 (Fig. 4H).

Therefore, the RAM 90 receives an address for storing the input digital signal from the automatic analog / digital conversion control circuit 75 and becomes a standby state for storing the digital signal. Then, after the digital conversion of the input signal is completed, if the RAM selection signal (Fig. 4k) and the ram light signal (Fig. 4L) applied by the automatic analog / digital conversion control circuit 75 is input to the RAM 90, the The digital signals output from the buffers 80 and 85 are stored at the designated addresses.

When the operation of storing the digital signal in the RAM 90 by the above process is completed, all the operations according to the analog / digital conversion are automatically completed under the control of the automatic analog / digital conversion control circuit 75.

Therefore, the central processing unit reads the digital data stored in the RAM 90 and performs the necessary signal processing regardless of the analog / digital conversion operation time. Therefore, the analog / digital conversion operation performed under the control of the automatic analog / digital conversion control circuit 75 is performed irrespective of the central processing unit, and thus the central processing unit can perform the necessary signal processing at high speed.

Next, when the FRUN signal input to the automatic analog / digital conversion control circuit 75 is in a low state, the automatic analog / digital conversion control circuit 75 performs a signal conversion operation of each circuit under the analog / digital conversion command of the central processing unit. To control.

When the I / O write signal #IOWR shown in FIG. 4B is applied from the central processing unit, the automatic analog / digital conversion control circuit 75 performs control for an analog / digital conversion operation. At this time, the CPU writes the data (no data meaning) to a specific address while outputting the I / O write signal #IOWR (FIG. 4C).

Thereafter, the automatic analog / digital conversion control circuit 75 controls the operations of the mux, the sample / hold unit, the analog / digital conversion unit, and the buffer according to the above-described control process to perform digital conversion of the input analog signal. After that, the operation to save to RAM is completed.

When the storage of the digital signal converted in the RAM 90 is completed, the automatic analog / digital conversion control circuit 75 outputs a signal indicating the completion of the RAM storage of the digital signal to the central processing unit (FIG. 4M).

When the RAM storage completion signal (FIG. 4m) is input, the CPU recognizes that the digital conversion of the analog signal is completed, reads the signal from the RAM 90, and performs necessary signal processing.

As described above, the automatic analog / digital conversion circuit according to the present invention controls the analog / digital conversion operation to be performed independently of the central processing unit, so that the central processing unit can perform the necessary signal processing regardless of the signal conversion operation time. have. Therefore, while increasing the use efficiency of the central processing unit, high-speed signal processing is possible.

Claims (4)

A mux unit for selectively outputting one analog signal from a plurality of analog signals; A sample / hold unit which performs sampling and holding operations of an analog signal; An analog / digital converter for converting the output of the sample / hold unit into a digital signal; A RAM for storing an output of the analog / digital converter; Automatic analog / digital conversion circuit including automatic mux, sample / hold part, analog / digital conversion part, automatic analog / digital conversion control means for controlling the operation of RAM to perform analog / digital conversion automatically. . The method of claim 1, And the automatic analog / digital conversion control means can selectively control the analog / digital conversion operation under the control of the central processing unit. The method according to claim 1 or 2, The mux part, A plurality of mux elements connected in parallel to input analog signals from the outside; And a mux element for selectively outputting one analog signal from the plurality of mux elements under control of the automatic analog / digital conversion control means. The method of claim 3, wherein And a buffer which temporarily stores the output of the analog / digital converter and transmits the output to the RAM.