JPH0637339Y2 - Waveform storage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to speeding up the display of stored waveforms in a waveform storage device.

[Outline of device]

The waveform storage device constantly performs analog-to-digital conversion (hereinafter AD conversion) of the observed signal and writes it to the memory.
After a trigger is applied, AD conversion and writing are performed a predetermined number of times m, and then the operation is stopped. Then, the n data before the stop is transferred to another display memory and displayed. Where n> m
Then, it is possible to display the data before the trigger is applied, which is a major feature of ordinary oscilloscopes. On the other hand, since the stop position depends on the presence or absence of a trigger, the positions of n pieces of data to be displayed are indefinite. For this reason,
There are also cases where the transfer from the end of the acquisition memory to the display memory is started and the process returns to the beginning of the acquisition memory. Therefore, it is necessary to always check the address while transferring. The present invention is to add a selector to a memory access circuit so that only a desired memory can be accessed at all times, thereby eliminating the above processing and speeding up data transfer from an acquisition memory to a display memory. .

[Conventional technology]

As a conventional technique, there is one that uses a direct memory access method for transfer, which allows the fastest transfer, but requires a dedicated large-scale integrated circuit and peripheral circuits.

The other method is a method in which both the acquisition memory area and the display memory area use the memory of the microcomputer and are transferred by a program. In this method, a pointer is provided to each memory, and data is transferred one by one by indirect addressing and pointer updating is repeated. As described above, in some cases, the transfer first returns from the end of the memory to the beginning. Therefore, in this method, it is necessary to check whether or not it is at the end every time the pointer is updated, regardless of the area, and the processing time required for this is longer than the original transfer and pointer updating processing.

[Problems to be solved by the invention]

As described above, in the conventional technology, either an expensive circuit is used or an inexpensive but slow program transfer is performed.

In recent years, the waveform storage device is in the direction of increasing the capacity, and if the latter is adopted, the transfer time will increase and the operability will decrease.

In order to solve these drawbacks, the present invention makes it possible to automatically access the data at the end of the memory after the data is transferred in the program transfer method, thereby shortening the transfer time and improving the operability. With the goal.

[Means for solving problems]

In order to achieve the above object, the present invention separates each memory from the microcomputer, selects each memory by a selector, and stores the data in the memory in a portion (4096) of the address signal output from the microcomputer. In the case of bytes, the lower 12 bits are accessed. The capacity of each memory is a power of 2.

[Operation] This result will be explained assuming that the memory capacity is 4096 bytes.
When the end of the memory is transferred, the pointer value is FFF (hexadecimal number). When this is updated by 1 byte, it becomes 1000 (hexadecimal number), but the valid one is the lower 3 digits (12 bits), and its memory is selected by the selector.
The address 000 (hexadecimal number) in the memory, that is, the beginning can be accessed.

〔Example〕

An embodiment of the present invention in a 2-channel waveform storage device will be described below with reference to FIG. Reference numeral 1 is a microcomputer for controlling the whole, and its flowchart is shown in FIG. 2 is the upper 4 bits of the address signal, 3 is the lower 12 bits, 4, 7 and 8 are selectors, 5 and 6 are signals for selecting 7, 8 and 9 is 7, 8
Is a signal for selecting each memory, 10, 11, 12, 13 are signals for selecting each memory, 14, 15 are acquisition memories, 16, 17
Is a display memory, each memory is 4096 bytes, and 18 is an 8-bit data bus.

Next, this operation will be described. The microcomputer 1 outputs the upper 4 bits 2 of the address signal and the selection signal 9. The selector 4 for selecting the acquisition memory or the display memory has the upper 4 bits 2 of the address signal.
Select signal 5 is output when B, C (hexadecimal), D, E (hexadecimal)
At that time, the selection signal 6 is output to drive one of the selectors 7 and 8. As a result, either the acquisition memory 14 or 15 or the display memory 16 or 17 is selected. When the selector 7 is driven, the selection signal 9 is input, when it is OFF, the selection signal 10 is output, and when it is ON, the selection signal 11 is output to select one of the acquisition memories 14 and 15 corresponding to the channel. When the selector 8 is driven, the display memory 16 or 17 is similarly selected corresponding to the channel. In this way, the microcomputer 1 selects any one of the acquisition memories 14 and 15 and the display memories 16 and 17 according to the upper 4 bits 2 of the address signal and the selection signal 9. Also microcomputer 1
Outputs the lower 12 bits of the address signal 3 and designates the address in each memory.

In this way, the microcomputer 1 outputs the selection signal 9
When it is turned off and the address B000 to CFFF (hexadecimal number) is accessed, the address in the acquisition memory 14 is always accessed. In particular, if the pointer indicates the address BFFF (hexadecimal number) and then it is updated by 1 byte, it becomes address C000 (hexadecimal number).
Actually, the above operation will access the address B000. The same applies to access to the acquisition memory 15 and the display memories 16 and 17.

[Effect of device]

As described above, according to the present invention, it is not necessary to check the end of the memory by the program and switch to the beginning.

Therefore, the transfer time is greatly reduced compared to the conventional program transfer method. In particular, depending on the model of the microcomputer, there is one that can transfer an arbitrary number of data with one instruction. By implementing the present invention, this instruction can be used, and in this case, a transfer speed close to that of the direct memory access method can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flow chart of the microcomputer 1. 1: Microcomputer, 4, 7, 8: Selector, 14, 15: Acquisition memory, 16, 17: Display memory.

Claims (1)

[Scope of utility model registration request] 1. A micro computer and the micro computer.
A plurality of acquisition memories for storing the analog-digital converted data from the computer in correspondence with the lower-order bit address signal from the same microcomputer, and the data transferred from the acquisition memory, the lower memory from the microcomputer. A plurality of display memories for storing in correspondence with bit address signals,
An acquisition memory-a selector for a display memory, which selects between the acquisition memory and the display memory according to an address signal of an upper bit indicating a memory address from the microcomputer;
An acquisition memory selector for selecting one of the plurality of acquisition memories according to a selection signal from a computer, and a display memory for selecting one of the plurality of display memories according to a selection signal from the microcomputer. When transferring data from the acquisition memory to the display memory, the address of the acquisition memory is specified by the lower bit of the memory address of the microcomputer to access the acquisition memory at the end of the memory. A waveform storage device characterized by cyclically controlling from an address to a leading address.