KR20010025919A - Method for processor down report - Google Patents

Abstract

PURPOSE: The method for rebooting is provided to report the processor down information to a user, and to display the down information of the system on the operator's terminal. CONSTITUTION: The interrupt intercept protection is configured to ignore the interrupt happened by the other device error(20). The system error table is fetched(22). The MPU(Micro-processor) checks if the content of the system error is a bus or an address error(24). If not a bus or an address error, the MPU fetches the user device error table(26). The related error content is processed(28). If yes at the step 24, the MPU runs the exception handling(30). The down flag, which is configured in the external RAM, is set(34). The information, such as the processor information state, the PC value, and the SR value, is saved on the down message area(36). The boot restarting is run according to the OS of the ROM(32).

Description

How to restart on processor down {METHOD FOR PROCESSOR DOWN REPORT}

The present invention relates to a restart control method of a system having a micro-processor (hereinafter referred to as "MPU"), in particular, when the system is restarted by processor down (processor down) automatically A method of restarting when a processor crashes to automatically report to a user.

At present, the control of most electrical, electronic control devices and exchange systems is equipped with a logic computing device, for example, a one-chip controller called an MPU. Such MPUs tend to be multiplexed with two or more MPUs in order to improve control complexity and control speed. These MPUs, as is well known, have many registers for performing ROMs and RAMs and instructions and temporarily storing data. In addition, in order for the MUP to operate, a program ROM permanently storing an operating system (OS) program, a RAM for storing the data processed by the MUP or reading the stored data, and the like. Is common.

In a switching system, a plurality of processors are mounted to process a large amount of traffic at one time, and are divided into lower and upper processors. If the processor is down for some reason in such a switching system, it is supposed to be rebooted by the operation of the OS.

1 is a block diagram illustrating a hardware block in which the present invention is performed. In Fig. 1, reference numeral 10 denotes a ROM in which an OS programmed to meet operating conditions of a system is stored. The ROM 10 has a program counter (hereinafter referred to as "PC") 12a and a state register (hereinafter referred to as "SR") 12b therein. Is connected to. The MPU 12 is also connected with a RAM 14 for accessing data under the control of the MPU 12 and a VDU 16 for displaying display data output from the MPU 12. Such a device is a hardware specification that is common to electrical and electronic systems controlled by a microprocessor as well as an exchange system.

FIG. 2 is a flowchart illustrating a method of restarting a processor according to the prior art, which is operated when the processor of the system shown in FIG. 1 is down for some reason, causing a system error (eg, a bus error). Alternatively, when an address error occurs, a process of restarting after displaying an internal PC value and an SR value on a user terminal (VDU) by an exception process is performed.

First, a description will be given of a restart method when the processor is down according to the prior art with reference to FIGS.

The types of interrupts provided by general-purpose microprocessors such as the MC68XXX series MPUs are as follows. Several types of interrupts are provided: bus errors, address errors, illegal errors, device errors, checksum errors, trap errors, and so on. These errors are fatal errors that occur while the user program is running in the processor. If this error occurs, the OS restarts the MUP. In the interrupt service routine, the interrupt vector value is generated and the corresponding service routine takes appropriate action.

Now, when the system as shown in Fig. 1 is down due to some cause during operation and one of the interrupts is generated, the error content of the system generated by the automatic vector is recorded in the vector table in the MUP 12. do.

In this case, the MUP 12 illustrated in FIG. 1 sets interrupt interception prevention to ignore an interrupt generated by another device error in step 20 of FIG. 2, and fetches a system error table in step 22. come. Here, the system error table refers to values corresponding to the system error (address error or bus error, etc.) in the vector values.

In step 24, the MUP 12 searches whether the system error is a bus or addresser error. If it is determined that the search result is not a bus or address error, the MPU 12 fetches the user device error table in step 26 and processes the error content in step 28.

If the error content of the system is determined to be a bus or address error in the search of step 24, the MPU 12 executes exception processing in step 30 of FIG. Here, the exception processing means that the values of the PC 12a and the SR 12b in the MPU 12 are outputted to the VDU 16 as a user terminal for display. At this time, if the user is monitoring the VDU (16) it is possible to know the down phenomenon of the report system by displaying the displayed value. In step 30, the MPU 12, which has performed the interrupt exception processing, restarts the system according to the OS.

However, the conventional method for restarting a processor as shown in FIG. 2 does not report to the user what cause the processor has been shut down, but merely the PC value, SR value, and process name of the processor. By simply displaying the back on the dummy terminal VDU 16, operators could not take appropriate measures. In addition, when the MPU 12 shown in FIG. 1 is down while operating as a main processor, a solution to solve this problem may not be properly prepared, which may cause a recovery time of the system.

Accordingly, an object of the present invention is to provide a method for reporting information on a cause of a processor down to a user when the processor is down in a system using the processor.

It is another object of the present invention to provide a method for restarting a processor that displays down information of the system on an operator's terminal in response to the system restarting by the processor down.

In order to achieve the above object, the present invention stores the contents of a program counter, a status register, and a stack frame message at a down time in a predetermined storage area as a down message, sets a down flag, and restarts a boot. And retrieving whether or not the down flag is set when the boot is restarted, and accessing the contents of the down message stored in the storage area and displaying the content on the user terminal in response to the down flag being set. do.

1 is a block diagram illustrating a hardware block in which the present invention is performed.

2 is a flowchart illustrating a method of restarting a processor in accordance with the prior art;

3 is a flowchart illustrating a method for restarting a processor in accordance with an embodiment of the present invention, and an improved control flowchart for down report.

4 is a flowchart illustrating an initial operation control at restart according to an embodiment of the present invention.

Hereinafter, a processor down report method by restarting a processor according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings, and the same elements as those shown in FIG. Reference numbers are written together. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

FIG. 3 is a flowchart illustrating a method for restarting a processor in accordance with an embodiment of the present invention, which is an improved control flow diagram for down reporting, and includes a send fault report process in the aforementioned control process of FIG. 1. Is further added. Here, the send pulse report process sets a down flag in response to the occurrence of a system error and an interrupt indicating a system error, and externally stores values such as PC 12a, SR 12b, etc. in the MPU 12. It includes a series of control procedures for storing in the memory area of the.

FIG. 4 is a flowchart illustrating an initial operation control at restart according to an embodiment of the present invention. In FIG. 4, the system detects whether a down flag is set at boot restart due to a system error, and the down flag is set. And accessing the down message stored in the external memory area and displaying the same on the VDU 16.

If a system error such as a bus or address error occurs now and an interrupt is generated, the MPU 12 raises the priority of the interrupt as described in FIGS. 1 and 2 to prevent the interception by another interrupt, and then generates the current. In step 24 of FIG. 3, the detected error is a bus or address error.

If it is determined in step 24 that the bus or address error, the MPU 12 performs an exception process in step 30 of FIG. In step 34, the down flag set in the external RAM 14 is set, and in step 36, information on the currently operating process information state, the value of the PC 12a, the value of the SR 12b, the stack frame, etc. is externally set. It is stored in the down message area set in RAM 14. The MPU 12 performing the send pulse lift process as in step 36 of FIG. 3 performs a boot restart according to the OS of the ROM 10 in step 32 of FIG. 3 (32 of FIG. 4).

In operation 40 of FIG. 4, the MPU 12 performing a boot restart stores the down message set in the area of the RAM 14, that is, the process information state, the PC value, the SR value, and the stack frame information at the down time. 16) so that the operator can monitor it.

At this time, assuming that the VDU 16 is a terminal capable of man machine communication (MMC) with the system, the operator immediately recognizes the fault information displayed through the VDU 12 to easily cope with a process state in which the fault occurs. This malfunction can be debugged.

As described above, according to the present invention, when the system is down for some reason, the interrupt status due to an error can be known by reporting the down state at restart, and the stack frame value at the time of the processor down is transmitted to the operator's terminal. This has the advantage that operators can more easily debug system failures.

Claims (2)

In the method of restarting when the processor is down, During the processor down process, the contents of the internal program counter, status register, and stack frame message at the time of down is stored as a down message in a preset storage area, and the down flag is set and boot restarted; And a process of accessing the contents of the down message stored in the storage area and displaying the contents of the down message stored in the storage area in response to the setting of the down flag when the boot is restarted. City restart method. The method of claim 1, wherein the down message includes process status information at the time the processor is down, program counter information and status registers in the processor, stack frame information, and the like.