KR20010020824A - Cold cathode field emission device and method of producing the same, and cold cathode field emission display - Google Patents

Abstract

PURPOSE: To provide a cold cathode field electron emission element easily manufactured and capable of coping with a big screen of a display device. CONSTITUTION: This cold cathode field electron emission element is provided with (A) a cathode electrode 11 formed on a support 10, (B) an insulating layer formed on the support 10 including the cathode electrode 11, (C) a gate electrode 13 formed on the insulating layer 12, (D) an opening 14 penetrating the gate electrode 13 and the insulating layer 12, (E) a resistor layer 15e formed on the cathode electrode 11 located at the bottom of the opening 14 and having the tip part in a shape of a drill, and (F) an electron emitting part 17e made of a conductive material whose work function is smaller than that of the material constituting the resistor layer 15e and formed on the tip of the resistor layer 15e reflecting its drill shape.

Description

COLD CATHODE FIELD EMISSION DEVICE AND METHOD OF PRODUCING THE SAME, AND COLD CATHODE FIELD EMISSION DISPLAY}

The present invention relates to a cold cathode field emission device, a method for manufacturing the same, and a cold cathode field emission display device. More specifically, a cold cathode field emission device having a horn-shaped tip and a method for manufacturing the same, and a cold cathode field emission. The present invention relates to a planar cold cathode field emission display device in which elements are arranged in a two-dimensional matrix.

Currently, various types of flat panel (flat-panel type) display devices have been studied as an image display device replacing the mainstream cathode ray tube (CRT; cathode ray tube). Examples of such a flat panel display include a liquid crystal display (LCD), an electroluminescence display (ELD), and a plasma display panel (PDP). In addition, a cold cathode field emission display device, which is capable of emitting electrons from a solid in a vacuum without thermal excitation, and a so-called field emisson display (FED), has also been proposed. And low power consumption.

A cold cathode field emission type display device (hereinafter sometimes referred to simply as a "display device") generally includes a cathode panel having an electron emission portion corresponding to each pixel arranged in a two-dimensional matrix form, and from the electron emission portion. An anode panel having a phosphor layer excited by collision with emitted electrons and emitting light has a configuration in which the anode panel is disposed opposite the vacuum layer. In each pixel on the cathode panel, a plurality of electron emission sections are usually formed, and a gate electrode for drawing electrons from the electron emission sections is also formed. The part which has this electron emission part and a gate electrode is called a field emission element.

In the configuration of such a display device, in order to obtain a large emission electron current at a low driving voltage, the tip shape of the electron emission section is sharply sharpened, and the presence of the electron emission section in a section corresponding to one pixel by miniaturizing individual electron emission sections Increasing the density and shortening the distance between the tip of the electron emission section and the gate electrode is required. Therefore, in order to realize this, the field emission element which has various structures is conventionally proposed.

As a representative example of the field emission device used in such a conventional display device, a so-called Spindt type field emission device having an electron emission portion made of a conical conductor is known. 37 is a conceptual diagram of the display device to which the spin type field emission device is applied. The spin type field emission device formed on the cathode panel CP includes a cathode electrode 201 formed on the support 200, an insulating layer 202, a gate electrode 203 formed on the insulating layer 202, and a gate electrode. And a conical electron emission portion 205 formed in the opening 204 formed through the 203 and the insulating layer 202. A predetermined number of electron emitters 205 are arranged in a two-dimensional matrix to form one pixel. On the other hand, the anode panel AP has a structure in which the phosphor layer 211 is formed on the transparent substrate 210 by a predetermined pattern, and the phosphor layer 211 is covered with the anode electrode 212.

When a voltage is applied between the electron emission section 205 and the gate electrode 203, electrons "e" are drawn out from the tip of the electron emission section 205 by the resulting electric field. This electron "e" is attracted to the anode electrode 212 of the anode panel AP and collides with the phosphor layer 211 which is a light emitting layer formed between the anode electrode 212 and the transparent substrate 210. As a result, the phosphor layer 211 is excited to emit light, thereby obtaining a desired image. The operation of this field emission element is basically controlled by the voltage applied to the gate electrode 203.

Here, the outline | summary of the typical manufacturing method of a spin type field emission element is demonstrated with reference to FIG. 38 (A), FIG. 38 (B), FIG. 39 (A), and FIG. 39 (B). This manufacturing method is basically a method of forming the conical electron emitting portion 205 by vertical vapor deposition of a metal material. That is, the deposition particles are incident perpendicularly to the openings 204 but reach the bottom of the openings 204 using a shielding effect by an overhang-shaped deposit formed near the opening end. By reducing the amount of conical deposits, the electron emission portions 205 are formed in a self-alignment manner. Here, a method of forming the release layer 206 in advance on the gate electrode 203 will be described in order to facilitate the removal of unnecessary overhang deposits.

[Step-10]

First, for example, a cathode electrode 201 made of niobium (Nb) is formed on a support 200 made of a glass substrate, and an insulating layer 202 made of SiO ₂ and a gate electrode 203 made of a conductive material are formed thereon. ) Is sequentially formed, and then the gate electrode 203 and the insulating layer 202 are patterned to form the openings 204 (see FIG. 38 (A)).

[Process-20]

Next, as shown in FIG. 38 (B), the exfoliation layer 206 is formed by obliquely depositing aluminum on the gate electrode 203. At this time, by sufficiently selecting the incident angle of the deposition particles with respect to the normal of the support 200, the release layer 206 is formed on the gate electrode 203 with almost no aluminum deposited on the bottom of the opening 204. can do. The release layer 206 protrudes from the opening end of the opening 204 in an eave shape, whereby the diameter of the opening 204 is substantially reduced.

[Process-30]

Next, molybdenum (Mo) is vertically deposited on the entire surface as a conductive material, for example. At this time, as the conductive material layer 205A having an overhang shape grows on the release layer 206 as shown in FIG. 39A, the substantial diameter of the opening 204 gradually decreases, so that the opening 204 is formed. The deposited particles contributing to the deposition at the bottom are gradually limited to passing near the center of the opening 204. As a result, a conical deposit is formed at the bottom of the opening 204, and the conical deposit becomes the electron emission section 205. FIG.

[Step-40]

Thereafter, as shown in FIG. 39 (B), the peeling layer 206 is peeled off from the surface of the gate electrode 203 by an electrochemical process and a wet process to remove the conductive material layer 205A above the gate electrode 203. Remove (lift off).

By the way, since the electron-emitting part as described above is actually formed in the case of tens of millions of orders on the support, the non-uniformity of the electron emission characteristic due to the non-uniformity of individual shapes and dimensions cannot be avoided. In other words, the threshold value of the gate voltage at the start of electron emission is different for each electron emission portion, and furthermore, the I-V curve (the horizontal axis of the gate voltage V and the vertical axis of the emission electron current I) is used. Since the inclination of the characteristic curve indicating the change of the emission electron current (I) with respect to (V) is all steep, any electron emission part is destroyed by overcurrent even under a gate voltage during normal driving, and from any electron emission part There is a fear that a problem arises that electrons are not emitted. As a field emission device capable of partially improving this non-uniformity, for example, an electric field having an electrical resistance layer provided between a cathode electrode and a cone-shaped electron emission portion in Japanese Patent Application Laid-Open No. 5 (1993) -47296. An emitting element is disclosed. Since the electrical resistive layer has the function of reducing the inclination of the I-V curve, by appropriately selecting the electrical resistivity of the electrical resistive layer, any electron emitting portion can emit electrons without being destroyed under the gate voltage during normal driving.

By the way, the electron emission characteristic of the field emission device having the structure shown in FIG. 39B is the tip of the electron emission section 205 from the edge 203 A of the gate electrode 203 forming the upper end of the opening 204. It depends heavily on the distance to. The distance is determined by the processing accuracy of the shape of the opening 204, the dimensional accuracy of the diameter, and the film thickness precision and coverage (step coverage) of the conductive material layer 205A on which the film is formed in [Step-30]. It also greatly depends on the shape precision of the release layer 206 serving as the undercoat.

Therefore, in order to manufacture a display device composed of a plurality of field emission elements having uniform characteristics, the conductive material layer 205A must be uniformly formed over the entire surface of the film to be formed. However, in the conventional vapor deposition apparatus, the conductive material particles are emitted from the evaporation source installed at one point with a certain magnification angle, so that the layer thickness and the coverage symmetry are different in the vicinity and the center of the film to be formed. . As a result, the height of the electron emitting portion becomes uneven or the apex position of the electron emitting portion is likely to deviate from the center of the opening 204, and the distance from the distal end of the conical electron emitting portion 205 to the gate electrode 203 is increased. It is difficult to suppress nonuniformity. Moreover, the nonuniformity of this distance occurs not only in the same manufacturing lot but also between manufacturing lots, which causes an image display characteristic of the display device, for example, uneven luminance of an image. In addition, since the conductive material layer 205A is usually formed to a thickness of about 1 μm or more, the deposition method requires a film formation time of several tens of hours, which makes it difficult to improve throughput and a large deposition apparatus. There are also problems such as things.

Moreover, it is also very difficult to form the peeling layer 206 uniformly over the whole surface of the large to-be-film-formed body by the diagonal vapor deposition method. It is also very difficult to deposit the exfoliation layer 206 with high precision so that the exfoliation layer 206 extends in an eave shape from the edge portion of the opening 204 formed in the gate electrode 203. In addition, the film formation of the release layer 206 is not only nonuniform in the support surface, but also nonuniformity between lots occurs easily. In addition, in order to manufacture a large area display device, it is very difficult not only to peel the peeling layer 206 over the entire glass substrate of a large area, but also the peeling of the peeling layer 206 may cause contamination and It leads to a decrease in production yield.

In addition, since the height of the conical electron emitting portion 205 is mainly defined by the film thickness of the conductive material layer 205A, the design freedom of the electron emitting portion 205 is low. In addition, since it is difficult to arbitrarily set the height of the electron emission section 205, when the distance from the electron emission section 205 to the gate electrode 203 is shortened, the film thickness of the insulating layer 202 must be made thin. do. However, if the thickness of the insulating layer 202 is made thin, the capacitance between the wirings (between the gate electrode 203 and the cathode electrode 201) cannot be made small, thereby increasing the burden on the electrical circuit of the display device as well as display. There is a problem that uniformity and image quality in the plane of the device are degraded.

This problem has not been solved at all in the method for producing a field emission device having an electric resistance layer, which is disclosed in Japanese Patent Laid-Open No. 5 (1993) -47296. This is because the method for manufacturing a field emission device disclosed in this patent publication is based on a conventional method for manufacturing a spin type field emission device based on the removal (lift off) of the conductive material layer. Moreover, in the manufacturing method disclosed in the said patent publication, the method of forming an electrical resistance layer also by the lift-off method can further increase the cause of a contamination.

Therefore, the present invention can solve the problems in the manufacture of the conventional spin type cold cathode field emission device, and a cold cathode electric field which can manufacture a plurality of cold cathode field emission devices having uniform and good electron emission characteristics by a simple method. An object of the present invention is to provide a light emitting device (hereinafter referred to as a "field emission device"), a manufacturing method thereof, and a cold cathode field emission display device (hereinafter referred to as a "display device") constructed using the field emission device. do.

BRIEF DESCRIPTION OF THE DRAWINGS The schematic diagram which shows the field emission element of Example 1;

2 is a schematic cross-sectional view showing a configuration example of a display device of the present invention.

3 (A) and 3 (B) are schematic cross-sectional views illustrating the method of manufacturing the field emission device of Example 1, FIG. 3 (A) is an opening forming step, and FIG. 3 (B) is a forming step of the resistor layer. Respectively shown.

4 (A) and 4 (B) are schematic cross-sectional views illustrating a method of manufacturing the field emission device of Example 1, following FIG. 3 (B), and FIG. 4 (A) shows a step of forming a mask material layer, Fig. 4B is a view showing a step of leaving a mask material layer in recesses, respectively.

5 (A) and 5 (B) are schematic cross-sectional views illustrating a method of manufacturing the field emission device of Example 1, following FIG. 4 (B). FIG. 5 (A) is a resistor having a tip-shaped cone shape. Fig. 5B is a view showing the step of forming the electron emitting portion, respectively.

6 (A) and 6 (B) are diagrams illustrating a mechanism for achieving a horn shape at the tip of the resistor layer, and FIG. 6 (A) is a conceptual diagram showing a change in the surface profile of an object to be etched as the etching proceeds. 6 (B) is a graph showing the relationship between the etching time and the thickness of an object to be etched at the opening center.

FIG. 7 is a schematic diagram showing the field emission device of Example 2. FIG.

8 (A) and 8 (B) are schematic cross-sectional views illustrating the method for manufacturing the field emission device of Example 2, FIG. 8 (A) until the formation process of the converging electrode, and FIG. 8 (B) of the openings. Figures showing the formation process, respectively.

9 (A) and 9 (B) are schematic cross-sectional views illustrating a method of manufacturing the field emission device of Example 2, following FIG. 8 (B). FIG. 9 (A) is a step of forming a resistor layer. 9 (B) shows a step of leaving a mask material layer in recesses, respectively.

10 (A) and 10 (B) are schematic cross-sectional views illustrating the method for manufacturing the field emission device of Example 2, following FIG. 9 (B), and FIG. 10 (A) is a resistor having a tip-shaped cone shape. The process of forming a layer, and FIG. 10 (B) respectively show a process of leaving a mask material layer in a recess.

11A and 11B are schematic cross-sectional views illustrating the manufacturing method of Example 3, in which Fig. 11A is a step of forming a resistor layer, and Fig. 11B is a step of forming a mask material layer. Respectively shown.

12 (A) and 12 (B) are schematic cross-sectional views illustrating the method for manufacturing the field emission device of Example 3, following FIG. 11 (B), and FIG. 12 (A) shows a mask material layer at the circumference thereof. Fig. 12 (B) shows a step of forming a resistor layer having a distal end portion having a horn shape.

13 (A) and 13 (B) are schematic cross-sectional views illustrating the method for manufacturing the field emission device of Example 3, following FIG. 12 (B), and FIG. 13 (A) shows a process of forming an electron emission section. 13 (B) is a diagram showing an isotropic etching step of the openings, respectively.

14 (A) and 14 (B) are schematic diagrams illustrating changes over time of the surface profile of an object to be etched, and FIG. 14 (A) is a diagram showing a case of using a mask material layer made of copper. Fig. 1 shows the case where a mask material layer made of a resist material is used, respectively.

15 is a schematic cross-sectional view illustrating the manufacturing method of Example 4. FIG.

16 is a schematic view of a field emission device obtained by the manufacturing method of Example 5. FIG.

17 (A) and 17 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 5, and FIG. 17 (A) shows a step of forming the planarization layer, and FIG. 17 (B) shows the bottom portion of the opening of the resistor layer. The figure which shows the process of embedding by each.

18 (A) and 18 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 5 following FIG. 17 (B), and FIG. 18 (A) is a step of forming an adhesive layer and a conductive material layer. 18 (B) each shows a step of forming a mask material layer.

19 (A) and 19 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 5 following FIG. 18 (B), and FIG. 19 (A) is a step of leaving a mask material layer in the main portion, FIG. 19. (B) is a figure which shows the formation process of an electron emission part, respectively.

20 is a schematic view of a field emission device obtained by the manufacturing method of Example 6. FIG.

21 (A) and 21 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 6, and FIG. 21 (A) is a step of embedding the bottom of the opening portion into the resistor layer, and FIG. 21 (B) is in close contact. The figure which shows the formation process of a layer, a conductive material layer, and a mask material layer, respectively.

22 (A) and 22 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 7, wherein FIG. 22 (A) shows the mask material layer up to the step of forming the mask material layer, and FIG. The figure which shows the process of leaving a layer, respectively.

23 (A) and 23 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 7 after FIG. 22 (B), and FIG. 23 (A) is a step of forming an electron emitting portion having a horn shape, FIG. 23B each shows an isotropic etching step of the insulating layer.

24 is a schematic cross-sectional view illustrating the manufacturing method of Example 8. FIG.

25 (A) and 25 (B) are views for explaining the technical background of Example 9, and FIG. 25 (A) is a conceptual diagram showing the change of the surface profile of the etching target material as the etching proceeds, and FIG. 25 (B). Is a conceptual diagram of a state in the middle of etching.

26 (A) and 26 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 9, and FIG. 26 (A) is a step of leaving a mask material layer in recesses, and FIG. 26 (B) is a conductive material layer. The figure which shows the state currently in the process of etching.

27 (A) and 27 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 9, following FIG. 26 (B), and FIG. 27 (A) is a step of forming an electron emitting portion having a horn shape, FIG. 27 (B) each show a change in the surface profile of an object to be etched as the etching proceeds.

28 is a schematic diagram of a field emission device obtained by the manufacturing method of Example 10.

29 (A) and 29 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 10; FIG. 29 (A) is a step of leaving a mask material layer in recesses; FIG. 29 (B) is a conductive material layer Figures showing the etching degree of each.

30 is a schematic view of a field emission device obtained by the manufacturing method of Example 11. FIG.

31 (A) and 31 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 11, and FIG. 31 (A) is a mask on the main portion of the conductive material layer until FIG. The figure which shows the process of leaving a material layer, respectively.

32 (A) and 32 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 12, and FIG. 32 (A) shows the mask material layer up to the step of forming the mask material layer, and FIG. The figure which shows the process of leaving a layer, respectively.

33 is a schematic cross-sectional view illustrating the manufacturing method of Example 13. FIG.

34 (A) and 34 (B) are schematic cross-sectional views illustrating the manufacturing method of Example 14, and FIG. 34 (A) is a step of leaving a mask material layer in recesses, and FIG. 34 (B) is a conductive material layer. The figure which shows the state currently in the process of etching.

35 is a schematic diagram of a field emission device obtained by the manufacturing method of Example 15.

36 (A), 36 (B) and 36 (C) are schematic cross-sectional views illustrating the manufacturing method of Example 15, FIG. 36 (A) until the forming step of the opening portion, and FIG. 36 (B) is the conductive material Process of leaving a mask material layer in the main part of the layer, and FIG. 36C shows a process of forming an electron emitting portion, respectively.

37 is a schematic partial cross-sectional view showing a general configuration of a conventional display device.

38 (A) and 38 (B) are schematic cross-sectional views for explaining an example of a conventional method for manufacturing a spin type field emission device. FIG. 38 (A) is a state in which an opening is formed, and FIG. 38 (B) is The figure which shows the state which formed the peeling layer on the gate electrode, respectively.

39 (A) and 39 (B) are schematic cross-sectional views for explaining an example of a method for manufacturing a conventional spin type field emission device following FIG. 38 (B), and FIG. 39 (A) shows growth of a conductive material layer. Fig. 39B is a view showing a state in which an unnecessary conductive material layer is removed like a peeling layer, respectively.

<Explanation of symbols for main parts of drawing>

10: support, l1: cathode electrode, 12: insulating layer, 13: gate electrode, 14, 24, 74, 104, 154: opening, 15, 15e, 25, 25e, 35, 35e, 55, 55e, 65, 75 105, 115: resistor layer, 16, 26, 36, 58, 58, 78, 108, 118, 158: mask material layer, 17, 27, 37: conductive thin film, 57, 77, 107, 117, 157: conductive Material layer (for electron emission part formation), 17e, 27e, 37e, 57e, 67e, 77e, 107e, 117e, 157e: electron emission part, 15A, 25A, 35A, 57A, 67A, 77A, 107A, 117A, 157A: Main part, 35B, 77B, 117B: Column part, 35C, 77C, 117C: Magnification part, 56, 56e, 66, 66e, 76, 76e, 106, 106e, 116, 116e, 156, 156e: Cohesion layer, 12: Insulation Layer, 20: second insulating layer, 21: convergence electrode, CP: cathode panel, AP: anode panel, 160: substrate, 161: phosphor layer, 162: anode electrode

The field emission device of the present invention for achieving the above object is

(A) a cathode electrode formed on the support,

(B) an insulating layer formed on the cathode electrode and the support,

(C) a gate electrode formed on the insulating layer,

(D) an opening penetrating through the gate electrode and the insulating layer,

(E) a resistor layer formed on the cathode electrode located at the bottom of the opening portion and having a tip-shaped tip portion;

(F) An electron emission portion formed of a conductive material having a work function smaller than that of the material constituting the resistor layer and reflecting the shape of the tip of the tip portion on the tip of the resistor layer.

Characterized in having a.

The manufacturing method of the field emission device of the present invention (hereinafter referred to as "manufacturing method according to the first aspect") is a method for manufacturing the field emission device of the present invention. In other words,

(a) forming a cathode electrode on the support;

(b) forming an insulating layer on the cathode electrode and the support;

(c) forming a gate electrode on the insulating layer,

(d) forming at least an opening in the insulating layer, the opening having the cathode electrode exposed at the bottom thereof;

(e) forming a resistor layer on the entire surface including the inside of the opening;

(f) forming a mask material layer on the resistor layer so as to shield an area of the resistor layer located at the central portion of the opening;

(g) Etch the resistor layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the resistor layer is higher than the etching rate in the direction perpendicular to the support of the mask material layer. Thereby forming a resistor layer having a horn shape in the opening portion,

(h) forming an electron emission section on the tip of the resistor layer, which is made of a conductive material having a lower work function than the material constituting the resistor layer and reflecting the horn shape of the tip;

Characterized in that it comprises a.

The step (g) is a kind of etchback process that uses the difference in the etching rates of the mask material layer and the conductive material layer. In addition, in this specification, the etching speed in the direction perpendicular | vertical with respect to a support body is only called "etching speed."

The display device of the present invention is a display device to which the field emission device of the present invention is applied. In other words,

Composed of a plurality of pixels,

Each pixel is composed of an anode electrode and a phosphor layer provided on a substrate to face a plurality of cold cathode field emission elements and a plurality of cold cathode field emission elements,

Each cold cathode field emission element

(A) a cathode electrode formed on the support,

(B) an insulating layer formed on the cathode electrode and the support,

(C) a gate electrode formed on the insulating layer,

(D) an opening penetrating through the gate electrode and the insulating layer,

(E) a resistor layer formed on the cathode electrode located at the bottom of the opening portion and having a tip-shaped tip portion;

(F) An electron emission portion formed of a conductive material having a work function smaller than that of the material constituting the resistor layer and reflecting the shape of the tip of the tip portion on the tip of the resistor layer.

Characterized in having a.

In the field emission element and the display device of the present invention, it is preferable that the resistor layer has a horn-shaped tip portion, and a portion below the tip portion, that is, a portion in contact with the cathode electrode 11, fills the bottom of the opening portion. That is, it is preferable that the resistor layer forms the pencil shape cut out as a whole. This is related to the intention of the present invention to suppress nonuniformity of electron emission characteristics of each electron emission section by interposing a resistor layer between the cathode electrode and the electron emission section. That is, by directly filling the bottom of the opening with the resistor layer, direct contact between the cathode electrode and the electron emitting portion in the opening can be reliably avoided. The horn shape of the tip of the resistor layer includes a cone shape or a pyramid shape. Which horn shape is to be achieved depends on the planar shape of the opening for the following manufacturing reasons. That is, if the planar shape of the opening is circular, at least the tip portion of the resistor layer is substantially conical, and if the planar shape of the opening is spherical, the shape is substantially pyramidal.

The electron emitting portion is composed of a conductive material having a lower work function (Ф) than the material constituting the resistor layer, but which conductive material is selected, the work function of the material constituting the resistor layer, the potential difference between the gate electrode and the electron emitting portion, and the desired material. It depends on the magnitude of the emitted electron current density. Representative constituent materials of the electron emission portion of the field emission device include tungsten (Ф = 4.55 eV), niobium (Ф = 4.02 to 4.87 eV), molybdenum (Ф = 4.53 to 4.95 eV), aluminum (Ф = 4.28), and copper ( Φ = 4.6), tantalum (Ф = 4.3), chromium (Ф = 4.5 eV), and silicon (Ф = 4.9).

In the field emission element and the display apparatus of this invention, it is preferable that the electrical resistivity of a resistor layer exists in the range of 1.0 kPa * cm -10MPa * cm. Therefore, in the manufacturing method which concerns on the 1st aspect of this invention, it is preferable to form a resistor layer in the process (e) using the material whose electrical resistivity is in the range of 1.0 kPa * cm-10 MPa * cm. The material constituting the resistor layer can be appropriately selected from materials capable of having an electrical resistivity in the above range. In particular, polysilicon can vary the electrical resistivity in a wide range depending on the impurity concentration. It is a preferable material for the reason that a method is established in a semiconductor manufacturing process.

In the field emission device and the display device of the present invention, a second insulating layer may be further formed on the gate electrode and the insulating layer, and a convergence electrode may be formed on the second insulating layer. In the so-called high-voltage type display device, in which the potential difference between the anode electrode and the cathode electrode is in the order of thousands of volts, the convergence electrode is installed to prevent the emission of the electron orbit emitted from the electron emission portion. It is a member. By increasing the convergence of the emission electron trajectory, crosstalk between the pixels is reduced, and in particular, color turbidity can be prevented in the case of color display, and the pixels can be miniaturized to achieve high definition of the display screen. .

And in the field emission element of this invention, although an opening penetrates through a gate electrode and an insulating layer, in a process (d) of the manufacturing method by a 1st aspect for manufacturing this field emission element, a cathode electrode is provided in a bottom part. The reason why the exposed openings are formed at least in the insulating layer is because it is assumed that the openings in the gate electrode and the openings in the insulating layer need not be formed at the same time. In the case where it is not necessary to simultaneously form the openings in the gate electrode and the openings in the insulating layer, for example, a gate electrode having an opening formed thereon is formed on the insulating layer from the beginning and a part of the insulating layer is formed within the openings. It is a case where an opening part is formed by removing. In addition, this "at least" meaning also applies to the process (d) of the manufacturing method by the 2nd aspect of this invention mentioned later, and the process (d) of the manufacturing method by the 3rd aspect of this invention.

The production method according to the first aspect of the present invention can be broadly divided into the first A and the first B aspects by the modification of the step (e). That is, in the manufacturing method according to the first aspect of the present invention, in the step (e), the recessed portion reflecting the step difference between the top surface and the bottom surface of the opening portion is generated on the surface of the resistor layer, and in the following step (f), the resistor layer is After the mask material layer is formed on the entire surface, the mask material layer is removed until the flat surface of the resistor layer is exposed, thereby leaving the mask material layer on the recessed portion. The surface of the mask material layer left in the recess is preferably approximately flat. Therefore, when the surface of the mask material layer is already substantially flat in the step formed on the entire surface of the conductive material layer, the mask material layer may be removed by an etch back method, an polishing method, or a combination of these methods under anisotropic etching conditions. When the surface of the mask material layer is not substantially flat at the step formed on the entire surface of the conductive material layer, the mask material layer may be removed by a polishing method. And in order to form the recessed part which reflects the level | step difference between the upper end surface and the bottom surface of an opening part on the surface of a resistor layer, it is preferable to form a resistor layer by the film forming method which is excellent in step coverage (step coverage property). As such a film forming method, the CVD method (chemical vapor deposition method) is particularly preferable.

The mask material layer in the manufacturing method according to the first aspect is a material which can set the etching rate in the next step (g) to be slower than the etching rate of the conductive material layer, and fluidity at an appropriate stage of formation so as to make the surface flat. It is composed of a material that can have. As a material which comprises a mask material layer, a resist material, SOG (spin on glass), and a polyimide resin are mentioned, for example, These materials can be apply | coated simply by a spin coating method. Alternatively, the material may be a material capable of flattening the surface by heating reflow after film formation such as BPSG (boro-phospho-silicate glass).

The manufacturing method according to the first B aspect of the present invention makes it possible to narrow the area of the conductive material layer shielded by the mask material layer in the manufacturing method according to the first A aspect. That is, in the manufacturing method according to the first B aspect of the present invention, in the step (e), a substantially funnel-shaped recess formed of a circumferential portion and an enlarged portion communicating with the upper end of the circumferential portion reflecting the step between the upper and lower surfaces of the opening portion It forms on the surface of a resistor layer, and in the following process (f), a mask material layer is formed in a circumference part. When the mask material layer is first formed on the entire surface of the resistor layer in the step (f), the manufacturing method according to the first aspect can be further divided into two methods depending on the method of leaving the mask material layer in the circumference. . That is, (1) removing the mask material layer and the resistor layer in a plane parallel to the surface of the support to leave the mask material layer only in the circumference, and (2) the mask material layer on the resistor layer and in the enlarged portion. It removes and leaves a mask material layer only in the circumference part. The method of (1) is possible by the etch back method or the polishing method by the conditions that the etching rate of a mask material layer and a resistor layer becomes equal. The method of (2) is also possible by dry etching or wet etching using an etching species capable of etching only the mask material layer without etching the resistor layer.

In the manufacturing method according to the first aspect, the formation of the resistor layer before the surface of the resistor layer, which grows approximately perpendicularly from the sidewall of the opening, contacts at approximately the center of the opening, in order to create a substantially funnel-shaped recess in the surface of the resistor layer. Stop it. For example, if the opening is cylindrical, the thickness of the resistor layer needs to be set smaller than the radius of the opening, so that a cylindrical circumference is formed. In this case, the diameter of the circumferential portion may be selected in the range of approximately 5 to 30%, more preferably approximately 5 to 10% of the diameter of the opening. In addition, in order to form the recessed part having a shape as mentioned above, it is preferable to form a resistor layer by the formation method in which thin film growth advances at substantially the same speed in all directions from the side wall surface of an opening part. In this respect, the CVD method is particularly preferable as a method of forming the resistor layer. The advantage of the CVD method over the vapor deposition method is that in the CVD method, it is present in the film forming atmosphere, unlike the vapor deposition method of depositing the deposited particles from the evaporation source located at one point and the possibility of greatly improving the throughput due to the fast film forming speed. Since any film can be formed at any point in contact with the source gas, it is relatively easy to form a film with a uniform film thickness and coverage over the entire surface of the film to be coated.

In any of the methods (1) or (2) of the manufacturing method according to the first aspect of the present invention, a layer of the minute mask material left in an extremely narrow region (i.e., the circumference) of the approximately center portion of the opening portion as a mask of the etch back process is finally obtained. Because of its function, the tip of the resistor layer formed is further sharpened. However, such a fine mask material layer is required to have sufficient etching resistance. In general, it is preferable that, when the etching rate of the etching rate of the mask material layer R _2, resistive material layer as R _1, the relationship 10R ₂ ≤R ₁ satisfied. That is, the etching rate R ₂ of the mask material layer is preferably about one tenth or less than the etching rate R ₁ of the resistor layer. For example, when the resistor layer is made of polysilicon, at least one of copper (Cu), gold (Au), or platinum (Pt) may be used as the mask material layer.

When forming a mask material layer in the whole surface of a resistor layer in the manufacturing method by 1st aspect, it is necessary to employ | adopt the film forming method which can embed a mask material layer also inside the narrow peripheral part. Electrolytic plating or electroless plating is preferable. In the case of employing the sputtering method or the CVD method, it is particularly desirable to devise a scheme for improving the step coverage. For example, when employing a sputtering method, it is preferable to perform so-called high temperature reflow sputtering or high pressure sputtering at a film forming temperature of approximately 300 ° C or higher. In the case of employing the CVD method, it is preferable to use a bias ECR (electron cyclotron resonance) plasma apparatus.

In step (h) of the manufacturing method according to the first aspect of the present invention, an electron emission is made of a conductive material having a work function having a lower work function than the material constituting the resistor layer on the tip of the resistor layer and reflecting the shape of the tip of the tip. As a method of forming a part, vapor phase thin film formation methods, such as a vapor deposition method, CVD method, sputtering method, and ion plating method, or liquid thin film formation methods, such as an electrolytic plating method and an electroless plating method, are mentioned. In the thin film formation method, a thin film made of a conductive material on the entire surface of the film to be formed (hereinafter referred to as "conduction" except for the case where an electron emitting portion is selectively formed only at the tip of the resistor layer, such as a selective vapor deposition method or a selective plating method. Thin film ") is formed. Therefore, for example, when the gate electrode or the converging electrode is exposed on the surface of the film to be formed at the time of forming the thin film, it is necessary to devise that the gate electrodes or the converging electrodes are not shorted by the conductive thin film. In order to prevent the short circuit, (1) the conductive material layer formed on the mask layer is removed (lifted off) together with the mask layer by covering the gate electrode or the converging electrode with the mask layer prior to forming the conductive thin film, or ( 2) After forming the conductive thin film, the electron emission portion is protected by the mask layer and the conductive thin film on the gate electrode or the convergence electrode is removed, or (3) the material layer constituting the gate electrode or the convergence electrode is not patterned. After forming and forming a conductive thin film, the material which comprises a gate electrode or a converging electrode, and the conductive material layer are patterned together.

The method for producing a field emission device according to the second aspect of the present invention (hereinafter referred to as "manufacturing method according to the second aspect") is, for example, the electric field described in Japanese Patent Laid-Open No. 5-47396 described in the prior art section. The field emission device having a configuration similar to that of the emission device can be manufactured at very low cost with very high precision, manufacturing yield, and reliability. That is, the manufacturing method according to the second aspect of the present invention

(a) forming a cathode electrode on the support;

(b) forming an insulating layer on the cathode electrode and the support;

(c) forming a gate electrode on the insulating layer,

(d) forming at least an opening in the insulating layer, the opening having the cathode electrode exposed at the bottom thereof;

(e) embedding the bottom of the opening portion into the resistor layer;

(f) forming a conductive material layer for forming an electron emission portion on the entire surface including the remaining portion of the opening;

(g) forming a mask material layer on the conductive material layer so as to shield an area of the conductive material layer located at the central portion of the opening;

(h) conductive by etching the conductive material layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the conductive material layer is faster than the etching rate in the direction perpendicular to the support of the mask material layer. A process of forming an electron emitting portion made of a material layer and having a tip-shaped tip portion

Characterized in that it comprises a.

In the manufacturing method according to the second aspect of the present invention, the electron-emitting portion may have a horn shape as a whole, or only the tip portion thereof may have a horn shape, such as a shaved pencil. The horn shape includes a cone shape or a pyramid shape. Which horn shape is to be achieved depends on the planar shape of the opening for the following manufacturing reasons. In other words, if the planar shape of the opening portion is circular, at least the tip portion of the resistor layer becomes a substantially conical shape.

As a manufacturing method by a 2nd aspect of this invention, in a process (e), it is preferable to form a resistor layer using the material whose electrical resistivity is in the range of 1.0 kPa * cm-10 MPa * cm. In the step (e), it is preferable to form such a resistor layer on the entire surface including the inside of the opening, and then etch the resistor layer to fill the bottom of the opening with the resistor layer. Alternatively, when the surface of the resistor layer is to be flattened, the resistor layer is formed on the entire surface including the inside of the opening in the step (e), and the planarization layer is formed on the entire surface of the resistor layer so that the surface is substantially flat. By etching both of these layers under the condition that the etching rates of the planarization layer and the resistor layer become approximately equal, the bottom of the opening portion can be filled with a resistor layer having a flat upper surface.

In the manufacturing method according to the second aspect of the present invention, in step (d), an opening having an inclination angle θ ₁ of the side wall with respect to the surface of the cathode electrode is formed in the insulating layer, and in the subsequent step (h), the cathode An inclination angle θ ₂ of the inclined surface with respect to the surface of the electrode may form a horn-shaped electron emission part satisfying a relationship of θ ₁ <θ ₂ <90 °. The step (h) is a kind of etchback process as described above, and if the sidewall of the opening is perpendicular to the surface of the cathode electrode, the etching residue of the conductive material layer remains at the corner of the opening, depending on the etching conditions. There is a fear that the electron emission section and the gate electrode having the tip of the shape are short-circuited by the etching residue. In order to avoid this short circuit, if etching is continued for a long time until the etching residue is sufficiently removed, the height of the electron emission section is also reduced at the same time, thereby increasing the distance from the end of the gate electrode to the tip of the electron emission section, thereby degrading the electron emission efficiency. .

However, when the inclination angle θ ₁ of the side wall of the opening is defined as described above, etching species tend to enter the resistor layer on the side wall as compared with the case where the side wall is perpendicular to the surface of the cathode electrode. In the etch back process, anisotropic etching conditions are generally employed in which ions, which are etching species, are incident substantially perpendicularly to the etched object, so that the etching species easily enters, which shortens the etching time, which means that sidewalls of the openings are exposed in a short time. do. Accordingly, it is possible to prevent shorting of the gate electrode and the electron emitting portion without reducing the height of the resistor layer of the opening, that is, the height of the electron emitting portion (without decreasing the electron emission efficiency).

Anisotropic etching is the most common method of forming the opening in the insulating layer, and in this etching, the sidewall of the opening can be inclined by utilizing the effect of lowering the etching rate by the reactive reaction by-product. In particular, in the case where a silicon compound such as a silicon oxide material or a silicon nitride material is used as a constituent material of the insulating layer, a fluorocarbon-based etching gas is generally used as the etching gas, and a carbon-based polymer may be used as the deposition material. . In order to increase the deposition amount of the carbon-based polymer in such an etching reaction system, the etching gas may be a source of oxygen-based chemical species that increases the flow rate of the fluorocarbon-based etching gas or promotes combustion of the carbon-based polymer. Reduced flow rate, shorten average free stroke of ions by increasing gas pressure, lower RF power for plasma excitation, or increase frequency of RF power for plasma excitation By suppressing the removal of the polymer or by lowering the temperature of the etched object, a means such as lowering the vapor pressure of the carbon-based polymer can be devised. However, if the deposition amount of the carbon-based polymer is excessively large, the etching does not proceed at a practical rate, so the above means need to be taken within a range that can attain a practical etching rate.

The manufacturing method according to the second aspect of the present invention can also be broadly divided into the second A aspect and the second B aspect by the modification of the step (f), similarly to the manufacturing method according to the first aspect described above. That is, in the manufacturing method according to the second aspect of the present invention, in the step (f), the recessed portion reflecting the step difference between the top surface and the bottom surface of the opening is formed on the surface of the conductive material layer for forming the electron emission portion, and the subsequent step ( In g), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer is removed until the flat surface of the conductive material layer is exposed, thereby leaving the mask material layer in the recess. In the manufacturing method according to the first aspect described above, recesses are formed on the surface of the resistor layer, whereas in the manufacturing method according to the second aspect, the recesses are generated on the surface of the conductive material layer. The type of the mask material layer, the method of forming the mask material layer and the method of removing the mask material layer are the same.

The manufacturing method according to the second aspect of the present invention makes it possible to narrow the area of the conductive material layer shielded by the mask material layer than in the manufacturing method according to the second A aspect. That is, in the manufacturing method according to the second B aspect of the present invention, in the step (f), a substantially funnel-shaped recessed portion consisting of a circumferential portion and an enlarged portion communicating with the upper end of the circumferential portion, reflecting the step between the top and bottom surfaces of the opening portion. Is produced on the surface of the conductive material layer for forming an electron emission portion, and in the subsequent step (g), a mask material layer is formed in the circumference portion. In the case of first forming a mask material layer on the entire surface of the conductive material layer in the step (f), the manufacturing method according to the second B aspect can be further divided into two methods depending on the method of leaving the mask material layer in the circumference. . That is, (1) removing the mask material layer and the conductive material layer in a plane parallel to the surface of the support to leave the mask material layer only in the circumference, and (2) the mask material layer on the resistor layer and in the enlarged portion. This method is to leave the mask material layer only in the circumference. In the manufacturing method according to the first embodiment described above, recesses are formed on the surface of the resistor layer, while in the manufacturing method according to the second embodiment, the recesses are formed on the surface of the conductive material layer. The method of forming the recess, the type of mask material layer, the method of forming the mask material layer, and the method of removing the mask material layer are the same. And after forming such a recessed part, it is especially preferable to form a conductive material layer by CVD method at a process (f).

In either (1) or (2) of the manufacturing method according to the second aspect of the present invention, a layer of the minute mask material left in an extremely narrow region (i.e., the circumference) of the approximately center portion of the opening portion finally functions as a mask of the etch back process. Therefore, the tip of the electron emitting portion formed is further sharpened. However, such a fine mask material layer is required to have sufficient etching resistance. In general, it is preferable that, when the etching rate of the etching rate of the mask material layer R _2, the conductive material layer by R _3, the relationship 10R ₂ ≤R ₃ satisfied. That is, the etching rate R ₂ of the mask material layer is preferably about one tenth or less than the etching rate R ₃ of the conductive material layer. For example, the conductive material layer may include tungsten (W), titanium (Ti), niobium (Nb), molybdenum (Mo), tantalum (Ta), chromium (Cr), or a compound thereof (for example, nitride such as TiN or WSi). ₂ , MoSi ₂ , TiSi ₂ , or a silicide such as TaSi ₂ ), at least one of copper (Cu), gold (Au), or platinum (Pt) may be used as the mask material layer.

In the manufacturing method according to the second aspect of the present invention, the adhesion layer may be formed such that the adhesion between the conductive material layer for forming an electron emission portion and the insulating layer in the manufacturing process is improved, and the conductive material layer is formed with good step coverage. have. That is, before forming the conductive material layer for electron emission part formation in a process (f), an adhesion layer can be formed in the whole surface containing the remainder of an opening part. This method is called a manufacturing method according to Embodiment 2C of the present invention. As the adhesion layer, a layer used as a barrier metal in a conventional semiconductor process may be used, and may be a single type of material layer or a composite layer in which a plurality of types of material layers are combined.

In the manufacturing method according to the second aspect, in the step (h), the conductive material layer, the mask material layer, and the adhesive layer under anisotropic etching conditions in which the etching rate of the conductive material layer and the etching rate of the adhesion layer are higher than the etching rate of the mask material layer. It is preferable to etch. The conductive material layer and the adhesion layer may be removed at an approximately equivalent etching rate under the same etching conditions, or even if the etching rate R ₃ of the conductive material layer or the like is faster, 5 times the etching rate R ₄ of the adhesion layer. Particular preference is given to selecting within a fold (R ₄ ≦ R ₃ ≦ 5R ₄ ). This etching is performed when etching of the conductive material layer or the like proceeds to expose the adhesion layer to most of the etching target surface, and a large amount of the etching reaction products of the adhesion layer are generated and a part thereof adheres to the surface of the conductive material layer or the like. This is because if the vapor pressure of the reaction product is too low, there is a high possibility that the etching reaction product itself functions as an etching mask and interferes with etching of the conductive material layer or the like. Most simply, if the conductive material layer and the adhesive layer are made of the same conductive material, the etching rates of both layers can be made substantially the same. However, in the case where the conductive material layer and the adhesion layer are composed of the same conductive material, it is particularly preferable to form the adhesion layer by the sputtering method and to form the conductive material layer by the CVD method. When the conductive material layer for forming the electron emission portion and the adhesion layer are made of the same conductive material, it can be approximately R ₃ = R ₄ .

In the manufacturing method according to Embodiments 2A to 2C, the conductive material layer is formed by the CVD method with excellent step coverage, since the recessed portion reflecting the step between the top and bottom surfaces of the opening is formed on the surface of the conductive material layer. It is particularly preferable to.

The manufacturing method according to the third aspect of the present invention also provides a field emission device having a configuration similar to that of the field emission device described in Japanese Patent Application Laid-open No. Hei 5-47396 described in the prior art. It is reliable and can be manufactured at low cost. That is, the manufacturing method by the 3rd aspect of this invention,

(a) forming a cathode electrode having a resistor layer on its surface on a support;

(b) forming an insulating layer on the cathode electrode and the support;

(c) forming a gate electrode on the insulating layer,

(d) forming at least an opening in the insulating layer an opening in which the resistor layer is exposed at the bottom;

(e) forming a conductive material layer for forming an electron emission portion on the entire surface including the inside of the opening;

(f) forming a mask material layer on the conductive material layer so as to shield an area of the conductive material layer located at the central portion of the opening;

(g) conductive by etching the conductive material layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the conductive material layer is faster than the etching rate in the direction perpendicular to the support of the mask material layer. A process of forming an electron emitting portion made of a material layer and having an end portion having an horn shape on a resistor layer

Characterized in that it comprises a.

In the manufacturing method according to the third aspect of the present invention, in the step (a), the position where the cathode electrode is formed and the position where the resistor layer is formed may be completely coincident or slightly shifted. However, when slightly shifted, the cathode electrodes constituting the separate pixels of the resistor layer should not be short-circuited, and the electron emission section and the cathode electrode should not be directly contacted. In order to completely match the formation positions of both, it is most simple to form a laminate of the material layer constituting the cathode electrode and the material layer constituting the resistor layer, and pattern the laminate using a common processing mask. On the other hand, when the patterning of the cathode electrode and the patterning of the resistor layer are performed in separate processes, the formation position of both is usually slightly shifted depending on the alignment accuracy.

In the manufacturing method which concerns on the 3rd aspect of this invention, in a process (a), it is preferable to form a resistor layer using the material whose electrical resistivity is in the range of 1.0 kPa * cm-10 MPa * cm.

In the manufacturing method according to the third aspect of the present invention, in the step (d), an opening portion having an inclination angle θ ₁ of the side wall with respect to the surface of the cathode electrode is formed in the insulating layer,

In the subsequent step (g), the inclination angle θ ₂ of the inclined surface with respect to the surface of the cathode electrode can form a horn-shaped electron emission portion satisfying the relationship of θ ₁ <θ ₂ <90 °.

The manufacturing method according to the third aspect of the present invention can also be broadly divided into the third A and third B aspects by the modification of the step (e), as in the manufacturing method according to the first aspect described above. That is, in the manufacturing method according to the third aspect of the present invention, in the step (e), the recessed portion reflecting the step between the top surface and the bottom surface of the opening is formed on the surface of the conductive material layer for forming the electron emission portion, and the subsequent step ( In f), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer is removed until the flat surface of the conductive material layer is exposed, thereby leaving the mask material layer in the recess. In the manufacturing method according to the third aspect, the type of mask material layer, the method for forming the mask material layer, and the method for removing the mask material layer are as described with reference to the manufacturing method according to the first aspect.

The manufacturing method according to the third aspect of the present invention makes it possible to narrow the area of the conductive material layer shielded by the mask material layer than in the manufacturing method according to the third aspect. That is, in the manufacturing method according to the third aspect of the present invention, in the step (e), a substantially funnel-shaped recessed portion consisting of a circumferential portion and an enlarged portion communicating with the upper end of the circumferential portion, reflecting a step between the top and bottom surfaces of the opening Is produced on the surface of the conductive material layer for forming the electron emission portion, and in the subsequent step (f), a mask material layer is formed in the circumference portion. When the mask material layer is first formed on the entire surface of the conductive material layer in the step (e), the manufacturing method according to the third embodiment can be further divided into two methods depending on the difference in the method of leaving the mask material layer in the circumference. . That is, (1) removing the mask material layer and the conductive material layer in a plane parallel to the surface of the support to leave the mask material layer only in the columnar portion, and (2) the mask material on the conductive material layer and in the enlarged portion. By removing the layer, the mask material layer is left only in the circumference. In the manufacturing method according to the third aspect, the type of mask material layer, the method for forming the mask material layer, the method for removing the mask material layer, and the relationship between the etching rate of the conductive material layer and the mask material layer are described in the manufacturing method according to the second B aspect. As described in relation to FIG.

In the manufacturing method according to the third aspect of the present invention, the adhesion layer is formed so as to improve the adhesion between the conductive material layer for forming the electron emission portion and the insulating layer in the manufacturing process, and the conductive material layer is formed into a film with good step coverage. You may. That is, in step (e), the adhesion layer can be formed on the entire surface including the remaining portion of the opening before forming the conductive material layer for forming the electron emission portion. This method is called manufacturing method by 3rd aspect of this invention. In the manufacturing method according to the third C aspect, the relationship between the type of the adhesive layer and the etching rate of the conductive material layer and the adhesive layer is as described with reference to the manufacturing method according to the second C aspect.

In the manufacturing method according to the third aspect to the third aspect, the recessed portion reflecting the step between the top surface and the bottom surface of the opening portion needs to be formed on the surface of the conductive material layer, so that the conductive material layer is formed by the CVD method with excellent step coverage. It is especially preferable to form.

In the field emission device of the present invention, the display device, and the manufacturing method according to all aspects of the present invention, the support constituting the field emission device may be formed of at least a surface of an insulating member, and the glass substrate and the glass substrate on which the insulating film is formed. A quartz substrate, a quartz substrate having an insulating film formed on its surface, or a semiconductor substrate having an insulating film formed on its surface can be used.

In the display device of the present invention, the substrate should have at least a surface composed of an insulating member, and a glass substrate, a glass substrate having an insulating film formed on its surface, a quartz substrate, a quartz substrate having an insulating film formed on its surface, and a semiconductor substrate having an insulating film formed on its surface may be used. Can be.

As a constituent material of the insulating layer, SiO ₂ , SiN, SiON, a glass paste cured product can be used alone or as appropriately laminated. Known processes, such as a CVD method, a coating method, a sputtering method, and a printing method, can be used for film forming of an insulating layer.

The gate electrode, the cathode electrode, and the convergence electrode include tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), copper (Cu), and silver. Metal layers such as (Ag), alloy layers containing these metal elements, or compounds containing these metal elements (for example, nitrides such as TiN or silicides such as WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ ), or diamond It can form using the semiconductor layer of. However, in the present invention, when the resistive layer or the electron emitting portion is formed by etching, these electrodes may be exposed so that a material capable of securing the etching selectivity with respect to the material constituting the resistive layer or the electron emitting portion is selected. There is a need.

The conductive material layer for forming the electron emission portion or the electron emission portion is tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), copper Metal layers such as (Cu), silver (Ag), alloy layers containing these metal elements, or compounds containing these metal elements (for example, nitrides such as TiN, WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi _2, etc. It can be formed using a semiconductor layer such as silicide) or diamond.

[Examples of the Invention]

DESCRIPTION OF EMBODIMENTS Hereinafter, the present invention will be described according to embodiments of the invention (hereinafter referred to as embodiments) with reference to the drawings.

Example 1

Example 1 relates to the field emission device of the present invention, the display device of the present invention having such a field emission device, and the method of manufacturing the field emission device according to the first aspect of the present invention. A typical partial sectional view of the field emission element of Example 1 is shown in FIG. 1, and a typical partial sectional view of the display device is shown in FIG. Moreover, the manufacturing method of the field emission element is shown to FIG. 3 (A), FIG. 3 (B), FIG. 4 (A), FIG. 4 (B), FIG. 5 (A), FIG. 5 (B), FIG. And FIG. 6 (B).

In this field emission element, as shown in FIG. 1, the cathode electrode 11 which consists of chromium (Cr) is formed on the support body 10 which consists of glass substrates, for example. In practice, the cathode electrode 11 is arranged in a predetermined direction on the support 10 as a plurality of strip-shaped layers. An insulating layer 12 made of, for example, SiO ₂ is formed on the cathode electrode 11 and the support 10, and a gate electrode 13 made of, for example, chromium (Cr) is formed on the insulating layer 12. It is. In practice, a plurality of gate electrodes 13 are formed in a band shape on the insulating layer 12 and are arranged in a predetermined direction. The arrangement direction of the gate electrode 13 is generally a direction orthogonal to the arrangement direction of the cathode electrode 11. Openings 14 penetrating these two members are formed in the gate electrode 13 and the insulating layer 12, and sidewalls of the openings formed in the insulating layer 12 are receded from the opening ends of the gate electrode 13. A resistor layer 15e is formed on the cathode electrode 11 located at the bottom of the opening 14. The tip portion of the resistor layer 15e has a horn shape, specifically, a cone shape, and a portion of the resistor layer 15e closer to the cathode electrode 11 than the tip portion fills the opening 14. Therefore, the resistor layer 15e has the pencil shape which cut off the front as a whole. The resistor layer 15e is made of, for example, polysilicon containing phosphorus (P) as an impurity at a concentration of 10 ¹⁹ / cm 3, and the electrical resistivity is 1.0 kPa · cm. On the tip end of the resistor layer 15e, an electron emission section 17e is formed. The electron emitting portion 17e is made of a material having a lower work function than the polysilicon constituting the resistor layer 15e, more specifically tungsten (W). The thickness of the electron emission section 17e is about 0.01 μm and is formed to reflect the shape of the tip of the tip of the resistor layer 15e.

In addition, although the conductive thin film 17 is shown on the gate electrode 13 in FIG. 1, the conductive thin film 17 is made of the same material as the electron emitting portion 17e and according to the formation of the electron emitting portion 17e. Formed layer. Although the conductive thin film 17 on the gate electrode 13 may be removed by a suitable method after the electron emitting portion 17e is formed, the pattern of the conductive thin film 17 is substantially the same as that of the gate electrode 13 to short-circuit the gate electrodes 13. The structure which can prevent this is employ | adopted.

The display device of the first embodiment is a device to which the above-described field emission device is applied and is composed of a plurality of pixels as shown in FIG. Each pixel includes a plurality of the aforementioned field emission devices and an anode electrode 162 and a phosphor layer 161 disposed on the substrate 160 so as to face each other. The anode electrode 162 is formed to cover the phosphor layer 161 formed of aluminum and having a predetermined pattern on the substrate 160 made of glass. The stacking order of the phosphor layer 161 and the anode electrode 162 on the substrate 160 may be reversed, but in this case, the anode electrode 162 is placed in front of the phosphor layer 161 as viewed from the viewing side of the display device. Therefore, the anode electrode 162 needs to be made of a transparent conductive material such as ITO (indium tin oxide).

In the actual display device configuration, the field emission device includes the cathode panel CP, the anode electrode 162, and the phosphor layer 161 are components of the anode panel AP, and the cathode panel CP and the anode panel AP It joins through a frame (not shown), and the space enclosed by both panels and the frame is exhausted in a high vacuum state. A relatively negative voltage is applied to the electron emission section 17e from the scanning circuit 163 through the cathode electrode 11 and the resistor layer 15e, and the control circuit 164 is applied to the gate electrode 13. A relatively positive voltage is applied from), and a constant voltage higher than the gate electrode 13 is applied to the anode electrode 162 from the acceleration power supply 165. When displaying on the display device, a video signal is input to the control circuit 164 and a scan signal is input to the scanning circuit 163. Electron " e " is drawn out from the distal end of the electron emission section 17e by an electric field generated when a voltage is applied to the cathode electrode 11 and the gate electrode 13. When the electron "e" is attracted to the anode electrode 162 and collides with the phosphor layer 161, the phosphor layer 161 emits light to obtain a desired image.

Hereinafter, the manufacturing method of the field emission element which concerns on Example 1 is shown in FIG. 3 (A), FIG. 3 (B), FIG. 4 (A), FIG. 4 (B), FIG. 5 (A), FIG. 5 (B), It demonstrates with reference to FIG. 6 (A) and FIG. 6 (B).

[Step-100]

First, as an example, a cathode electrode 11 made of chromium (Cr) is provided on a support 10 formed by forming a SiO ₂ layer having a thickness of about 0.6 μm on a glass substrate. Specifically, a plurality of band-shaped cathode electrodes 11 extending in parallel in the row direction can be formed by depositing a chromium layer on the support 10 by, for example, sputtering and patterning the chromium layer. have. The width of the cathode electrode 11 is 50 μm, for example, and the space between the electrodes is 30 μm, for example. An example of the sputtering conditions of the chromium layer is shown in Table 1 below, and an example of the RIE conditions in the case of performing the patterning of the chromium layer by, for example, RIE (reactive ion etching) method is shown in Table 2 below.

Table 1

Ar flow 100SCCM pressure 5 Pa DC power 2 kW Sputtering temperature 200 ℃

TABLE 2

Cl ₂ flow 100SCCM O ₂ flow rate 100SCCM pressure 0.7 Pa RF power 0.8 kW (13.56 MHz) Etching temperature 60 ℃

Next, an insulating layer 12 made of SiO ₂ is formed on the cathode electrode 11 and the support 10 by plasma CVD. Table 3 below shows an example of CVD conditions when TEOS (tetraethoxysilane) is used as the source gas. The thickness of the insulating layer 12 shall be about 1 micrometer.

TABLE 3

TEOS flow rate 800SCCM O ₂ flow rate 600SCCM pressure 1100 Pa RF power 0.7 kW (13.56 MHz) Production temperature 400 ℃

Next, the gate electrode 13 is formed on the insulating layer 12. Specifically, a plurality of strip-shaped gates extending in parallel to the column direction by depositing a titanium nitride (TiN) layer on the insulating layer 12 by DC sputtering and patterning the TiN layer, for example. The electrode 13 can be formed. The width of the gate electrode 13 is 50 μm, for example, and the space between the electrodes is 30 μm, for example. An example of the DC sputtering conditions of the TiN layer is shown in Table 4 below, and an example of the RIE conditions when the TiN layer is patterned by, for example, the RIE method is described below.

Table 4

Ar flow 30SCCM N ₂ flow rate 60SCCM pressure 0.67 Pa DC power 3 kW Sputtering temperature 200 ℃

Table 5

Cl ₂ flow 150SCCM Ar flow rate 90SCCM pressure 35 Pa RF power 0.7 kW (13.56 MHz)

Next, an opening 14 penetrating the gate electrode 13 and the insulating layer 12 is formed in an overlapping region of the cathode electrode 11 and the gate electrode 13, that is, one pixel region. The planar shape of the opening 14 is circular with a diameter of 0.3 μm. The openings 14 are usually formed in about 500 to 5000 pieces in one pixel area. In order to form the openings 14, using the resist layer formed by conventional photolithography techniques as a mask, first, openings are formed in the gate electrode 13 by RIE using a chlorine-based etching gas. Openings are formed in the insulating layer 12 by the RIE method using a fluorocarbon etching gas. RIE conditions when forming the opening 14 in the gate electrode 13 are as shown in Table 5. An example of RIE conditions at the time of forming the opening 14 in the insulating layer 12 is shown in Table 6 below. The resist layer after completion of the RIE is removed by ashing. An example of ashing conditions is shown in Table 7 below. In this way, the structure shown in FIG. 3 (A) can be obtained.

Table 6

C ₄ F ₈ Flow 30SCCM CO flow rate 70SCCM Ar flow 300SCCM pressure 7.3Pa RF power 1.3 kW (13.56 MHz) Etching temperature 20 ℃

TABLE 7

O ₂ flow rate 1200SCCM pressure 75 Pa RF power 1.3 kW (13.56 MHz) Ashing temperature 300 ℃

[Process -110]

Next, as shown in FIG. 3B, the resistor layer 15 is formed on the entire surface including the inside of the opening 14. Here, as the resistor layer 15, a polysilicon layer having a thickness of about 0.4 m is formed by a reduced pressure CVD method. Film-forming conditions are illustrated in Table 8 below. Under this condition, PH ₃ is included as a dopant gas in the film formation atmosphere, and phosphorus (P) as an impurity is introduced at the concentration of about 10 ¹⁹ / cm 3 at the same time as the film formation. In addition, the recessed part 15A which reflects the level | step difference between the upper end surface and the bottom surface of the opening part 14 is formed in the surface of the resistor layer 15 formed at this time. After completion of film formation, furnace annealing or rapid thermal annealing (RTA) is performed to activate impurities. Here, annealing is performed at 600 degreeC and electric resistivity is made into the order of about 1.0 kPa * cm. There is no problem in the heat resistance of the glass which comprises the support body 10, and the chromium which comprises the cathode electrode 11 at this temperature.

Table 8

SiH ₄ flow 300SCCM PH ₃ flow rate 15SCCM He flow rate 50SCCM pressure 350 Pa Growth temperature 550 ℃

[Process -120]

Next, as shown in Fig. 4A, a mask material layer 16 having a thickness of about 0.35 mu m is formed on the entire surface of the resistor layer 15 so as to have a substantially flat surface.

[Process -130]

Subsequently, as illustrated in FIG. 4B, the mask material layer 16 is etched in the recessed portion 15A by etching the mask material layer 16 until the flat surface of the resistor layer 15 is exposed. Leave RIE conditions are illustrated in Table 9 below. The mask material layer 16 absorbs the recessed portions 15A of the resistor layer 15 to achieve a substantially flat surface, and is formed so as to shield the area of the resistor layer 15 located at the center of the opening 14. have.

Table 9

Ar flow 50SCCM O ₂ flow rate 80SCCM pressure 26.7 Pa RF power 120 W (13.56 MHz)

[Process -140]

Next, as shown in Fig. 5A, the resistor layer 15 is etched. Etching conditions are illustrated in Table 10 below. This etching is performed under anisotropic etching conditions in which the etching rate of the resistor layer 15 is faster than the etching rate of the mask material layer 16.

Table 10

Etching equipment RF Bias Applied ECR Etching Equipment Cl ₂ flow 120SCCM O ₂ flow rate 4SCCM pressure 4Pa Microwave power 1.2 kW (13.56 MHz) RF bias power 70 W (2 MHz) Etching temperature 20 ℃

[Process -150]

Next, as shown in Fig. 5B, an electron emission section 17e is formed on the tip of the resistor layer 15e. Here, for example, a tungsten layer having a thickness of about 0.01 μm is formed into a film by sputtering to form a conductive thin film 17. An example of sputtering conditions for forming a tungsten layer is shown in Table 11 below. By the sputtering method, the incidence direction of the layer-forming species on the surface of the film forming body (layer forming body) can coincide with the direction substantially perpendicular to the support 10, and thus the sidewall of the opening 14 has a conductive material layer. The conductive thin film 17 is formed only on the gate electrode 13 and the insulating layer 12 and on the front end portion of the resistor layer 15e without depositing any of these materials. The portion formed in the tip portion of the resistor layer 15e in the conductive thin film 17 functions as the electron emission portion 17e. The conductive thin film 17 formed on the gate electrode 13 and the insulating layer 12 is removed leaving a portion on the gate electrode 13 so that adjacent gate electrodes 13 are not shorted.

Table 11

Ar flow 200SCCM pressure 0.67 Pa DC power 3 kW Sputtering temperature 200 ℃

Thereafter, when the sidewall of the opening formed in the insulating layer 12 is retracted in the opening 14 under isotropic etching conditions, the field emission device shown in FIG. 1 is completed. Isotropic etching can be performed by dry etching using radical as the main etching species or wet etching using etching liquid, such as chemical dry etching. As etching liquid, the mixed liquid whose volume ratio of 49% hydrofluoric acid aqueous solution and pure water is 1: 100 can be used, for example. The isotropic etching of the insulating layer 12 can also be performed before the formation of the tungsten layer by the above-mentioned sputtering method.

Subsequently, the display device is manufactured by combining the cathode panel CP in which a plurality of such field emission elements are formed with the anode panel AP. Specifically, a frame having a height of about 1 mm made of ceramics or glass is prepared, and a seal material made of frit glass is applied between the frame and the anode panel AP and the frame and the cathode panel CP. What is necessary is just to bake and bake at about 450 degreeC for 10 to 30 minutes. Then, the exhaust (排氣) the interior of the display device until a degree of vacuum of about 10 ^-4 Pa by an appropriate method and sealed.

Here, the mechanism in which the resistor layer 15e having the tip portion having a horn shape is formed in [Step-140] will be described with reference to Figs. 6 (A) and 6 (B). FIG. 6 (A) is a schematic diagram showing how the surface profile of an etched object changes at regular intervals as the etching progresses, and FIG. 6 (B) shows the relationship between the etching time and the thickness of the etching target at the opening center. It is a graph. The thickness of the mask material layer at the center of the opening is h _l , and the height of the resistor layer at the center of the opening is h ₂ .

Under the etching conditions shown in Table 10, the etching rate of the resistor layer 15 is naturally faster than the etching rate of the mask material layer 16 made of the resist material. In the region where the mask material layer 16 does not exist, the resistive layer 15 immediately begins to be etched, and the surface of the etched object (here, the resistive layer 15) quickly descends. In contrast, in the region where the mask material layer 16 is present, unless the mask material layer 16 is removed first, the etching of the resistor layer 15 underneath does not start, so that the mask material layer 16 is etched. While the rate of decrease in the thickness of the etched object (here, the mask material layer 16) is slow (h ₁ reduction interval), the rate of decrease in the thickness of the etched object for the first time when the mask material layer 16 disappears is masked. It is as fast as the region where the material layer 16 is not present (h ₂ reduction section). The start time of the h ₂ reduction interval is slowest in the center of the opening of the mask material layer 16 at the maximum thickness and the mask material layer 16 is accelerated toward the thin opening. In this way, a cone-shaped resistor layer 15e is formed.

Here, the etching front is shown by the black circle in FIG. 6 (A). In the example shown in this figure, since the maximum diameter of the mask material layer 16 substantially coincides with the diameter of the opening 14, the etching front descends along the sidewall of the opening 14 approximately as the etching proceeds. . When the maximum diameter of the mask material layer 16 does not match the diameter of the opening 14, for example, when the maximum diameter of the mask material layer 16 is smaller than the diameter of the opening 14, the etching front is opened. It descends along the inner position from the side wall of the. A portion above the etching front of the resistor layer 15 remaining inside the opening 14 is called a tip portion. Since the field emission device of the present invention interposes the resistor layer 15e between the cathode electrode 11 and the electron emission section 17e, and suppresses the non-uniformity of the electron emission characteristics of each electron emission section 17e. In order to reliably avoid direct contact between the electron emission section 17e and the cathode electrode 11, it is important to stop the etching before the etching front reaches the surface of the cathode electrode 11.

The cone shape of the tip of the resistor layer 15e is changed by the etching rate ratio of the resistor layer 15 to the etching rate of the mask material layer 16, that is, the "mask selection ratio." The larger the mask selection ratio, the greater the decrease in the thickness of the resistor layer 15 as compared with the decrease in the thickness of the mask material layer 16. Therefore, the inclination angle of the inclined surface of the tip portion of the resistor layer 15e increases. Here, the "tilt angle" as used herein refers to the surface of the cathode electrode 11 as a reference. When the mask material layer 16 is made of a resist material, when the ratio of the O ₂ flow rate to the Cl ₂ flow rate is increased under the conditions shown in Table 10, the large mask selectivity is lowered. Moreover, when using the etching apparatus which can change the incident energy of ion using a substrate bias together, a large mask selectivity can be reduced by raising RF bias power or decreasing the frequency of the AC power supply for bias application. The value of the large mask selectivity in Example 1 is selected to 1.5 or more, preferably 2 or more, more preferably 3 or more.

In the above etching, it is of course necessary to ensure a high selectivity with respect to the gate electrode 13, and there is no problem under the conditions shown in Table 10. This is because the tungsten constituting the gate electrode 13 is hardly etched in the chlorine-based etching species, and a selectivity of about 10 or more tungsten is obtained under the above conditions.

Example 2

Example 2 is a variation of Example 1. The difference between the field emission device of Example 2 and the field emission device of Example 1 is that a second insulating layer is further formed on the gate electrode, and a convergence electrode is formed on the second insulating layer. The conceptual diagram of the field emission element of Example 2 is shown in FIG. 7, and the process diagram of the manufacturing method by the 1A aspect of this invention for manufacturing such a field emission element is shown to FIG. 8 (A), FIG. 8 (B), FIG. 9 (A), FIG. 9 (B), FIG. 10 (A), and FIG. 10 (B). In addition, the code | symbol of these figures is a part common with FIG. 1, and detailed description is abbreviate | omitted about a common part.

In the field emission device of Example 2, a second insulating layer 20 is formed on the gate electrode 13 of the field emission device shown in FIG. 1 and, for example, tungsten (W) on the second insulating layer 20. It has the structure in which the convergence electrode 21 which consists of these was formed. The converging electrode 21 prevents orbital divergence of electrons emitted from an electron emitting portion in a display device of a high voltage type in which the potential difference between the anode electrode and the cathode electrode is an order of thousands of volts and the distance between both electrodes is relatively long. It is a member provided in order to apply a relative negative voltage from a convergent power supply (not shown). By increasing the convergence of the emission electron trajectory, crosstalk between pixels is reduced, and in particular, color turbidity can be prevented in the case of color display, and the pixels can be miniaturized to achieve high definition of the display screen. The tip end of the converging electrode 21 is receded from the tip end of the gate electrode 13. The original purpose of the converging electrode 21 is to correct only the trajectory of electrons trying to deviate greatly from the direction perpendicular to the cathode electrode 11, so that the electron emission efficiency of the field emission element is too small if the opening diameter of the converging electrode 21 is too small. This may fall. However, the tip of the convergence electrode 21 is retracted from the tip of the gate electrode 13 in this way, and thus it is very preferable in the sense that only necessary convergence effect can be obtained without disturbing electron emission.

Openings 24 penetrating through the converging electrode 21, the second insulating layer 20, the gate electrode 13, and the insulating layer 12 are formed. The side wall of this opening part 24 is comprised by each processing surface of the convergence electrode 21, the 2nd insulating layer 20, the gate electrode 13, and the insulating layer 12. As shown in FIG. The upper end of the opening formed in the second insulating layer 20 retreats from the distal end of the convergence electrode 21, and the upper end of the opening formed in the insulating layer 12 is receded from the distal end of the gate electrode 13. The opening diameter of the opening 24 is not uniform in the depth direction, and the diameter is about 0.5 µm in the vicinity of the convergence electrode 21 and 0.35 µm in the vicinity of the gate electrode 13. The shape of the opening 24 allows the electric field having a desired strength to be efficiently formed in the opening 24. The bottom part of the opening part 24 is embedded with the resistor layer 25e, and the tip part of the resistor layer 25e has a horn shape, specifically, a cone shape. On the distal end of the resistor layer 25e, an electron emitting portion 27e is formed to reflect the horn shape. Constituent materials of the resistor layer 25e and the electron emitting portion 27e can be the same as those of the resistor layer 15e and the electron emitting portion 17e of the first embodiment.

In addition, although the conductive thin film 27 is shown on the gate electrode 13 and the converging electrode 21 in FIG. 7, this conductive thin film 27 is comprised from the same material as the electron emission part 27e, It is a layer formed by formation of the discharge part 27e. Although the conductive thin film 27 on the gate electrode 13 and the converging electrode 21 may be removed by a suitable method after the formation of the electron emission portion 27e, in particular, the conductive thin film 27 on the converging electrode 21 is converged. The structure which can prevent the short circuit of the converging electrodes 21 by patterning in substantially the same shape as the electrode 21 is employ | adopted.

Hereinafter, the method of manufacturing the field emission device according to the second embodiment will be described with reference to FIGS. 8 to 10.

[Process -200]

First, the cathode electrode 11 is formed on the support 10. The cathode electrode 11 can be formed in the same manner as in Example 1 using the chromium layer. Next, an insulating layer 12 having a thickness of about 0.7 μm is formed on the support 10 and the cathode electrode 11. The insulating layer 12 can be formed in accordance with the conditions shown in Table 3 above. Subsequently, the gate electrode 13 is formed on the insulating layer 12 in the same manner as in the first embodiment.

Next, the second insulating layer 20 having a thickness of about 1 μm made of SiO ₂ is formed over the entire surface by, for example, the CVD method in accordance with the conditions shown in Table 3 above. In addition, a tungsten layer having a thickness of about 0.07 μm is formed on the entire surface of the second insulating layer 20 by, for example, sputtering according to the conditions shown in Table 11 above, and predetermined patterning is performed to form the convergence electrode 21. (See FIG. 8 (A)).

[Process -210]

Next, a resist layer 22 having a predetermined pattern is formed on the converging electrode 21 and the second insulating layer 20. The condensing electrode 21 and the second are formed using the resist layer 22 as a mask. The insulating layer 20, the gate electrode 13, and the insulating layer 12 are sequentially etched. By this etching, as shown in Fig. 8B, a circular opening 24 having the cathode electrode 11 exposed at the bottom can be formed. Here, etching of the converging electrode 21 and the gate electrode 13 can be performed according to the conditions of Table 5 mentioned above. In addition, etching of the 2nd insulating layer 20 and the insulating layer 12 can be performed in accordance with the conditions shown in Table 6 mentioned above.

[Process-220]

Next, as shown in Fig. 9A, the resist layer 22 is removed and the impurity-containing polysilicon is deposited on the entire surface including the inside of the opening 24, for example, in accordance with the CVD conditions shown in Table 8 above. A resistor layer 25 is formed. A recessed portion 25A is formed on the surface of the resistor layer 25 that reflects the step between the top surface and the bottom surface of the opening 24.

[Process-230]

Next, as shown in FIG. 9B, the mask material layer 26 is left in the recessed portion 25A in the same manner as in the first embodiment.

[Process-240]

Next, the resistor layer 25 and the mask material layer 26 are etched to form a resistor layer 25e having a conical end portion as shown in Fig. 10A. Etching of these layers can be performed like [Step-140] of Example 1.

[Process -250]

Next, as shown in Fig. 10B, an electron emission portion 27e is formed on the tip of the resistor layer 25e. Here, for example, a tungsten layer having a thickness of about 0.01 μm is formed into a film by sputtering to form a conductive thin film 27. An example of sputtering conditions for forming a tungsten layer is as shown in Table 11 above. In this step, a conductive thin film 27 is formed on the gate electrode 13, on the converging electrode 21 and the second insulating layer 20, and on the tip portion of the resistor layer 15e. The portion formed in the tip portion of the resistor layer 25e in the conductive thin film 27 functions as the electron emission portion 27e. In addition, the conductive thin film 27 formed on the converging electrode 21 and the second insulating layer 20 is patterned to have substantially the same shape as the converging electrode 21.

Thereafter, when the sidewalls of the openings formed in the insulating layer 12 and the second insulating layer 20 are retracted inside the opening 24 under isotropic etching conditions, the field emission device shown in FIG. 7 is completed. Isotropic etching is as described in Example 1. Such a field emission device can be used to configure the display device of the present invention. The method of configuring the display device is the same as the method described in the first embodiment.

Example 3

Example 3 relates to a method of manufacturing a field emission device according to Embodiment 1B of the present invention. 11 (A), 11 (B), 12 (A), 12 (B), 13 (A), 13 (B), 14 (A) and FIG. It shows in 14 (B). In addition, the code | symbol of these figures is a part common with FIG. 1, and detailed description is abbreviate | omitted about a common part.

[Process-300]

First, the cathode electrode 11 is formed on the support 10. The cathode electrode 11 includes a TiN layer (thickness 0.1 μm), a Ti layer (thickness 5 nm), an Al-Cu layer (thickness 0.4 μm), a Ti layer (thickness 5 nm), a TiN layer (thickness 0.02 μm), and a Ti layer (0.02). μm) is laminated in this order to form a laminate, and then the laminate is formed by patterning. In the figure, the cathode electrode 11 is shown as a single layer. An example of the sputtering conditions in the case of forming a laminate by the sputtering method is shown in Table 12 below, and an example of the RIE conditions in the case of performing the patterning of the laminate by the RIE method is shown in Table 13 below.

Table 12

Ar flow 30SCCM N ₂ flow rate 60SCCM (only when forming a TiN layer) pressure 0.67 Pa DC power 3 kW Sputtering temperature 200 ℃

Table 13

BCl ₃ flow rate 30SCCM Cl ₂ flow 70SCCM pressure 7Pa RF power 1.3 kW (13.56 MHz) Etching temperature 60 ℃

Next, the insulating layer 12 is formed, the gate electrode 13 is formed, and the opening 14 is formed in the same manner as in Example 1, and the resistor layer 35 is formed on the entire surface including the inside of the opening 14. ). However, the resistor layer 35 in Example 3 selects the thickness so that the recessed part 35A deeper than the recessed part 15A demonstrated in Example 1 may be produced in the surface. Here, the thickness of the resistor layer 35 is set to 0.25 μm with respect to the diameter of the opening 14 to reflect the step between the top and bottom surfaces of the opening 14 to reflect the circumferential portion 35B and the circumferential portion ( An approximately funnel-shaped recessed portion 35A composed of an enlarged portion 35C in communication with the upper end of 35B is formed on the surface of the resistor layer 35. The state which terminated the process so far is shown to FIG. 11 (A).

[Process-310]

Next, as shown in FIG. 11B, a mask material layer 36 is formed on the entire surface of the resistor layer 35. Here, as an example, a copper (Cu) layer having a thickness of about 0.5 μm is formed by an electroless plating method. An example of the electroless plating conditions is shown in Table 14 below.

Table 14

Plating amount Copper sulfate (CuSO ₄ · 5H ₂ O) 7 g / liter formalin (37% HCHO) 20 m1 / liter sodium hydroxide (NaOH) 10 g / liter sodium tartrate 20 g / liter Plating bath temperature 50 ℃

[Process-320]

Next, as shown in FIG. 12 (A), the mask material layer is formed on the circumferential portion 35B by removing the mask material layer 36 and the resistor layer 35 in a plane parallel to the surface of the support 10. Leave 36. This removal can be performed, for example, by chemical / mechanical polishing (CMP) in accordance with the conditions illustrated in Table 15 below. The word "wafer" is conventionally used among the following conditions, but the member corresponding to the wafer in the present invention is the support 10.

Table 15

Wafer pressurization pressure 3.4 × 10 ⁴ Pa (= 5psi) Plate rotation speed 280 rpm Wafer Support Rotational Speed 16 rpm Slurry flow rate 150ml / min

[Process 330]

Next, the resistive layer 35 and the mask material layer 36 are etched under anisotropic etching conditions in which the etching rate of the resistor layer 35 is faster than the etching rate of the mask material layer 36. Etching conditions at this time are illustrated in Table 16 below. As a result, as shown in Fig. 12B, a resistor layer 35e having a tip shape in the opening 14 is formed. And when the mask material layer 36 remains in the front-end | tip of the resistor layer 35e, the mask material layer 36 can be removed by the wet etching using the dilute hydrofluoric acid aqueous solution.

Table 16

Etching equipment Microwave Plasma Etching Equipment with Magnetic Field SF ₆ flow rate 30SCCM Cl ₂ flow 70SCCM Ar flow rate 500SCCM pressure 3Pa Microwave power 1.3 kW (2.45 GHz) RF bias power 20 W (8 MHz) Etching temperature -30 ℃

[Process -340]

Next, as shown in Fig. 13A, an electron emission portion 37e is formed on the tip of the resistor layer 35e. Here, for example, a tungsten layer having a thickness of about 0.01 μm is formed into a film by sputtering to form a conductive thin film 37. An example of the sputtering conditions for forming the tungsten layer is as shown in Table 11 above. In this process, the conductive thin film 37 is formed on the gate electrode 13 and the insulating layer 12 and the resistor layer 35e, and the conductive thin film 37 formed at the tip of the resistor layer 35e emits electrons. It becomes part 37e. In addition, the conductive thin film 37 formed on the gate electrode 13 and the insulating layer 12 is patterned in substantially the same shape as the gate electrode 13.

[Process -350]

Thereafter, as shown in FIG. 13B, when the sidewall of the opening formed in the insulating layer 12 is retracted inside the opening 14 under isotropic etching conditions, the field emission device is completed. Isotropic etching is as described above in Example 1. Such a field emission device can be used to configure the display device of the present invention. The method of configuring the display device is the same as the method described in the first embodiment.

By the way, in the resistor layer 35e formed in Example 3, the sharp horn shape is achieved by the front-end | tip part compared with the electron emission part 15e formed in Example 1. This is due to the difference between the shape of the mask material layer 36 and the ratio of the etching rate of the resistor layer 35 to the etching rate of the mask material layer 36. This difference will be described with reference to FIGS. 14A and 14B. 14 (A) and 14 (B) are diagrams showing how the surface profile of the etched object changes every fixed time, and FIG. 14 (A) is a case where the mask material layer 36 made of copper is used. 14 (B) shows a case where the mask material layer 16 made of a resist material is used, respectively.

When the mask material layer 36 made of copper is used (see FIG. 14A), the etching rate of the mask material layer 36 is sufficiently slower than the etching rate of the resistor layer 35. 36 is not lost, and thus, the tip portion can form a sharp resistor layer 35e. In contrast, in the case where the mask material layer 16 made of resist material is used (see FIG. 14 (B)), the etching rate of the mask material layer 16 is not so large as that of the resistor layer 15. The mask material layer 16 tends to be lost during etching, and therefore, the shape of the horns of the resistor layer 15e after the mask disappears tends to be slowed down.

The mask material layer 36 remaining on the circumferential portion 35B also has the advantage that the shape of the resistor layer 35e does not change well even if the depth of the circumferential portion 35B changes slightly. That is, the depth of the circumferential portion 35B may be changed by the thickness of the resistor layer 35 or the non-uniformity of the step coverage, but the width (diameter) of the circumferential portion 35B is substantially constant regardless of the depth, so the mask material layer The width of the 36 is also substantially constant, and no significant difference appears in the shape of the resistor layer 35e finally formed. In contrast, in the mask material layer 16 remaining in the recessed portion 15A, the width (diameter) of the mask material layer also changes in the shallow and deep portions of the recessed portion 15A, so that the recessed portion 15A is shallow and the mask material layer ( The thinner the thickness of 16), the slower the horn shape of the resistor layer 15e starts. Therefore, there is a possibility that the shape of the tip portion of the electron emission portion 17e formed on the resistor layer 15e by reflecting this horn shape may also be slowed down. The electron emission efficiency of the field emission element is changed not only by the potential difference between the gate electrode and the cathode electrode, the distance between the gate electrode and the cathode electrode, but also by the shape of the tip portion of the electron emission portion in addition to the work function of the constituent material of the electron emission portion. For this reason, it is preferable to select the shape and etching rate of a mask material layer as mentioned above as needed.

Example 4

Example 4 is a variation of Example 3. The difference from the fourth embodiment is that the fourth embodiment differs from the third embodiment in that the mask material layer 36 and the resistor layer 35 are removed as in the third embodiment in leaving the mask material layer in the circumferential portion 35B. Only 36 is removed. The manufacturing method of Example 4 will be described with reference to FIG. 15. In addition, the code | symbol of FIG. 15 is part common with FIG. 11 (A)-FIG. 13 (B), and abbreviate | omits detailed description about a common part.

[Process-400]

First, the formation of the mask material layer 36 shown in FIG. 11B is performed in the same manner as in [Step-300] to [Step-310] of Example 3, and then on the resistor layer 35 and the enlarged portion. By removing only the mask material layer 36 in 35C, the mask material layer 36 is left in the circumferential portion 35B as shown in FIG. At this time, by performing wet etching using, for example, an aqueous difluoric acid solution, only the mask material layer 36 made of copper can be selectively removed without removing the resistor layer 35 made of impurity-containing polysilicon. The height of the mask material layer 36 remaining in the circumferential portion 35B depends on the etching time, but this etching time does not require as much rigor as long as the portion of the mask material layer 36 embedded in the enlarged portion 35C is sufficiently removed. Do not. The reason for this is that the discussion concerning the height of the mask material layer 36 is substantially the same as the discussion regarding the shallow and deepness of the circumferential portion 35B described above with reference to Fig. 14A. This is because the height of 36 does not significantly affect the shape of the resistor layer 35e and the electron emitting portion 37e finally formed.

Subsequently, formation of the electron emitting portion 37e and isotropic etching of the insulating layer 12 in the opening 14 are performed in the same manner as described in Example 3, whereby the field emission element shown in FIG. Is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 5

Example 5 relates to a manufacturing method according to a second aspect of the present invention, more specifically, to a second aspect. A schematic partial cross-sectional view of a field emission device completed by the manufacturing method of Example 5 is shown in FIG. 16 and the manufacturing method thereof is shown in FIGS. 17A, 17B, 18A, and 18B. ), And FIG. 19 (A) and FIG. 19 (B). Reference numerals in these figures are partially common to those in FIG. 1, and detailed descriptions of components common to those in FIG. 1 will be omitted.

The difference between the field emission device that can be manufactured in Example 5 and the field emission device of Example 1 is that the bottom of the opening 14 is buried in the resistor layer 55e, and the horn shape is formed on the resistor layer 55e. The branch is that the electron emitting portion 57e is formed. And although the adhesion layer 56e is shown between the resistor layer 55e and the electron emission part 57e, the adhesion layer 56e is formed for manufacturing reasons, not a functionally indispensable component of the field emission element. The side wall of the insulating layer 12 is cut out in the opening 14 from directly under the gate electrode 13 over the upper end of the resistor layer 55e.

Hereinafter, with reference to FIGS. 17A, 17B, 18A, 18B, 19A, and 19B, the method of manufacturing the field emission device according to the fifth embodiment. It demonstrates with reference to.

[Process -500]

First, the formation of the insulating layer 12 is performed in the same manner as in [Step 100] of Example 1. FIG. Subsequently, a gate electrode 13 made of chromium is formed on the insulating layer 12. Film formation of the chromium layer by the sputtering method at the time of forming the gate electrode 13 can be performed in accordance with the conditions shown in Table 1 above, and patterning by the RIE method of the chromium layer is performed according to the conditions shown in Table 2 above. Can be. Subsequently, the opening 14 is formed. When the opening 14 is formed, the gate electrode 13 can be etched according to the conditions shown in Table 2 above, and the insulating layer 12 can be etched according to the conditions shown in Table 6 above. Next, the resistor layer 55 made of impurity-containing polysilicon is formed on the entire surface including the opening 14, and the planarization layer 51 is formed on the entire surface of the resistor layer 55 so that the surface is substantially flat. To form. Here, the resist layer formed by the spin coating method is used as the planarization layer 51. The planarization layer 51 is a layer formed to planarize the upper surface of the resistor layer 55e formed in the next step [Step-510], but may be omitted. When the planarization layer 51 is omitted, the shape of the recess formed on the surface of the resistor layer 55 is also reflected on the surface of the resistor layer 55e. Fig. 17A shows a state where the process up to this point is finished.

[Process -510]

Next, these two layers are etched under the condition that the etching rates of the planarization layer 51 and the resistor layer 55 are approximately equal, and as shown in FIG. 17B, the resistor layer 55e has a flat top surface. The bottom of the opening part 14 is buried. Etching can be performed by the RIE method using the etching gas containing a chlorine gas and an oxygen gas.

[Process -520]

Next, as shown in FIG. 18A, the adhesion layer 56 is formed on the entire surface including the remaining portion of the opening 14. The adhesive layer 56 is, for example, a TiN layer having a thickness of 0.07 μm formed by the sputtering method, and can be formed in accordance with the sputtering conditions shown in Table 12. Subsequently, a conductive material layer 57 for forming an electron emission portion is formed on the entire surface including the inside of the opening 14. Here, a tungsten layer having a thickness of about 0.3 μm is formed into a conductive material layer 57 by hydrogen reduction pressure reduction CVD. An example of CVD conditions is shown in Table 17 below. A recessed portion 57A is formed on the surface of the formed conductive material layer 57 reflecting the step between the top surface and the bottom surface of the opening 14.

Table 17

WF ₆ flow 95SCCM H ₂ flow rate 700SCCM pressure 1.2 × 10 ⁴ Pa Production temperature 430 ℃

[Process 530]

Next, as shown in Fig. 18B, a mask material layer 58 is formed on the entire surface of the conductive material layer 57 so that the surface is substantially flat. This mask material layer 58 can be formed in the same manner as in [Step-120] of the embodiment.

[Process -540]

Next, as shown in Fig. 19A, the mask material layer 58 is etched by the RIE method using an oxygen-based gas. RIE conditions may employ the conditions shown in Table 9 above. The etching ends when the flat surface of the conductive material layer 57 is exposed. As a result, the mask material layer 58 remains flat in the recessed portion 57A of the surface of the conductive material layer 57. The mask material layer 58 is formed so as to shield the region of the conductive material layer 57 located in the central portion of the opening 14.

[Process -550]

Next, the conductive material layer 57, the mask material layer 58 and the adhesion layer 56 are etched together. This etching can be performed, for example, in accordance with the conditions shown in Table 16 above. As a result of this etching, as shown in Fig. 19B, an electron emission portion 57e having a tip portion having a horn shape is formed. The mechanism in which the horn shape is achieved at the tip end of the electron emission section 57e is the same as the mechanism described for the resistor layer in the first embodiment. Then, when the sidewall of the opening formed in the insulating layer 12 is retracted in the opening 14, the field emission device shown in FIG. 16 can be obtained. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 6

Example 6 is a variation of Example 5. The manufacturing method of Example 6 differs from the manufacturing method of Example 5 by providing a step of further forming a second insulating layer on the insulating layer and the gate electrode and further forming a converging electrode on the second insulating layer. Is the point. A typical partial cross-sectional view of the field emission device completed by the manufacturing method of Example 6 is shown in FIG. 20 and the manufacturing method thereof is shown in FIGS. 21A and 21B. Reference numerals in these figures are partially common to those in FIG. 7, and detailed descriptions of components common to those in FIG. 7 will be omitted.

The field emission device completed by the manufacturing method of Example 6 is composed of, for example, a support 10 made of a glass substrate, a cathode electrode 11 made of chromium (Cr), and SiO ₂ , as shown in FIG. 20. An insulating layer 12 made of chromium, a gate electrode 13 made of chromium, a second insulating layer 20 made of SiO ₂ , a convergence electrode 21 made of chromium, and an electron emitting portion 67e. . Openings 24 penetrating through the converging electrode 21, the second insulating layer 20, the gate electrode 13, and the insulating layer 12 are formed. The bottom part of the opening part 24 is embedded by the resistor layer 65, and the electron emission part 67e is formed on this resistor layer 65. As shown in FIG. And although the adhesion layer 66e is shown between the resistor layer 65 and the electron emission part 67e, the adhesion layer 66e is formed not for the functional component of a field emission element but for manufacturing reasons.

Hereinafter, the method of manufacturing the field emission device according to the sixth embodiment will be described with reference to FIGS. 21A and 21B. In addition, about the process which does not describe a process condition in each process demonstrated in the following example in this specification including Example 6, the conditions shown in the above-mentioned table can be selected suitably, and can be applied.

[Process-600]

First, the formation of the insulating layer 12 is performed in the same manner as in [Step-200] of the second embodiment. Next, a gate electrode 13 made of chromium is formed on the insulating layer 12, and a second insulating layer 20 is formed on the gate electrode 13 and the insulating layer 12, and the second insulating layer is formed. On 20, a converging electrode 21 made of chromium is formed. The film formation and patterning of the chromium layer for forming the converging electrode 21 can be performed in the same manner as the formation of the gate electrode 13. Next, the opening part 24 is formed. In forming the openings 24, the converging electrode 21 and the gate electrode 13 are etched according to the conditions shown in Table 2 above, and the second insulating layer 20 and the insulating layer according to the conditions shown in Table 6 above. (12) can be etched. Next, a resistor layer 65 is formed so as to fill the bottom of the opening 24, more specifically, the bottom of the opening 24 in the portion penetrating the insulating layer 12. The resistor layer 65 can be formed by a process combining the entire surface film formation of the resistor layer, planarization by the planarization layer, and etching in the same manner as in [Step-500] to [Step-510] of the fifth embodiment. have. In Example 6, a polysilicon layer containing phosphorus (P) is used as the resistor layer 65. Fig. 21A shows a state where the process up to this point is finished.

[Process 610]

Next, as shown in Fig. 21B, the contact layer 66 made of TiN and the conductive material layer for forming an electron emission part made of tungsten are formed on the entire surface including the remaining portion of the opening 24, for example. 67) are formed in this order. A recessed portion 67A is formed on the surface of the conductive material layer 67 reflecting the step between the top surface of the opening 24 and the bottom surface (the surface of the resistor layer 65 in the sixth embodiment). A mask material layer (not shown) is formed on the entire surface of the conductive material layer 67, and the mask material layer 68 is left in the recessed portion 67A by, for example, etching back the mask material layer.

Thereafter, the conductive material layer 67, the mask material layer 68, and the adhesion layer 66 are etched in the same manner as in [Step-550] of Example 5 to form an electron emission portion 67e having a horn shape. . Further, when the sidewalls of the openings formed in the insulating layer 12 and the second insulating layer 20 in the opening 54 are retracted by isotropic etching, the field emission device shown in FIG. 20 is obtained. By using such a field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 7

Example 7 relates to a manufacturing method according to a second aspect of the present invention, more specifically, the second B aspect. The manufacturing method of Example 7 is shown to FIG. 22 (A), FIG. 22 (B), FIG. 23 (A), and FIG. 23 (B). Reference numerals in these figures are partially common to those in FIG. 1, and detailed descriptions of components common to those in FIG. 1 will be omitted.

[Process -700]

First, the formation of the gate electrode 13 is performed in the same manner as in the first embodiment. Next, an etching stop layer 28 having a thickness of, for example, SiO ₂ , formed of SiO ₂ is formed on the gate electrode 13 and the insulating layer 12. The etching stop layer 28 is not a functionally indispensable member of the field emission device, but serves to protect the gate electrode 13 during the etching of the conductive material layer 77 performed in a subsequent step. Therefore, when the gate electrode 13 can have sufficiently high etching resistance with respect to the etching conditions of the conductive material layer 77, the etching stop layer 28 may be omitted. Conditions for forming the etch stop layer 28 are as shown in Table 3 above. Thereafter, an opening 74 penetrating through the etch stop layer 28, the gate electrode 13, and the insulating layer 12 is formed by the RIE method. Next, an adhesion layer 76 made of TiN and a conductive material layer 77 for forming an electron emission portion made of tungsten are formed in this order on the entire surface including the remaining portion of the opening 74. Here, the thickness of the conductive material layer 77 is 0.25 μm with respect to 0.6 μm of the diameter of the opening 74, so that between the top surface and the bottom surface (the surface of the resistor layer 75 in the seventh embodiment) of the opening 74. A substantially funnel-shaped recess 77A consisting of a circumferential portion 77B and an enlarged portion 77C communicating with the upper end of the circumferential portion 77B is reflected on the surface of the conductive material layer 77. The mask material layer 78 is formed on the entire surface of the conductive material layer 77. Here, as an example, a copper (Cu) layer having a thickness of about 0.5 μm is formed as the mask material layer 78 according to the conditions shown in Table 14 described above. Fig. 22A shows a state where the process up to this point is finished.

[Process -710]

Next, as shown in FIG. 22B, the mask material is formed on the circumferential portion 77B by removing the mask material layer 78 and the conductive material layer 77 in a plane parallel to the surface of the support 10. Leaves layer 78. This removal can be performed, for example, by the chemical mechanical polishing (CMP) method in accordance with the conditions illustrated in Table 15 above.

[Process -720]

Next, the conductive material layer 77, the mask material layer 78, and the adhesion layer 76 are etched in the same manner as in [Step-550] of Example 5 to form a horn shape as shown in Fig. 23A. The branch forms the electron emission section 77e. The adhesion layer 76e remains between the electron emission portion 77e and the resistor layer 75. The electron emission portion 77e formed in the seventh embodiment is similar to the electron emission portion 57e shown in FIG. 16 with respect to the fifth embodiment, but the width of the mask material layer 78 is narrower than in the fifth embodiment, It also has a more steep horn shape due to its higher selection ratio.

[Process -730]

In addition, when the sidewalls of the openings formed in the insulating layer 12 in the openings 74 are retracted by isotropic etching, and the etching stop layer 28 is removed, the field emission device shown in Fig. 23B is completed. Can be. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 8

Example 8 is a variation of Example 7. Embodiment 8 differs from Embodiment 7 in that it leaves the mask material layer 78 in the circumferential portion 77B, instead of removing the mask material layer 78 and the conductive material layer 77 as in Embodiment 7. Only the mask material layer 78 is removed. The manufacturing method of Example 8 is described with reference to FIG. In addition, the code | symbol of FIG. 24 is part common with FIG. 22 (A)-FIG. 23 (B), and abbreviate | omits detailed description about a common part.

[Process-800]

First, the formation of the mask material layer 78 is performed in the same manner as in [Step-700] of Example 7. Subsequently, by removing only the mask material layer 78 on the conductive material layer 77 and in the enlarged portion 77C, the mask material layer 78 is left in the circumferential portion 77B as shown in FIG. At this time, by performing wet etching using, for example, a dilute hydrofluoric acid solution, only the mask material layer 78 made of copper can be selectively removed without removing the conductive material layer 77 made of tungsten.

Subsequent formation of the electron emission section 77e and isotropic etching of the insulating layer 12 in the opening 74 are performed in the same manner as described in Example 7, whereby the field emission device is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 9

Example 9 relates to a manufacturing method according to a second C aspect of the present invention. The ninth embodiment is similar to the fifth embodiment except that the conductive material layer 57 and the adhesion layer 56 are made of the same conductive material. First, the technical background which led to the proposal of the manufacturing method of Example 9 is demonstrated with reference to FIG. 25, and it continues to FIG. 26 (A), 26 (B), FIG. 27 (A) and FIG. 27 (B). The flowchart of the manufacturing method of Example 9 is shown. In addition, the code | symbol of these figures is a part common with FIG. 16 (A)-FIG. 19 (B), and detailed description is abbreviate | omitted about a common part.

The process shown in Figs. 19A and 19B is the process from [Step-540] to [Step-550] in Example 5, that is, the conductive material layer 57 and the adhesion layer 56. ) Shows the case where etching proceeds ideally. However, in an actual process, the subtle nonuniformity of the etching conditions may cause the horn shape of the electron emission portion 57e to slow down as the etching proceeds or the etching residue may remain on the sidewall of the opening 14. As one of the reasons, depending on the combination of the constituent materials of the conductive material layer 57 and the adhesion layer 56, it is considered that the etching reaction product derived from the adhesion layer 56 inhibits the etching of the conductive material layer 57. Can be. For example, a phenomenon that may occur when the conductive material layer 57 is made of tungsten (W) and the adhesion layer 56 is made of titanium nitride (TiN) and is etched using fluorine-based chemical species is shown in FIG. 25. Conceptually illustrated. In FIG. 25, SF ₆ is used as the etching gas and SF _X ⁺ is generated as the fluorine species. However, when NF ₃ is used as the etching gas, CF is used when NF _X ⁺ and a fluorocarbon gas are used. _X ⁺ is generated as fluorine species, respectively. FIG. 25A shows the change of the surface profile "a" to "g" of the etching target material (ie, the conductive material layer 57, the adhesion layer 56, and the mask material layer 58) as the etching proceeds. 25 (B) schematically shows a phenomenon that may occur at the time of achieving the surface profile "c". Here, the etching rate ratio of the conductive material layer 57 and the mask material layer 58 is assumed to be 2: 1, and the etching rate ratio of the conductive material layer 57 and the adhesion layer 56 is assumed to be 10: 1. do.

In the initial stage of etching, the area of the conductive material layer 57 made of tungsten occupies most of the area to be etched, and the surface profile changes from "a" to "b". At this time, the conductive material layer 57 is quickly removed by a reaction represented by W + xF → WFx (where x is a natural number of 6 or less, and typically x = 6). However, when the surface profile "c" is achieved, the area of the adhesion layer 56 made of TiN occupies most of the area to be etched, and the ratio of the area of the conductive material layer 57 to the area of the etched object. Silver becomes only 1% or less in the design of a normal field emission element. However, titanium fluoride (TiFx; x is a natural number of 3 or less and typically x = 3) produced by the reaction between TiN and a fluorine species has a low vapor pressure, and thus the surface of the conductive material layer 57 Adheres to and hinders the progress of etching. Thus, when the surface profile after the mask material layer 58 is lost, the horn shape is slowed down as it moves from "d" → "e" → "f" → "g" and at the same time the sidewall of the opening 14 Even etching residue may remain. This causes a problem such as a decrease in electron emission efficiency or a short circuit between the gate electrode and the cathode electrode due to the etching residue.

Example 9. In the production method of the field emission device, to substantially match the etch rates (R ₄₎ of the etch rate (R ₃₎ and the adhesive layer 56 of the conductive material layer (57) or (equalization) or the conductive material layer Even if the etching rate R ₃ of 57 is faster, the above problem is solved by selecting within 5 times the etching rate R ₄ of the adhesion layer 56 (R ₄ ≦ R ₃ ≦ 5R ₄ ). In order to match the etching rates of the conductive material layer 57 and the adhesion layer 56 under the same etching conditions, it is simplest to configure both layers using the same conductive material. Even if the conductive materials constituting the both layers are the same, it is possible to achieve the goodness of the step coverage required for the conductive material layer and the goodness of the adhesiveness required for the adhesive layer by appropriately selecting the film forming method. Hereinafter, the manufacturing method of the field emission element of Example 9 is demonstrated.

[Process -900]

First, the formation of the resistor layer 55e filling the bottom of the opening 14 is performed in the same manner as in [Step-500] to [Step-510] of the fifth embodiment. Next, an adhesion layer 56 having a thickness of about 0.07 μm made of tungsten is formed on the entire surface including the remaining portion of the opening 14 by the DC sputtering method. Sputtering conditions are as described in Table 11 above. The tungsten layer formed by the sputtering method can fulfill a sufficient function as the adhesion layer 56. Subsequently, the formation of the conductive material layer 57 made of tungsten and the process of leaving the mask material layer 58 in the recessed portion 57A of the surface of the conductive material layer 57 are performed in the [Step-520] to [ Step 540] can be performed in the same manner. Fig. 26 (A) shows a state where the process up to this point is finished.

[Process -910]

Next, the conductive material layer 57 and the mask material layer 58 are etched. Here, for example, etching can be performed according to the RIE conditions shown in Table 18 below. FIG. 26B shows the time point at which the adhesion layer 56 is exposed. In Example 9, since the material occupying most of the area of the etched object at this point is still tungsten, the etching reaction product having low vapor pressure as described with reference to FIGS. 25A and 25B does not occur, so the etching is performed. It continues quickly.

Table 18

WF ₆ flow 150SCCM O ₂ flow rate 30SCCM Ar flow 90SCCM pressure 35 Pa RF power 0.7 kW (13.56 MHz)

[Process -920]

In addition, when the adhesion layer 56 is also added to the object to be etched, and etching continues, an electron emission portion 57e having a good cone shape can be finally formed as shown in Fig. 27A. FIG. 27B shows changes in the surface profiles "a" to "f" of the etched object (ie, the conductive material layer 57, the adhesion layer 56, and the mask material layer 58) as the etching proceeds. Illustrated. Here, the etching rate ratio of the conductive material layer 57 and the mask material layer 58 is assumed to be 2: 1, and the etching rate ratio of the conductive material layer 57 and the adhesion layer 56 is assumed to be 1: 1. have. Even after the mask material layer 58 is lost, it can be clearly seen that the slowing down of the horn shape of the electron emission portion 57e and the residual of the etching residue are effectively suppressed.

Thereafter, when the sidewall of the opening formed in the insulating layer 12 is retracted inside the opening 14 under isotropic etching conditions, the same field emission device as shown in FIG. 16 is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 10

Example 10 is a variation of Example 5. Example 10 differs from Example 5 in that the side wall of the opening is inclined. The conceptual diagram of the field emission element completed by the manufacturing method of Example 10 is shown in FIG. 28, and the process diagram of the manufacturing method of such a field emission element is shown to FIG. 29 (A) and FIG. 29 (B). In addition, the reference numerals of these drawings are partially common to those of FIG. 1, and detailed description thereof will be omitted.

As shown in FIG. 28, the field emission device according to the tenth embodiment includes a resistor layer 105 filling a bottom of an opening 104 and an electron emission portion 107e having a horn shape formed on the resistor layer 105. Have Although the adhesion layer 106e is shown between the electron emission part 107e and the resistor layer 105, the adhesion layer 106e is formed for manufacturing reasons, not a functionally indispensable component of the field emission element. The side wall of the opening 104 is inclined with an inclination angle θ ₁ , and the inclined surface of the electron emitting portion is inclined with an inclination angle θ ₂ , and the inclination angle θ ₁ and the inclination angle θ ₂ are θ ₁ <θ ₂ <90 We satisfy relationship of °. If the sidewall of the opening is vertical, depending on the etching conditions, an etching residue of the conductive material layer or the adhesion layer remains on the sidewall of the opening, and the gate electrode 13 and the resistor layer 105 are short-circuited by the etching residue, and consequently, the gate electrode. There is a possibility that the 13 and the cathode electrode 11 are short-circuited. If the etching time is extended to sufficiently remove such etching residues, the height of the electron emission section is reduced this time and the distance between the end of the gate electrode 13 and the tip of the electron emission section is increased. This increase in distance leads to a decrease in electron emission efficiency, and thus to an increase in power consumption. However, when the sidewall of the opening 104 is inclined as in the tenth embodiment, even under anisotropic etching conditions, the etching species can sufficiently enter the conductive material layer or the adhesion layer on the sidewall, thereby suppressing the occurrence of the etching residue and simultaneously emitting electrons. It is not necessary to reduce the height of the wealth. Therefore, the structure of the field emission element shown in FIG. 28 can be said to be a structure which can suppress the increase of power consumption, while preventing the short circuit defect between the gate electrode 13 and the cathode electrode 11. As shown in FIG. Hereinafter, the manufacturing method of Example 10 is demonstrated with reference to FIG. 29 (A) and FIG. 29 (B).

[Process-1000]

First, the formation of the etching stop layer 28 is carried out in the same manner as in Example 7, and then the opening 104 is formed. In forming the opening 104, the RIE of the gate electrode 13 is performed under the conditions shown in Table 5, but the etching stop layer 28 and the insulating layer 12 are shown in Table 19 below as an example. RIE conditions apply. The RIE conditions shown in Table 19 have a higher C ₄ F ₈ flow rate than the conditions shown in Table 6 above, which can promote the deposition of carbon-based polymers. As a result, as shown in Fig. 29A, an opening 104 having an inclined sidewall is formed. At this time, the inclination angle θ _{1 of the} sidewall of the opening 104 with respect to the surface of the cathode electrode 11 is about 75 °.

Table 19

C ₄ F ₈ Flow 100SCCM CO flow rate 70SCCM Ar flow 100SCCM pressure 7.3Pa RF power 700 W (13.56 MHz) Etching temperature 20 ℃

Next, a resistor layer 105 filling the bottom of the opening 104 is formed through an etch back using the entire surface film forming and planarization layer of the resistor layer. In addition, an adhesion layer 106 made of titanium nitride and a conductive material layer 107 for forming an electron emission portion made of tungsten are formed in this order on the entire surface including the remaining portion of the opening 104. . On the surface of the formed conductive material layer 107, recessed portions 107A reflecting the step between the top surface of the opening 104 and the bottom surface (the surface of the resistor layer 105 in the tenth embodiment) are formed. Further, a mask material layer 108 is formed on the entire surface of the conductive material layer 107, and the mask material layer 108 is etched back to remain in the recessed portion 107A. Fig. 29A shows a state where the process up to this point is finished.

[Step-1010]

Next, the conductive material layer 107, the mask material layer 108, and the adhesion layer 106 are etched to form a conical electron emission portion 107e as shown in FIG. 29B. This etching can be performed, for example, in accordance with the conditions shown in Table 16 above. The inclination angle θ ₂ of the inclined surface of the tip of the electron emission portion 107e is about 80 °, and the inclination angle of the sidewall of the opening 104 is greater than (θ ₁ ) (about 75 °). Since the two inclination angles satisfy the relationship of θ ₁ <θ ₂ , the electron emission portion 107e having a sufficient height can be formed without leaving an etching residue on the sidewall of the opening 104 during the above etching.

Thereafter, when the sidewall of the opening formed in the insulating layer 12 is retracted in the opening 104 under isotropic etching conditions and the etching stop layer 28 is removed, the field emission device shown in FIG. 28 is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 11

Example 11 relates to a manufacturing method according to the third aspect of the present invention, more specifically, the third aspect. A typical partial cross-sectional view of the field emission device completed by the manufacturing method of Example 11 is shown in FIG. 30, and the manufacturing method thereof is shown in FIGS. 31A and 31B. Reference numerals in these figures are partially common to those in FIG. 1, and detailed descriptions of components common to those in FIG. 1 will be omitted.

In the field emission device that can be manufactured in Example 11, as shown in FIG. 30, a cathode electrode 11 made of chromium is formed on the support 10, and for example, contains impurities on the cathode electrode 11. A resistor layer 115 made of polysilicon is formed. An insulating layer 12 is formed on the cathode electrode 11 and the support 10, and a gate electrode 13 made of chromium is formed on the insulating layer 12. Openings 14 penetrating the two members are formed in the gate electrode 13 and the insulating layer 12, and sidewalls of the openings formed in the insulating layer 12 are receded from the opening ends of the gate electrode 13. On the resistor layer 115 positioned at the bottom of the opening 14, an electron emission portion 117e made of, for example, tungsten and having a horn shape (more specifically, a cone shape) is formed. Although an adhesion layer 116e is shown between the electron emission portion 117e and the resistor layer 115, the adhesion layer 116e is formed for manufacturing reasons, not a functionally indispensable component of the field emission device.

Hereinafter, the manufacturing method of Example 11 is demonstrated with reference to FIG. 31 (A) and FIG. 31 (B).

[Process-1100]

First, the cathode electrode 11 having the resistor layer 115 on the surface is formed on the support 10. Specifically, for example, a chromium (Cr) layer constituting the cathode electrode 11 and an impurity-containing polysilicon layer constituting the resistor layer 115 are laminated to form a common etching mask (not shown) and chlorine etching. The gas is used to etch the chromium layer and the impurity containing polysilicon layer. Next, an insulating layer 12 is formed on the cathode electrode 11 and the support 10, and a gate electrode 13 made of chromium is formed on the insulating layer 12. The gate electrode 13 and the insulating layer 12 are etched to form an opening 14 in which the resistor layer 115 is exposed at the bottom. Fig. 31A shows a state where the process up to this point is finished.

[Process-1110]

Next, an adhesion layer 116 made of TiN and a conductive material layer 117 for forming an electron emission portion made of tungsten are formed in this order on the entire surface including the inside of the opening 14. On the surface of the conductive material layer 117, recessed portions 117A reflecting the step between the top and bottom surfaces of the opening 14 are formed. Further, a mask material layer (not shown) is formed on the entire surface of the conductive material layer 117 and the mask material layer 118 is left in the recessed portion 117A by, for example, etching back the mask material layer (Fig. 31). (B)).

Thereafter, the conductive material layer 117, the mask material layer 118, and the adhesion layer 116 are etched in the same manner as in [Step-550] of Example 5 to form an electron emission portion 117e having a horn shape. . If the sidewalls of the openings formed in the insulating layer 12 are retracted by isotropic etching in the openings 14, the field emission device shown in Fig. 30 is obtained. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 12

Example 12 relates to a method for manufacturing a field emission device according to Embodiment 3B of the present invention. The manufacturing method of Example 12 is explained with reference to FIG. 32 (A) and FIG. 32 (B). Incidentally, the symbols in FIGS. 32A and 32B are partially common to FIGS. 31A and 31B, and detailed descriptions thereof will be omitted.

[Process-1200]

First, the formation of the adhesive layer 116 is performed in the same manner as in the eleventh embodiment. Next, a conductive material layer 117 for forming an electron emission portion made of tungsten is formed on the entire surface including the inside of the opening 24. Here, by setting the thickness of the conductive material layer 117 to 0.25 µm with respect to a diameter of 0.5 µm of the opening 24, the step between the top surface and the bottom surface (here, the surface of the resistor layer 115) of the opening 24. Reflecting this, the substantially funnel-shaped recessed part 117A which consists of the circumferential part 117B and the expanded part 117C which communicates with the upper end of the circumferential part 117B is produced in the surface of the conductive material layer 117. As shown in FIG. Further, for example, a copper (Cu) layer having a thickness of about 0.5 μm is formed on the entire surface of the conductive material layer 117 as the mask material layer 118. Fig. 32A shows a state where the process up to this point is finished.

[Process-1210]

Next, as illustrated in FIG. 32B, the mask material is formed on the circumferential portion 117B by removing the mask material layer 118 and the conductive material layer 117 in a plane parallel to the surface of the support 10. Leaves layer 118. This removal can be performed by, for example, a chemical mechanical polishing (CMP) method.

Thereafter, the conductive material layer 117, the mask material layer 118, and the adhesion layer 116 are etched in the same manner as in [Step-720] of Example 7 to form an electron emission portion, and the insulating layer 12 is further formed. By performing isotropic etching in the same manner as in [Step-730] of Example 7, a field emission device similar to Example 11 (see Fig. 30) can be completed. However, the horn shape of the electron emission section formed in the twelfth embodiment is steeper than the horn shape of the electron emission section 117e formed in the eleventh embodiment. The display device can be configured in the same manner as described in the first embodiment by using the field emission device completed in the twelfth embodiment.

Example 13

Example 13 is a variation of Example 12. Example 13 differs from Example 12 in that it leaves the mask material layer 118 in the circumference 117B, instead of removing the mask material layer 118 and the conductive material layer 117 as in Example 12. Only the mask material layer 118 is removed. The manufacturing method of Example 13 is described with reference to FIG. In addition, the code | symbol of FIG. 33 is a part common with FIG. 32 (A) and FIG. 32 (B), and detailed description is abbreviate | omitted.

[Process-1300]

First, the formation of the mask material layer 118 is performed in the same manner as in [Step-1200] of Example 12. Subsequently, only the mask material layer 118 on the conductive material layer 117 and in the enlarged portion 117C is removed, thereby leaving the mask material layer 118 in the circumferential portion 117B. At this time, by performing wet etching using, for example, an aqueous solution of difluoric acid, only the mask material layer 118 made of copper can be selectively removed without removing the conductive material layer 117 made of tungsten.

Subsequent formation of the electron emission section and isotropic etching of the insulating layer 12 in the opening 24 are performed in the same manner as described in Example 7, whereby the field emission device is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 14

Example 14 relates to a manufacturing method according to a third C aspect of the present invention. Example 14 is similar to Example 11, except that the conductive material layer 117 and the adhesion layer 116 are made of the same conductive material. The manufacturing method of Example 14 will be described with reference to FIGS. 34A and 34B. Incidentally, the symbols in FIGS. 34A and 34B are partially common to FIGS. 11A and 11B, and detailed descriptions thereof will be omitted.

[Process-1400]

First, the formation of the openings 14 is performed in the same manner as in the [Step-1100] of the eleventh embodiment. Next, an adhesion layer 116 having a thickness of about 0.07 μm made of tungsten is formed on the entire surface including the inside of the opening 14 by the DC sputtering method. Sputtering conditions are as described in Table 11 above. The tungsten layer formed by the sputtering method can fulfill a sufficient function as the adhesion layer 116. Thereafter, the process of forming the conductive material layer 117 made of tungsten and leaving the mask material layer 118 in the recessed portion 117A on the surface of the conductive material layer 117 is the same as that of [Step-1110] of the eleventh embodiment. I can do it. Fig. 34A shows a state in which the process up to this point is completed.

[Process-1410]

Next, the conductive material layer 117 and the mask material layer 118 are etched in the same manner as in the ninth embodiment. 34B illustrates the time point at which the adhesion layer 116 is exposed. In Example 14, since the material occupying most of the area of the object to be etched at this point is still tungsten, the etching reaction product with low vapor pressure does not occur and etching proceeds rapidly.

If the adhesion layer 116 is also added to the object to be etched, and etching continues, an electron emitting portion having a good cone shape can be finally formed without leaving an etching residue. Thereafter, when the sidewall of the opening formed in the insulating layer 12 is retracted in the opening 14 under isotropic etching conditions, the same field emission device as shown in FIG. 30 is completed. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

Example 15

Example 15 is a variation of Example 11. Example 15 differs from Example 11 in that the side wall of the opening is inclined. The conceptual diagram of the field emission element completed by the manufacturing method of Example 15 is shown in FIG. 35, and the process diagram of the manufacturing method of such a field emission element is shown to FIG. 36 (A) and FIG. 36 (B). In addition, the reference numerals of these drawings are partially common to those of FIG. 30, and detailed descriptions thereof will be omitted.

In the field emission device completed by the manufacturing method of Example 15, as shown in FIG. 35, a cathode electrode 11 made of chromium is formed on the support 10, and the resistor layer 115 is formed on the cathode electrode 11. ) Is formed. An insulating layer 12 is formed on the cathode electrode 11 and the support 10, and a gate electrode 13 made of chromium is formed on the insulating layer 12. The gate electrode 13 and the insulating layer 12 are formed with openings 154 penetrating these two members, and the sidewalls of the openings formed in the insulating layer 12 retreat from the opening ends of the gate electrode 13 and have an inclination angle ( inclined with θ ₁ ). On the resistor layer 115 positioned at the bottom of the opening 14, an electron emission portion 157e made of, for example, tungsten and having a horn shape (more specifically, a cone shape) is formed. The inclined surface of the electron emitting portion is inclined with an inclination angle θ ₂ , and the inclination angle θ ₁ and the inclination angle θ ₂ satisfy a relationship of θ ₁ <θ ₂ <90 °. Although an adhesion layer 156e is shown between the electron emission portion l57e and the resistor layer 115, the adhesion layer 156e is formed for manufacturing reasons, not a functionally indispensable component of the field emission device. The structure of the field emission device shown in FIG. 35 is a structure that can suppress an increase in power consumption while preventing a short circuit defect between the gate electrode 13 and the cathode electrode 11.

Hereinafter, the manufacturing method of Example 15 is demonstrated with reference to FIG. 36 (A), FIG. 36 (B), and FIG. 36 (C).

[Process-1500]

First, the formation of the gate electrode 13 is performed in the same manner as in [Step-1100] of the eleventh embodiment. Next, the gate electrode 13 is etched according to the conditions shown in Table 2, for example, and the insulating layer 12 is etched according to the conditions shown in Table 19, for example, to FIG. 36A. As shown, the sidewalls form an inclined opening 154. At this time, the inclination angle θ _{1 of the} side wall of the opening 154 with respect to the surface of the cathode electrode 11 is about 75 °.

[Process-1510]

Next, as shown in FIG. 36 (B), the contact layer 156 made of, for example, TiN and the conductive material layer 157 for forming an electron emission portion made of tungsten are formed on the entire surface including the inside of the opening 154. ) In this order. The concave portion 157A is formed on the surface of the conductive material layer 157 to reflect the step between the top surface and the bottom surface of the opening 154 (here, the surface of the resistor layer 115). A mask material layer (not shown) is formed on the entire surface of the conductive material layer 157 and the mask material layer 158 is left in the recessed portion 157A by, for example, etching back the mask material layer.

[Process-1520]

Thereafter, the conductive material layer 157, the mask material layer 158, and the adhesion layer 156 are etched in the same manner as in Example 11 to form an electron emission portion 157e having a horn shape (FIG. 36C). Reference). When the sidewalls of the openings formed in the insulating layer 12 are retracted by isotropic etching in the openings 154, the field emission device shown in Fig. 35 is obtained. Using the field emission device, the display device can be configured in the same manner as described in the first embodiment.

As mentioned above, although this invention was demonstrated according to the Example of this invention, this invention is not limited to these. The details of the structure of the field emission device, the details of processing conditions and materials used in the method of manufacturing the field emission device, and the details of the structure of the display device to which the field emission device is applied are exemplified and can be appropriately changed, selected, and combined. Do. For example, the convergence electrode described in Example 2 or Example 6 may be provided in the field emission element described in Example 3, Example 4, or Example 7-15. In the field emission device described in Examples 1 to 6, an adhesion layer may be provided between the cathode electrode and the resistor layer. In Example 2, although the manufacturing method by the 1A aspect of this invention was illustrated, the manufacturing method by 1stB aspect is also applicable similarly. In Example 6 and Example 10, although the manufacturing method by 2 A aspect of this invention was illustrated, the manufacturing method by 2 B aspect and 2 C aspect is also applicable similarly. Moreover, in Example 15, although the manufacturing method by 3rd aspect of this invention was illustrated, the manufacturing method by 3rd aspect and 3C aspect is also applicable similarly.

As apparent from the above description, since the field emission device of the present invention has a configuration in which the electron emission section and the cathode electrode are connected through the resistor layer, the non-uniformity of the electron emission characteristics due to the non-uniformity of the shape and dimensions of the electron emission section is This suppresses the display quality and the reliability.

In the manufacturing method according to the first aspect of the present invention, the resistive layer having the tip portion having a horn shape is uniformly formed by a process of carefully selecting the formation site and shape of the mask material layer and the etching rate ratio of the mask material layer and the resistor layer. Moreover, reproducibility can be formed favorably. Therefore, it is also easy to uniformize the shape and dimensions of the electron emission portion formed on the resistor layer by reflecting its horn shape, thereby providing a highly reliable field emission device with highly uniform electron emission characteristics. Further, in the field emission device of the present invention, since the electron emission portion is composed of the resistor layer and the electron emission portion formed thereon, the distance between the tip of the electron emission portion and the gate electrode can be finely adjusted by appropriately selecting the height of the resistor layer. This improves the degree of freedom in designing the field emission device, and furthermore, the display device using the field emission device.

In the manufacturing method according to the second and third aspects of the present invention, instead of forming the tip portion of the resistor layer into a horn shape, the horn shape of the tip portion of the electron emitting portion can be uniformly and easily achieved by the same principle. The uniformity in the shape and dimensions of the electron emission portion makes it possible to provide a highly reliable field emission element with highly uniform electron emission characteristics.

In the manufacturing method according to the first to third aspects of the present invention, the horn shape constituting the distal end portion of the resistor layer or the electron emitting portion can be formed by a series of self-aligned processes. Therefore, the complexity of the process is reduced, and even when manufacturing a large area cathode panel, an electron emission portion having a uniform dimension and shape can be formed over the entire surface of the cathode panel, which facilitates large screen display. It becomes possible to respond. Since the self-aligned process can be applied, the number of photolithography steps can be reduced, the manufacturing equipment investment can be reduced, the process time can be shortened, and the manufacturing cost of the field emission device and the display device can be reduced.

Claims (44)

(A) a cathode electrode formed on the support, (B) an insulating layer formed on the cathode electrode and the support, (C) a gate electrode formed on the insulating layer, (D) an opening penetrating through the gate electrode and the insulating layer, (E) a resistor layer formed on the cathode electrode located at the bottom of the opening portion and having a tip-shaped tip portion; (F) An electron emission portion formed of a conductive material having a work function smaller than that of the material constituting the resistor layer and reflecting the shape of the tip of the tip portion on the tip of the resistor layer. Cold cathode field emission device comprising: a. The method of claim 1, An electric resistivity of the resistor layer is in the range of 1.0 kPa · cm to 10 MPa · cm. The method of claim 1, And a second insulating layer is further formed on the gate electrode and the insulating layer, and a focus electrode is formed on the second insulating layer. (a) forming a cathode electrode on the support; (b) forming an insulating layer on the cathode electrode and the support; (c) forming a gate electrode on the insulating layer, (d) forming at least an opening in the insulating layer, the opening having the cathode electrode exposed at the bottom thereof; (e) forming a resistor layer on the entire surface including the inner surface of the opening; (f) forming a mask material layer on the resistor layer so as to shield an area of the resistor layer located at the central portion of the opening; (g) Etch the resistor layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the resistor layer is higher than the etching rate in the direction perpendicular to the support of the mask material layer. Thereby forming a resistor layer having a horn shape in the opening portion, (h) forming an electron emission section on the tip of the resistor layer, which is made of a conductive material having a lower work function than the material constituting the resistor layer and reflecting the horn shape of the tip; Method for producing a cold cathode field emission device comprising a. The method of claim 4, wherein In the step (e), the resistive layer is formed using a material having an electrical resistivity in the range of 1.0 kPa · cm to 10 MPa · cm, wherein the cold cathode field emission device is manufactured. The method of claim 4, wherein In the step (e), recesses reflecting the step between the top and bottom surfaces of the opening are formed on the surface of the resistor layer, In the step (f), the cold cathode field emission is formed by forming a mask material layer on the entire surface of the resistor layer and removing the mask material layer until the flat surface of the resistor layer is exposed to leave the mask material layer in the recess. Method of manufacturing the device. The method of claim 4, wherein In the step (e), a roughly funnel-shaped recess consisting of a columnar portion and an enlarged portion communicating with the upper end of the columnar portion is formed on the surface of the resistor layer, reflecting the step between the top and bottom surfaces of the opening, In the step (f), a mask material layer is formed in the circumferential portion, wherein the cold cathode field emission device is produced. The method of claim 7, wherein In the step (f), the mask material layer is formed on the entire surface of the resistor layer, and then the mask material layer and the resistor layer are removed in the plane parallel to the surface of the support to leave the mask material layer only in the circumference. The manufacturing method of a cold cathode field emission element. The method of claim 7, wherein In the step (f), after forming the mask material layer on the entire surface of the resistor layer, the mask material layer is left on the circumferential portion only by removing the mask material layer on the resistor layer and in the enlarged portion. Method of manufacturing the device. The method of claim 7, wherein When the etching speed in the direction perpendicular to the support of the mask material layer R _2, with respect to the support of the resistive material layer have an etch rate in the direction perpendicular to R _1, characterized in that it satisfies the relation of ₁ 10R ₂ ≤R The manufacturing method of a cold cathode field emission element. The method of claim 7, wherein A method of manufacturing a cold cathode field emission device, characterized in that the mask material layer consists of at least one of copper, gold, and platinum. The method of claim 4, wherein In the step (e), the resistive layer is formed by CVD. (a) forming a cathode electrode on the support; (b) forming an insulating layer on the cathode electrode and the support; (c) forming a gate electrode on the insulating layer, (d) forming at least an opening in the insulating layer, the opening having the cathode electrode exposed at the bottom thereof; (e) embedding the bottom of the opening portion into the resistor layer; (f) forming a conductive material layer for forming an electron emission portion on the entire surface including the remaining portion of the opening; (g) forming a mask material layer on the conductive material layer so as to shield an area of the conductive material layer located at the central portion of the opening; (h) conducting by etching the conductive material layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the conductive material layer is higher than the etching rate in the direction perpendicular to the support of the mask material layer. A process of forming an electron emitting portion made of a material layer and having a tip-shaped tip portion Method for producing a cold cathode field emission device comprising a. The method of claim 13, In the step (e), the resistive layer is formed using a material having an electrical resistivity in the range of 1.0 kPa · cm to 10 MPa · cm, wherein the cold cathode field emission device is manufactured. The method of claim 14, In the step (e), the resistive layer is formed on the entire surface including the inner surface of the opening, and the resistive layer is etched to fill the bottom of the opening with the resistive layer. The method of claim 15, In the step (e), a resistor layer is formed on the entire surface including the inner surface of the opening, and a planarization layer is further formed on the entire surface of the resistor layer so that the surface is approximately flat, and the support of the planarization layer and the resistor layer is provided. A method of manufacturing a cold cathode field emission device, characterized in that the bottom of the opening is buried in a resistor layer having a flat upper surface by etching the planarization layer and the resistor layer under conditions in which the etching rates in the direction perpendicular to each other are substantially equal. The method of claim 14, In the step (d), an opening having an inclination angle θ ₁ of a side wall with respect to the surface of the cathode electrode is formed in the insulating layer, In the step (h), the inclination angle θ ₂ of the slope relative to the surface of the cathode electrode forms a horn-shaped electron emission portion satisfying the relationship of θ ₁ <θ ₂ <90 °. Method for producing a cold cathode field emission device. The method of claim 14, In the step (f), a recess is formed in the surface of the conductive material layer for forming the electron emission portion, which reflects the step between the top surface and the bottom surface of the opening, In the step (g), after forming the mask material layer on the entire surface of the conductive material layer, the mask material layer is removed until the flat surface of the conductive material layer is exposed, thereby leaving the mask material layer in the recess. Method for producing a field emission device. The method of claim 14, In step (f), a substantially funnel-shaped recess consisting of a circumferential portion and an enlarged portion communicating with the upper end of the circumferential portion reflecting the step between the top surface and the bottom surface of the opening portion is formed in the surface of the conductive material layer for forming the electron emission portion. Create it, In the step (g), a mask material layer is left in the circumferential portion, wherein the cold cathode field emission device is produced. The method of claim 19, In the step (f), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer and the conductive material layer are removed in a plane parallel to the surface of the support to leave the mask material layer only in the circumference. The manufacturing method of a cold cathode field emission element. The method of claim 19, In the step (f), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer is left on the circumferential portion only by removing the mask material layer on the resistor layer and in the enlarged portion. Method of manufacturing the emitting device. The method of claim 19, When the etching speed in the direction perpendicular to the support of the mask material layer R _2, with respect to a support of the conductive material layer have an etch rate in the direction perpendicular to the R _3, by satisfying the relationship 10R ₂ ≤R ₃ The manufacturing method of the cold cathode field emission element characterized by the above-mentioned. The method of claim 22, A method of manufacturing a cold cathode field emission device, characterized in that the mask material layer consists of at least one of copper, gold, and platinum. The method of claim 14, In the step (f), before the formation of the conductive material layer for forming the electron emission portions, the adhesion layer is formed on the entire surface including the remaining portions of the openings. The method of claim 24, In the step (h), the etching rate in the direction perpendicular to the support of the conductive material layer and the etching rate in the direction perpendicular to the support of the adhesive layer are lower than the etching rate in the direction perpendicular to the support of the mask material layer. A method for producing a cold cathode field emission device, characterized by etching the conductive material layer, the mask material layer and the adhesion layer under fast anisotropic etching conditions. The method of claim 25, In step (h), when the etching rate in the direction perpendicular to the support of the conductive material layer for forming the electron emission portion is R _{3 and} the etching rate in the direction perpendicular to the support of the adhesion layer is R ₄ , A method for manufacturing a cold cathode field emission device, characterized by satisfying a relationship of R ₄ ≤ R ₃ ≤ 5R ₄ . The method of claim 26, A method for manufacturing a cold cathode field emission device, wherein the conductive material layer and the adhesion layer are made of the same material. The method of claim 14, A method for manufacturing a cold cathode field emission device, wherein a conductive material layer for forming an electron emission section is formed by CVD. (a) forming a cathode electrode having a resistor layer on its surface on a support; (b) forming an insulating layer on the cathode electrode and the support; (c) forming a gate electrode on the insulating layer, (d) forming at least an opening in the insulating layer an opening in which the resistor layer is exposed at the bottom; (e) forming a conductive material layer for forming an electron emission portion on the entire surface including the inner surface of the opening; (f) forming a mask material layer on the conductive material layer so as to shield an area of the conductive material layer located at the central portion of the opening; (g) conductive by etching the conductive material layer and the mask material layer under anisotropic etching conditions in which the etching rate in the direction perpendicular to the support of the conductive material layer is faster than the etching rate in the direction perpendicular to the support of the mask material layer. A process of forming an electron emitting portion made of a material layer and having an end portion having an horn shape on a resistor layer Method for producing a cold cathode field emission device comprising a. The method of claim 29, In the step (a), the resistive layer is formed using a material having an electrical resistivity in the range of 1.0 kPa · cm to 10 MPa · cm, wherein the cold cathode field emission device is manufactured. The method of claim 30, In the step (d), an opening having an inclination angle θ ₁ of the side wall with respect to the surface of the cathode electrode is formed in the insulating layer, In the step (h), the inclination angle θ ₂ of the inclined surface with respect to the surface of the cathode electrode forms a horn-shaped electron emission portion satisfying the relationship of θ ₁ <θ ₂ <90 °. Method of manufacturing the emitting device. The method of claim 30, In the step (e), a recess is formed on the surface of the conductive material layer for forming the electron emission portion, which reflects the step between the top surface and the bottom surface of the opening, In the step (f), the mask material layer is formed on the entire surface of the conductive material layer and then the mask material layer is removed until the flat surface of the conductive material layer is exposed to leave the mask material layer in the recess. Method for manufacturing a cathode field emission device. The method of claim 30, In step (e), a substantially funnel-shaped recess consisting of a circumferential portion and an enlarged portion communicating with the upper end of the circumferential portion, reflecting the step between the top surface and the bottom surface of the opening portion, is formed on the surface of the conductive material layer for forming the electron emission portion. Create it, In the step (f), a mask material layer is left in the circumferential portion, wherein the cold cathode field emission device is produced. The method of claim 33, wherein In the step (e), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer and the conductive material layer are removed in the plane parallel to the surface of the support to leave the mask material layer only in the circumference. The manufacturing method of the cold cathode field emission element characterized by the above-mentioned. The method of claim 33, wherein In the step (e), the mask material layer is formed on the entire surface of the conductive material layer, and then the mask material layer is left on the circumferential portion only by removing the mask material layer on the resistor layer and in the enlarged portion. Method of manufacturing the emitting device. The method of claim 33, wherein When the etching speed in the direction perpendicular to the support of the mask material layer R _2, with respect to a support of the conductive material layer have an etch rate in the direction perpendicular to the R _3, by satisfying the relationship 10R ₂ ≤R ₃ The manufacturing method of the cold cathode field emission element characterized by the above-mentioned. The method of claim 36, A method of manufacturing a cold cathode field emission device, characterized in that the mask material layer consists of at least one of copper, gold, and platinum. The method of claim 30, A method for manufacturing a cold cathode field emission device, wherein a conductive material layer for forming an electron emission section is formed by CVD. The method of claim 30, In the step (e), before the formation of the conductive material layer for forming the electron emission portions, the adhesion layer is formed on the entire surface including the remaining portions of the openings. The method of claim 39, In the step (g), the etching rate in the direction perpendicular to the support of the conductive material layer and the etching rate in the direction perpendicular to the support of the adhesive layer are less than the etching rate in the direction perpendicular to the support of the mask material layer. A method for producing a cold cathode field emission device, characterized by etching the conductive material layer, the mask material layer and the adhesion layer under fast anisotropic etching conditions. The method of claim 40, In step (g), when the etching rate in the direction perpendicular to the support of the conductive material layer for forming the electron emission portion is R ₃ , the etching rate in the direction perpendicular to the support of the adhesion layer is set to R ₄ . A method for manufacturing a cold cathode field emission device, characterized by satisfying a relationship of R ₄ ≤ R ₃ ≤ 5R ₄ . The method of claim 41, wherein A method for manufacturing a cold cathode field emission device, wherein the conductive material layer and the adhesion layer are made of the same material. Composed of a plurality of pixels, Each pixel is composed of an anode electrode and a phosphor layer formed on a substrate facing a plurality of cold cathode field emission elements and a plurality of cold cathode field emission elements, Each cold cathode field emission element (A) a cathode electrode formed on the support, (B) an insulating layer formed on the cathode electrode and the support, (C) a gate electrode formed on the insulating layer, (D) an opening penetrating through the gate electrode and the insulating layer, (E) a resistor layer formed on the cathode electrode located at the bottom of the opening portion and having a tip-shaped tip portion; (F) An electron emission portion formed of a conductive material having a work function smaller than that of the material constituting the resistor layer and reflecting the shape of the tip of the tip portion on the tip of the resistor layer. And a cold cathode field emission display device. The method of claim 43, An electric resistivity of the resistive layer is in the range of 1.0 kPa · cm to 10 MPa · cm.