JP2000195412A - Cold cathode field electron emission device and its manufacture, and cold cathode field electron emission display apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve uniformity of dimension or shape of an electron emission part and provide a field emission device, with easy manufacture, allowing correspondence to expansion of a picture of a display apparatus. SOLUTION: A field emission device is provided with a cathode electrode 11 formed on a supporting matter 10, an insulating layer 12 formed on the supporting matter 10 and the cathode electrode 11, a gate electrode 13 formed on the insulating layer 12, an opening part 19, penetrating through the gate electrode 13 and the insulating layer 12, in which the cathode electrode 11 is exposed at a bottom thereof and an electron emission part 18, formed on the cathode electrode 11 exposed on a bottom surface of the opening part 19, whose tip part has a conical form, made of polycrystalline or amorphous conductive material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode field emission device, a method of manufacturing the same, and a cold cathode field emission display device, and more particularly, to a cold cathode field emission device having a conical tip. The present invention relates to an emission device, a method of manufacturing the same, and a flat-type cold cathode field emission display device in which such cold cathode field emission devices are arranged in a two-dimensional matrix.

[0002]

2. Description of the Related Art Various types of flat-panel (flat-panel) display devices have been studied as image display devices to replace the current mainstream cathode ray tube (CRT). Examples of such a flat display device include a liquid crystal display device (LCD), an electroluminescence display device (ELD), and a plasma display device (PDP). In addition, a cold cathode field emission display device capable of emitting electrons from a solid into a vacuum without thermal excitation, a so-called field emission display (FED), has been proposed. Attention is drawn from the viewpoint of power consumption.

A display device of a cold cathode field emission type (hereinafter, referred to as a cold cathode field emission device)
Generally, a display device is simply referred to as a display device). In general, a collision between a cathode panel having an electron emission portion corresponding to each pixel arranged in a two-dimensional matrix and electrons emitted from the electron emission portion. And an anode panel having a phosphor layer that emits light when excited by the above. In each pixel on the cathode panel, usually, a plurality of electron emitting portions are formed, and further, a gate electrode for extracting electrons from the electron emitting portion is formed. The portion having the electron emission portion and the gate electrode will be referred to as a field emission device.

In the structure of such a display device, in order to obtain a large emission electron current at a low driving voltage, the tip of the electron emission portion is formed to have a sharp pointed shape, and each electron emission portion is miniaturized. It is necessary to increase the density of the electron-emitting portions in the section corresponding to one pixel and to reduce the distance between the tip of the electron-emitting portion and the gate electrode. Therefore, in order to realize these, field emission devices having various configurations have been conventionally proposed.

As one of typical examples of such a conventional display device, a so-called Spindt type display device in which an electron emitting portion is formed of a conical conductor is known. FIG. 17 is a conceptual diagram of the Spindt-type display device. A cathode panel CP constituting a Spindt-type display device includes a cathode electrode 201 formed on a support 200 and an insulating layer 2.
02 and the gate electrode 203 formed on the insulating layer 202
And a conical electron emission portion 205 formed in an opening 204 provided through the gate electrode 203 and the insulating layer 202. A predetermined number of the electron emission portions 205 are arranged in a two-dimensional matrix to form one pixel. On the other hand, the anode panel AP has a structure in which a phosphor layer 211 is formed on a transparent substrate 210 in a predetermined pattern, and the phosphor layer 211 is covered with an anode electrode 212.

When a voltage is applied between the electron-emitting portion 205 and the gate electrode 203, electrons e are extracted from the tip of the electron-emitting portion 205 by the resulting electric field. This electron e is supplied to the anode electrode 212 of the anode panel AP.
The anode electrode 212 and the transparent substrate 210
And the phosphor layer 211, which is a light emitting layer formed between the two. As a result, the phosphor layer 211 is excited to emit light, and a desired image can be obtained. The operation of the field emission device is basically controlled by the voltage applied to the gate electrode 203.

An outline of a method of manufacturing a field emission device in such a display device will be described below with reference to FIGS. This manufacturing method is basically a method of forming the conical electron emitting portion 205 by vertical vapor deposition of a metal material. That is, the vapor deposition particles enter the opening 204 perpendicularly, but the amount of the vapor deposition particles reaching the bottom of the opening 204 by utilizing the shielding effect of the overhanging deposit formed near the opening end. Is gradually reduced, and the electron emission portion 205 which is a conical deposit is formed in a self-aligned manner. Here, a method in which a release layer 206 is formed in advance on the gate electrode 203 in order to facilitate removal of unnecessary overhang-like deposits will be described.

[Step-10] First, after a cathode electrode 201 made of niobium (Nb) is formed on a support 200 made of, for example, a glass substrate, an insulating layer 202 made of SiO ₂ and a conductive layer are sequentially formed thereon. The gate electrode 203 is formed by forming a film and then patterning the conductive layer.
Is formed, and the gate electrode 203 and the insulating layer 202 are further formed.
An opening 204 is formed (see FIG. 18A).

[Step-20] Next, as shown in FIG. 18B, a peeling layer 206 is formed by obliquely depositing aluminum on the gate electrode 203. At this time, the peeling layer 206 is formed on the gate electrode 203 without substantially depositing aluminum on the bottom surface of the opening 204 by selecting a sufficiently large incident angle of the deposition particles with respect to the normal line of the support 200. can do. The peeling layer 206 protrudes in an eave shape from the opening end of the opening 204, whereby the diameter of the opening 204 is substantially reduced.

[Step-30] Next, for example, molybdenum (Mo) is vertically deposited as a conductive material on the entire surface. At this time, as shown in FIG. 19A, as the conductive material layer 205a having the overhang shape grows on the separation layer 206, the substantial diameter of the opening 204 is gradually reduced. The deposition particles contributing to deposition at the bottom of the portion 204 gradually become limited to those passing near the center of the opening 204. As a result, a conical deposit is formed at the bottom of the opening 204, and the conical deposit becomes the electron-emitting portion 205.

[Step-40] Thereafter, as shown in FIG. 19B, the separation layer 206 is separated from the surface of the gate electrode 203 by an electrochemical process and a wet process, and a conductive material above the gate electrode 203 is formed. The layer 205a is selectively removed.

[0012]

The electron emission characteristics of the field emission device having the structure shown in FIG. 19B are such that the electron emission from the edge 203a of the gate electrode 203 forming the upper end of the opening 204 is performed. It largely depends on the distance to the tip of the portion 205. This distance is equal to the opening 204
Processing accuracy and diameter dimensional accuracy, film thickness accuracy and coverage (step coverage) of the conductive material layer 205a formed in [Step-30], and further, the release layer 2 serving as a base thereof.
06 greatly depends on the shape accuracy.

Therefore, in order to manufacture a display device composed of a plurality of field emission devices having uniform characteristics, the conductive material layer 205a must be formed uniformly over the entire surface of the object to be formed. No. However, in a normal vapor deposition apparatus, conductive material particles are emitted with a certain spread angle from an evaporation source installed at one point, so that the layer thickness is symmetrical to the coverage near the center of the film-forming body and at the periphery. Sex is different. For this reason, the height of the electron-emitting portion is likely to vary, or the position of the vertex of the electron-emitting portion is likely to be shifted from the center of the opening portion 204, and the variation in the distance from the tip of the conical electron-emitting portion 205 to the gate electrode 203 is reduced. Difficult to control. Moreover, this variation in distance occurs not only within the same manufacturing lot but also between manufacturing lots, and causes image display characteristics of the display device, for example, unevenness in image brightness. Further, since the conductive material layer 205a is generally formed to a thickness of about 1 μm or more, the deposition method requires a deposition time of several tens of hours, and it is difficult to improve the throughput. There is also a problem that a device is required.

It is also very difficult to form the peeling layer 206 uniformly over the entire surface of the object to be deposited having a large area by oblique evaporation. Opening 20 provided in gate electrode 203
It is also very difficult to deposit the peeling layer 206 with high accuracy so that the peeling layer 206 extends like an eave from the edge of the fourth layer.
In addition, the formation of the release layer 206 not only varies in the plane of the support, but also tends to vary from lot to lot. Further, in order to manufacture a display device having a large area, it is extremely difficult to peel the release layer 206 over the entire glass substrate having a large area, and the peeling of the release layer 206 causes contamination, The manufacturing yield of the display device is reduced.

In addition, since the height of the conical electron emitting portion 205 is mainly determined by the thickness of the conductive material layer 205a, the degree of freedom in designing the electron emitting portion 205 is low. In addition, since it is difficult to arbitrarily set the height of the electron-emitting portion 205, when the distance from the electron-emitting portion 205 to the gate electrode 203 is reduced, the thickness of the insulating layer 202 must be reduced. Not get. However, when the thickness of the insulating layer 202 is reduced, the capacitance between the wirings (between the gate electrode 203 and the cathode electrode 201) cannot be reduced.
Not only does the load on the electric circuit of the display device increase, but also the in-plane uniformity and image quality of the display device deteriorate.

Further, the above-mentioned conical electron emitting portion 2
In 05, the electron emission characteristics may be different depending on the orientation of the crystal grain boundaries of the conductive material constituting the electron emission portion 205. There is no known technique for using a region having an optimal orientation as the electron-emitting portion 205.

Therefore, the present invention can solve the manufacturing problems in the conventional Spindt-type cold cathode field emission device and provide a plurality of cold cathode field emission devices having uniform and good electron emission characteristics. Cold cathode field emission device (hereinafter referred to as field emission device) that can be manufactured by a simple method
And a method of manufacturing the same, and a cold cathode field emission display (hereinafter, referred to as a display) configured using the field emission device.
A display device).

[0018]

According to the present invention, there is provided a field emission device comprising: (A) a cathode electrode formed on a support; and (B) a cathode electrode formed on the support and the cathode electrode. (C) a gate electrode formed on the insulating layer, (D) an opening that penetrates through the gate electrode and the insulating layer and exposes a cathode electrode at the bottom, and (E) a bottom of the opening. An electron emission portion is formed on the exposed cathode electrode, has a conical tip, and is made of a polycrystalline or amorphous conductive material.

A method for manufacturing a field emission device according to the present invention for achieving the above object is a method for manufacturing a field emission device according to the present invention. That is, (a) a step of forming a cathode electrode on a support, (b) a step of forming an insulating layer on a support including the cathode electrode, and (c) a step of forming a gate electrode on the insulating layer (D) forming an opening that penetrates through the gate electrode and the insulating layer and exposes the cathode electrode at the bottom, and (e) polycrystalline or non-crystalline for forming the electron emitting portion over the entire surface including the inside of the opening. Forming a crystalline conductive material layer;
(F) selectively forming a mask pattern made of a mask material layer on the conductive material layer with a planar arrangement capable of shielding a region of the conductive material layer located at the center of the opening; By etching the conductive material layer and the mask pattern under anisotropic etching conditions in which the etching rate of the material layer is faster than the etching rate of the mask pattern, the tip has a conical shape, and the conductive material is etched. Forming an electron-emitting portion made of a layer in the opening.

A display device of the present invention for achieving the above object is a display device to which the field emission device of the present invention is applied. That is, each pixel includes a plurality of pixels, and each pixel includes a plurality of field emission devices, an anode electrode provided on a transparent substrate facing the plurality of field emission devices, and a phosphor layer. (A) a cathode electrode formed on the support, (B) an insulating layer formed on the support and the cathode electrode, (C) a gate electrode formed on the insulating layer,
(D) penetrating through the gate electrode and the insulating layer and having the cathode electrode exposed at the bottom, and (E) formed on the cathode electrode exposed at the bottom of the opening, and the tip has a conical shape. And an electron emission portion made of a polycrystalline or amorphous conductive material.

In the method of manufacturing a field emission device, a display device or a field emission device according to the present invention (hereinafter sometimes collectively simply referred to as the present invention), the electron emitting portion is made of a polycrystalline or amorphous conductive material. Therefore, smoothness of the surface and high uniformity of the shape and dimensions are achieved. This is related to the direction of the crystal grain boundary of the conductive material forming the tip of the electron-emitting portion. The grain boundary has a higher surface free energy than the inside of the crystal grain, and is etched faster than the crystal grain, for example, when attacked by an etching species. In particular,
In the microfabrication process for manufacturing field emission devices,
In many cases, processing by anisotropic dry etching is performed, and many types of etching in the anisotropic dry etching are perpendicularly incident on the support. Therefore, the surface to be processed having many crystal grain boundaries along the direction perpendicular to the support tends to increase in surface roughness due to anisotropic dry etching, and it is difficult to control the shape. On the other hand, in a polycrystalline or amorphous conductive material, since the crystal grain boundaries are not aligned in one direction, the crystal grain boundaries are oriented in a specific direction with respect to the surface to be etched, particularly with respect to the support. It is not intensively exposed along the vertical direction. Therefore, the surface to be processed, that is, the surface of the tip portion of the electron-emitting portion becomes smooth, and the size and shape of the electron-emitting portion become highly uniform.

In the field emission device and display device of the present invention
Therefore, the electron emitting portion can be in a polycrystalline or amorphous state.
Conductive material that emits electrons repeatedly under a high electric field.
It has sufficient resistance to temperature rise due to emission and electron emission.
From materials that can withstand the thermal process involved in the manufacturing process
It can be selected as appropriate. Also, the field emission element of the present invention
In the manufacturing method of the element, the conductive material layer is polycrystalline or non-crystalline.
A conductive material layer that can assume a crystalline state and a high electric field
Electron emission under temperature and temperature rise accompanying electron emission
It has sufficient heat resistance and the heat
Can be appropriately selected from conductive material layers that can withstand
You. Above all, polysilicon and amorphous silicon
Means that high-speed film formation by CVD method is possible,
Preferred for reasons such as a proven track record in the process
It is a new conductive material. However, polysilicon and
In order to impart conductivity to amorphous silicon,
10 ¹⁶-10²⁰/ Cm^ThreeImpurities introduced on the order of
Is preferred. As a method for introducing impurities, CV
In method D, a source gas is mixed with a dopant (impurity) gas.
And the method of introducing simultaneously with the film formation, or impurities
Polysilicon layer or amorphous layer deposited without
Impurity in the silicon layer by ion implantation or diffusion
There is a way to introduce.

From the viewpoint of enhancing the electron emission efficiency, it is necessary that the tip of the electron emitting portion has a conical shape such as a conical shape, but as long as the tip has such a shape, The shape of the lower end portion, that is, the portion in contact with the cathode electrode does not matter. For example, the electron emission portion can be composed of a columnar portion embedded in the bottom of the opening and a conical sharpened portion formed integrally with the columnar portion. In such a case, even if the shape of the sharp portion is defined in a self-aligned manner for reasons of a manufacturing process described later, by appropriately selecting the height of the columnar portion, the height of the electron emitting portion in the opening can be increased. Specifically, it is possible to adjust the distance from the tip of the electron emission section to the gate electrode.

In the present invention, when the conductive material constituting the electron-emitting portion is polysilicon or amorphous silicon, the electron-emitting portion has a cap layer on the front end surface,
The cap layer can be made of a material having a higher electron emission efficiency than polysilicon or amorphous silicon. Here, a material having a high electron emission efficiency means that the reduction ratio of the height of the potential barrier is relatively large with respect to an externally applied electric field having a constant intensity, that is, the work function is greatly reduced. It is a material that can emit many electrons. As a constituent material of the cap layer, barium oxide (Ba)
O), magnesium oxide (MgO), lithium fluoride (LiF), barium fluoride (BaF ₂ ) can also be used, but high melting point metal, high melting point metal silicide, and a combination of high melting point metal and high melting point metal silicide are particularly preferable. It is suitable. As the refractory metal, tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), molybdenum (Mo), chromium (Cr) can be typically used. And compounds of these metals and silicon. When the cap layer is composed of a combination of a high melting point metal and a high melting point metal silicide, the layer structure of the cap layer is such that the upper layer side is a high melting point metal layer and the lower layer side is a high melting point metal silicide layer. This is a self-aligned silicidation process, so-called SALICIDE (Self-ALIgned SiliC).
IDE) process, which will be described later.

When the cap layer is formed of a high-melting-point metal or a high-melting-point metal silicide by an ordinary thin film forming technique, the cap layer often becomes crystalline with crystal grain boundaries oriented in a direction substantially perpendicular to the cathode electrode. This means that the electron flow inside the cap layer does not cross the grain boundaries. Therefore, disorder of the crystal structure in the cap layer is unlikely to occur, and the durability of the electron-emitting portion that emits electrons when exposed to a high electric field can be increased. Therefore, a field emission device,
As a result, it is possible to extend the life of a display device incorporating this. Furthermore, the electron emission efficiency is improved when the cap layer is formed, as compared with the case where the electron emission portion made of polysilicon or amorphous silicon is used alone.

In the field emission device or the display device according to the present invention, a second insulating layer may be further formed on the gate electrode, and a focusing electrode may be formed on the second insulating layer. In a so-called high-voltage type display device in which the potential difference between the anode electrode and the cathode electrode is on the order of 5 kV and the distance between the two electrodes is relatively long (distance is about 1 mm), the focusing electrode emits from the electron emission portion. This member is provided to prevent the divergence of the electron trajectory. By improving the convergence of the emitted electron trajectories, crosstalk between pixels is reduced, color turbidity is prevented particularly when color display is performed, and pixels are further miniaturized to achieve higher definition of a display screen. It becomes possible.

In the method for manufacturing a field emission device according to the present invention, in the step (e), a concave portion reflecting a step between the upper end surface and the bottom surface of the opening is generated on the surface of the conductive material layer. In the step (2), a mask material layer is formed on the entire surface of the conductive material layer so that the surface is substantially flat, and the mask material layer is etched until the flat surface of the conductive material layer is exposed. Preferably, a mask pattern is formed. The mask material layer is a material whose etching rate in the next step (g) can be set lower than the etching rate of the conductive material layer, and has fluidity at an appropriate stage of formation so that the surface can be flattened. It is composed of the material to be obtained. Examples of the material constituting the mask material layer include a resist material, SOG (spin-on-glass), and a polyimide resin, and these materials can be easily applied by a spin coating method. Alternatively, a material such as BPSG (boron / phosphorus silicate glass) that can be heated and reflowed after film formation to flatten the surface may be used.

In the step (g), before the etching front of the conductive material layer reaches the surface of the cathode electrode, the portion of the conductive material layer filling the bottom of the opening is left as a columnar portion of the electron emission portion. The etching may be terminated at first. Here, the etching front is the forefront that is the fastest in the surface to be etched, in other words, the deepest that progresses toward the support. In the method for manufacturing the field emission device of the present invention, since the electron emission portion having the conical tip is formed in a self-aligned manner, etching is performed until the etching front reaches the surface of the cathode electrode. The entire electron emitting portion becomes a cone, and if the etching is further continued, the bottom surface of the cone gradually shrinks. However, before reaching the surface of the cathode electrode, the etching front only descends along or near the inner wall surface of the opening, and the distance from the etching front to the surface of the cathode electrode is higher than the height of the columnar portion. Is equal to That is, the height of the columnar portion can be adjusted by stopping the etching front by controlling the etching conditions and time.

After the step (g), (h) a cap layer made of a material having a higher electron emission efficiency than polysilicon or amorphous silicon may be formed on the surface of the tip of the electron emission portion. Good. As a material for forming the cap layer, a high melting point metal and / or a high melting point metal silicide can be given. As a method for forming the cap layer,
Two methods are conceivable. One is selective growth and the other is the salicide process.

The selective growth is typically possible by the CVD method, and the refractory metal can be selectively grown on the surface of the tip of the electron-emitting portion without growing on the surface of the insulating layer. The cap layer formed of the refractory metal formed in this way contributes to the improvement of the electron emission efficiency of the electron emitting portion as it is, but a part or the whole of the cap layer is made of polysilicon constituting the electron emitting portion. Alternatively, a part or the whole may be changed to a high melting point metal silicide by reacting with amorphous silicon. That is, to apply the salicide process, the step (h) is further added.
(H-1) a step of forming a refractory metal layer on the entire surface including the tip surface of the electron emitting portion, and (h-2) reacting the refractory metal layer with the tip surface of the electron emitting portion by heat treatment; The step of forming the refractory metal silicide layer and the step of (h-3) removing an unreacted portion of the refractory metal layer to obtain a cap layer composed of the refractory metal silicide can be performed. It is suitable. In the step (h-2), the silicidation reaction proceeds from the interface between the tip surface of the electron-emitting portion and the refractory metal. By controlling the temperature and time of the heat treatment at this time, it is possible to leave a part of the thickness of the refractory metal layer unreacted or to change the refractory metal silicide over the entire thickness. it can.

The support constituting the field emission device of the present invention only needs to have at least a surface made of an insulating member. A glass substrate, a glass substrate having an insulating film formed on the surface, a quartz substrate, and an insulating material provided on the surface A quartz substrate with a film formed thereon and a semiconductor substrate with an insulating film formed on the surface can be used.

The constituent material of the insulating layer is SiO ₂ , S
iN, SiON, or a cured glass paste can be used alone or appropriately laminated. Known processes such as a CVD method, a coating method, a sputtering method, and a printing method can be used for forming the insulating layer.

The gate electrode is made of tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (A).
l), a metal layer such as copper (Cu), silver (Au), or an alloy layer containing these metal elements, a metal compound layer containing these metal elements, or a semiconductor layer such as diamond. Can be. In the present invention, when the electron-emitting portion is formed by etching, the gate electrode or the cathode electrode may serve as a base for etching. In such a case, it is preferable to select a material that can secure an etching selectivity with respect to the conductive material layer that forms the electron-emitting portion.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments).

Embodiment 1 Embodiment 1 relates to the field emission device of the present invention, a display device having such a field emission device, and a method of manufacturing the field emission device. The conductive material constituting the electron-emitting portion of the field emission device of the first embodiment is a polycrystalline conductive material, specifically, polysilicon, and is constituted by a columnar portion and a sharp portion. FIG. 1 shows a schematic partial cross-sectional view of such a field emission device. FIG. 2 is a schematic partial cross-sectional view of the display device. Further, a method of manufacturing the field emission device is shown in FIGS.

This field emission device has, for example, a support 10 made of a glass substrate, a cathode electrode 11 made of chromium (Cr), an insulating layer 12 made of SiO ₂ , a gate electrode 13 made of chromium, and a conical shape. It has an electron emission portion 18 having the same. Here, the cathode electrode 11
Is provided on the support 10. The insulating layer 12 is formed on the support 10 and the cathode electrode 11, and the gate electrode 13 is formed on the insulating layer 12. A circular opening 19 with the cathode electrode 11 exposed at the bottom is provided in the gate electrode 13 and the insulating layer 12, and the upper part of the side wall surface of the opening 19 provided in the insulating layer 12 is
Is receded from the open end of. The electron emission portion 18 is composed of a columnar portion 16c embedded in the bottom of the opening portion 19, and a cone-shaped, specifically, a cone-shaped sharpened portion 16t formed integrally with the columnar portion 16c. The surface of the sharpened portion 16t is smooth, and the height and dimensions of the sharpened portion 16t are highly uniform.

The display device according to the first embodiment is composed of a plurality of pixels as shown in FIG. Each pixel includes a plurality of the above-described field emission devices, and an anode electrode 102 and a phosphor layer 101 provided on a transparent substrate 100 so as to face each other. The anode electrode 102 is made of aluminum, and is formed so as to cover the phosphor layer 101 formed in a predetermined pattern on a transparent substrate 100 made of glass. The order of lamination of the phosphor layer 101 and the anode electrode 102 on the transparent substrate 100 may be reversed, but in this case, the anode electrode 102 is located in front of the phosphor layer 101 when viewed from the observation surface side of the display device. The anode electrode 102 with ITO (indium
It must be made of a transparent conductive material such as tin oxide.

In the actual configuration of the display device, the field emission element is a component of the cathode panel CP, the anode electrode 102 and the phosphor layer 101 are components of the anode panel AP, and these cathode panel CP and anode panel AP are used. Are joined via a frame (not shown), and the space surrounded by both panels and the frame is evacuated to high vacuum. The scanning circuit 1 is connected to the electron emission section 18 through the cathode electrode 11.
03, a relatively positive voltage is applied to the gate electrode 13 from the control circuit 104, and a higher positive voltage than the gate electrode 13 is applied to the anode electrode 102 from the acceleration power supply 105. You. When display is performed on the display device, a video signal is input to the control circuit 104 and a scanning signal is input to the scanning circuit 103. Cathode electrode 1
Electrons e are extracted from the tip of the electron-emitting portion 18 by an electric field generated when a voltage is applied to the gate electrode 13 and the gate electrode 13. When the electrons e are attracted to the anode electrode 102 and collide with the phosphor layer 101, the phosphor layer 101 emits light and a desired image can be obtained.

Hereinafter, a method for manufacturing the field emission device according to the first embodiment will be described with reference to FIGS.

[Step-100] First, a cathode electrode 11 made of chromium (Cr) is provided on a support 10 made of a glass substrate. Specifically, a chromium layer having a thickness of about 0.5 μm is deposited on the support 10 by, for example, a DC magnetron sputtering method, and the chromium layer is patterned to form a plurality of strips extending parallel to the row direction. Of the cathode electrode 11 can be formed. The film forming conditions are exemplified in Table 1 below. Here, the reason why chromium was selected as the constituent material of the cathode electrode 11 is that polysilicon is used as the conductive material layer 16 (see FIG. 3B) in a later step.
This is because it has heat resistance to a film forming temperature (substrate temperature of about 600 ° C.) when forming a film by the method.

[0041]

[Table 1] Ar gas flow rate: 100 SCCM Pressure: 0.67 Pa DC power: 3 kW Support heating: None

Next, the support 1 including on the cathode electrode 11
0, an approximately 0.7 μm thick SiO 2 _TwoInsulating layer 1 made of
2 is formed by a plasma CVD method. Film formation of insulating layer 12
Uses TEOS (tetraethoxysilane) as a source gas.
Can be performed by a plasma CVD method. Deposition conditions
Are illustrated in Table 2 below.

[0043]

[Table 2] TEOS flow rate: 800 SCCM O ₂ flow rate: 600 SCCM Pressure: 1.1 × 10 ³ Pa RF power: 700 W Support temperature: 400 ° C.

Next, a conductive layer made of TiN is formed on the entire surface of the insulating layer 12 by a DC magnetron sputtering method to a thickness of about 0.1 mm.
A film having a thickness of 1 μm is formed, and the conductive layer is patterned to form a plurality of strip-shaped gate electrodes 13 extending in the column direction, that is, in the direction orthogonal to the cathode electrode 11. The film forming conditions are exemplified in Table 3 below.

[0045]

[Table 3] Ar flow rate: 25 SCCM N ₂ flow rate: 50 SCCM Pressure: 0.4 Pa DC power: 6 kW Support heating: 200 ° C. (gas heating)

Further, an etching stop layer 14 is formed on the entire surface. The etching stop layer 14 is not an indispensable member for the function of the field emission device, and serves to protect the gate electrode 13 when the conductive material layer 16 is etched in a later step. If the gate electrode 13 can have sufficiently high etching resistance with respect to the etching conditions of the conductive material layer 16, the etching stop layer 14 may be omitted. Here, according to the conditions of Table 2 described above, the thickness is about 0.5 mm.
A 1 μm SiO ₂ film is formed.

Next, a resist material layer (not shown) is formed on the etching stopper layer 14 by the usual photolithography technique, and the etching stopper layer 14, the gate electrode 13, and the insulating layer 12 are formed using this resist material layer as a mask. Etching is performed to form an opening 15 at the bottom where the cathode electrode 11 is exposed. Etching stop layer 14 and insulating layer 12
Table 4 shows the etching conditions for the gate electrode 1.
Table 5 below illustrates the etching conditions of No. 3. By the above process, as shown in FIG.
An opening 15 of 5 μm is formed.

[0048]

[Table 4] Etching equipment: Magnetron RIE equipment C ₄ F ₈ Flow rate: 50 SCCM Pressure: 2 Pa RF power: 1200 W (13.56 MHz)

[0049]

[Table 5] Etching device: RF bias application type ECR etching device BCl ₃ flow rate: 60 SCCM Cl ₂ flow rate: 90 SCCM Pressure: 2.1 Pa Microwave power: 1000 W (2.45 GHz) RF bias power: 50 W (2 MHz)

[Step-110] Next, as shown in FIG. 3B, a conductive material layer 16 for forming an electron-emitting portion is formed on the entire surface including the inside of the opening 15. Here, the conductive material layer 1
6, a polysilicon layer having a thickness of about 0.4 μm is
The film is formed by the VD method. The film forming conditions are exemplified in Table 6 below. Under this condition, PH ₃ is contained as a dopant gas in the film formation atmosphere, and phosphorus (P) as an impurity is introduced at a concentration of about 10 ²⁰ / cm ³ simultaneously with the film formation. At this time, the surface of the formed conductive material layer 16 has a recess 1 reflecting the step between the upper end surface and the bottom surface of the opening 15.
6a is formed. After the film formation, furnace annealing or short-time annealing (RTA) is performed to activate the impurities. In the case of polysilicon, the resistivity can be reduced to the order of 1 Ω · cm by annealing at 600 ° C. and to the order of 10 ⁻³ Ω · cm by annealing at 900 ° C. Here, the heat resistance of the glass constituting the support 10 and the chromium constituting the cathode electrode 11 is taken into consideration.
Anneal at ° C.

[0051]

[Table 6] SiH ₄ flow rate: 500 SCCM PH ₃ flow rate: 0.35 SCCM He flow rate: 50 SCCM Pressure: 80 Pa Growth temperature: 600 ° C

[Step-120] Next, as shown in FIG. 4A, a mask material layer 17 having a thickness of about 0.35 μm is formed on the entire surface of the conductive material layer 16 by spin coating to make the surface substantially flat. It forms so that it may become.

[Step-130] Subsequently, the mask material layer 17 is etched until the flat surface of the conductive material layer 16 is exposed, as shown in FIG.
A mask pattern 17e composed of a mask material layer 17 for embedding a is formed. The etching conditions are illustrated in Table 7 below. The mask material layer 17 absorbs the concave portions 16 a of the conductive material layer 16, achieves a substantially flat surface, and has a plane that can shield a region of the conductive material layer 16 located at the center of the opening 15. It is formed with an arrangement.

[0054]

[Table 7] Etching apparatus: Parallel plate type RIE apparatus Ar flow rate: 50 SCCM O ₂ flow rate: 80 SCCM Pressure: 26.7 Pa RF power: 120 W (13.56 MHz)

[Step-140] Next, as shown in FIG. 5, the conductive material layer 16 is etched to form the electron emission portions 18. The etching conditions are illustrated in Table 8 below. This etching is performed under anisotropic etching conditions in which the etching rate of the conductive material layer 16 is higher than the etching rate of the mask pattern 17e.

[0056]

[Table 8] Etching apparatus: RF bias application type ECR etching apparatus Cl ₂ flow rate: 120 SCCM O ₂ flow rate: 4 SCCM Pressure: 4 Pa Microwave power: 1200 W (2.45 GHz) RF bias power: 70 W (2 MHz)

[Step-150] After that, the etching stop layer 14 is removed under isotropic etching conditions, and the side wall surface above the opening provided in the insulating layer 12 inside the opening 15 is receded. The field emission device shown in FIG. 1 is completed. The isotropic etching can be performed by dry etching using radicals as a main etching species, such as chemical dry etching, or wet etching using an etchant. Here, wet etching is performed using a mixture of 49% hydrofluoric acid and pure water at a ratio of 1: 100 (volume ratio). Next, a cathode panel CP on which a number of such field emission devices are formed
Is combined with the anode panel AP to produce a display device. Specifically, a frame made of ceramics or glass and having a height of about 1 mm is prepared, and the frame and the anode panel AP, and the frame and the cathode panel CP are prepared.
And a sealing material made of frit glass is applied in advance, and after the sealing material is dried, it is heated at about 450 ° C. for 10 minutes.
It may be fired for up to 30 minutes. After that, the inside of the display device is
Evacuation is performed until the degree of vacuum reaches about 0 ^-4 Pa, and sealing is performed by an appropriate method.

Here, the mechanism in which the electron-emitting portions 18 are formed in a self-aligned manner in [Step-140] will be described with reference to FIG. FIG. 6A is a schematic diagram showing how the surface profile of the object to be etched changes at regular intervals as the etching proceeds.
FIG. 6B is a graph showing the relationship between the etching time and the thickness of the object to be etched at the center of the opening. The thickness of the mask pattern 17e of aperture center h _p, the height of the electron emission portion of the aperture center and h _e.

Under the above etching conditions, the etching rate of the conductive material layer 16 is naturally higher than the etching rate of the mask pattern 17e made of the resist material.
In a region where the mask pattern 17e does not exist, the conductive material layer 16 starts to be etched immediately, and the surface of the object to be etched quickly descends. In contrast, the mask
In the area where the pattern 17e exists, first, the mask
If the pattern 17e is not removed, the underlying conductive material layer 1
Since the etching of 6 does not start, the mask pattern 1
While 7e is etched rate of decrease of the thickness of the object to be etched is slow (h _p decreasing segment), the first time when the mask pattern 17e is lost, thickness reduction rate mask pattern of the etching object similar to 17e nonexistent region of faster (h _e decreasing segment). start timing of h _p decreasing segment is slowest at the opening center of the mask pattern 17e is maximum thickness, faster toward the periphery thin opening in the mask pattern 17e. In this manner, the shape of the tip of the electron emitting section 18 becomes conical.

Here, the etching front is shown by a black circle in FIG. In the example shown in this figure, since the maximum diameter of the mask pattern 17e substantially coincides with the diameter of the opening 15, the etching front descends substantially along the inner wall surface of the opening 15 as the etching proceeds. go. If the maximum diameter of the mask pattern 17 e does not substantially match the diameter of the opening 15, for example, if the maximum diameter of the mask pattern 17 e is smaller than the diameter of the opening 15, the etching front will be within the opening 15. It will descend at a position inside the wall. Of the conductive material layer remaining inside the opening 15, a portion above the etching front is a sharp portion, and a portion below the etching front is a columnar portion. Therefore, after the etching front reaches the surface of the cathode electrode 11, there is naturally no columnar portion. In other words, in order to leave the columnar portion, the etching must be completed before the etching front reaches the surface of the cathode electrode 11.

Note that the conical shape of the sharp portion changes depending on the ratio of the etching rate of the conductive material layer 16 to the etching rate of the mask pattern 17e, that is, the "selection ratio to resist". The higher the resist selectivity, the greater the mask
Since the film thickness of the conductive material layer 16 becomes more severe than the film thickness of the pattern 17e, the conical shape of the sharp portion 16t becomes steeper. The selectivity to resist decreases as the ratio of the O ₂ flow rate to the Cl ₂ flow rate increases. When an etching apparatus that can change the incident energy of ions by using a substrate bias is used, the RF bias power is increased, or the frequency of the AC power supply for applying the RF bias is decreased, thereby reducing the energy consumption. The resist selectivity can be reduced. The value of the resist selectivity is 1.5 or more, preferably 2
The above is selected, more preferably 3 or more.

According to the method of manufacturing the field emission device according to the first embodiment, the surface of the sharp portion 16t is extremely smooth.
The reason why such a smooth surface is achieved will be described with reference to FIG. FIG. 7A is a schematic diagram showing a state in which a conductive material layer 16 made of polysilicon is formed on the entire surface including the inside of the opening 15, and FIG. 7B is a diagram showing anisotropic dry etching conditions. The state where the conductive material layer 16 is etched below and the electron emission portion 18 is formed is shown. Since the conductive material layer 16 is polycrystalline, the grain boundaries are not aligned in a certain direction. When such a layer is etched under anisotropic dry etching conditions, the probability that the etching seed is incident on the crystal grain boundaries is low, and the probability that the crystal grain boundaries are substantially coincident with the incident direction of the etching seeds is even lower. . That is, most of the etching proceeds not by the etching species incident on the crystal grain boundaries (indicated by white circles in the figure) but by the etching species incident on the crystal grains (indicated by black circles in the figure). Therefore, it is possible to avoid an inconvenience such as a locally accelerated etching along the crystal grain boundary and a roughened surface of the surface to be etched, thereby obtaining a smooth electron emitting portion having a uniform size and shape. Becomes

(Second Embodiment) A second embodiment is a modification of the first embodiment. The field emission device of the second embodiment is different from the field emission device of the first embodiment in that a cap layer is provided on the surface of the tip portion of the electron emission portion, more specifically, on the surface of the sharp portion 16t. The layer is made of a material having a higher electron emission efficiency than polysilicon or amorphous silicon. FIG. 8 shows a schematic partial cross-sectional view of the field emission device of the second embodiment, and FIG. 9 shows a process chart in the case of manufacturing this cap layer by a selective growth process. The reference numerals in these figures are partially common to FIG. 1, and detailed description of the components common to FIG. 1 will be omitted.

In the field emission device of the second embodiment,
As shown in FIG. 8, the electron emission section 28 has a configuration in which a cap layer 20c is provided at the tip of the electron emission section in the field emission device of the first embodiment. A deposition layer 20d is formed on the opening end face of the gate electrode 13, and this deposition layer 20d is made of tungsten like the cap layer 20c, and is formed simultaneously with the cap layer 20c in the selective growth process. There is no intention.

Hereinafter, a method of manufacturing the field emission device according to the second embodiment will be described with reference to FIG.

First, the steps up to [Step-140] of the first embodiment are performed in the same manner, and the columnar portion 16c embedded in the bottom of the opening 15 and the conical sharp portion formed integrally with the columnar portion 16c are formed. 16t (corresponding to the electron-emitting portion 18 in the first embodiment). Next, low pressure CVD
The tungsten is selectively grown by the method. The conditions for selective growth are shown in Table 9 below. Thereby, as shown in FIG. 9, the cap layer 20c is formed on the surface of the sharpened portion 16t to form the electron emission portion 28, and the precipitation layer 20d is formed on the side end surface of the gate electrode 13 made of TiN. . The cap layer 20c is a layer that substantially contributes to electron emission. The cap layer 20 obtained by the selective growth is
The direction of the crystal grain boundary is substantially perpendicular to the cathode electrode 11 and is made of crystalline material, so that the electron emission efficiency and the durability are improved. Thereafter, the etching stop layer 14 is removed under isotropic etching conditions, and the opening 19 is formed by retreating the side wall surface above the opening provided in the insulating layer 12 inside the opening 15. 8 is completed.

[0067]

[Table 9] WF ₆ flow rate: 10 SCCM SiH ₄ flow rate: 7 SCCM H ₂ flow rate: 1000 SCCM Ar flow rate: 10 SCCM Pressure: 26.6 Pa Support temperature: 260 ° C.

(Embodiment 3) Embodiment 3 is a modification of Embodiment 2. The difference between the field emission device of the third embodiment and the field emission device of the second embodiment is that the cap layer is formed by a salicide process, and as a result, the cap layer is formed of a refractory metal silicide layer and a refractory metal layer. In two layers. FIG. 10 is a schematic partial cross-sectional view of the field emission device according to the third embodiment, and FIGS. 11 and 12 show a method of manufacturing the cap layer by a salicide process. The reference numerals in these figures are partially common to FIG. 1, and detailed description of the components common to FIG. 1 will be omitted.

In the field emission device of the third embodiment,
As shown in FIG. 10, the electron emission section 38 is the same as that of the first embodiment.
The cap layer 2 composed of the refractory metal silicide layer 22 and the refractory metal layer 21e is provided on the surface of the tip of the electron emission portion 18 of the field emission device, more specifically, on the surface of the sharp portion 16t.
Three. By forming the high melting point metal silicide layer 22, the resistance of the entire electron emitting portion 38 can be reduced as compared with the case where the high melting point metal layer 21e alone forms the cap layer.

Hereinafter, a method of manufacturing the field emission device according to the third embodiment will be described with reference to FIGS.

[Step-300] First, steps up to [Step-140] of the first embodiment are performed in the same manner, and the columnar portion 16c embedded in the bottom of the opening 15 and the columnar portion 16c are formed integrally. A conical pointed portion 16t is formed. Next, a refractory metal layer 21 is formed on the entire surface including the inside of the opening 15 by a sputtering method. The refractory metal layer 21 is made of titanium (T) by DC magnetron sputtering.
i) forming a layer; The sputtering conditions are illustrated in Table 10 below.

[0072]

[Table 10] Ar gas flow rate: 100 SCCM Pressure: 0.67 Pa DC power: 3 kW Heating of support: None

[Step-310] Next, for example, at 600 ° C.
For a short time (RTA) to form a refractory metal layer 21 made of titanium and a sharp portion 16t made of polysilicon.
And a refractory metal silicide layer 2
Form 2 The refractory metal silicide layer 22 formed at this time is a titanium silicide layer.

[Step-320] Next, the refractory metal layer 21
Is removed by etching using a mixed aqueous solution of ammonia and hydrogen peroxide. Thereby, as shown in FIG. 12, the refractory metal silicide layer 22 and the refractory metal
The cap layer 23 made of 1e is formed, and the electron emission portion 38 including the already formed sharp portion 16t and the columnar portion 16c is formed. After that, the etching stop layer 14 isotropically etched.
Is removed, and the insulating layer 1 inside the opening 15 is removed.
When the opening 19 is formed by retreating the side wall surface above the opening provided in 2, the field emission device shown in FIG. 10 is completed.

Depending on the temperature and annealing time of the silicidation annealing, as shown in FIG.
The entire melting direction of the refractory metal layer 21 in the region in contact with t may be silicided to form the cap layer 33 composed of only the refractory metal silicide.

(Embodiment 4) Embodiment 4 is also a modification of Embodiment 1. The field emission device of the fourth embodiment is different from the field emission device of the first embodiment in that a second insulating layer is further formed on the gate electrode, and a focusing electrode is formed on the second insulating layer. It is in. Note that in Embodiment 4, the insulating layer formed over the support and the cathode electrode is referred to as a first insulating layer, and is distinguished from the second insulating layer.

As shown in FIG. 14, the field emission device of the fourth embodiment includes a support 40 made of, for example, a glass substrate,
A cathode electrode 41 made of chromium (Cr) and SiO ₂
A first insulating layer 42 made of chromium, a gate electrode 43 made of chromium, a second insulating layer 44 made of SiO ₂ , a focusing electrode 45 made of chromium, and an electron emission section 48. Here, a plurality of cathode electrodes 41 are arranged on the support 40 in a strip shape. The first insulating layer 42 is formed of the support 4
0 and the cathode electrode 41, and the gate electrode 43 is formed on the first insulating layer 42. The second insulating layer 44 is formed on the gate electrode 43, and the focusing electrode 45 is formed on the second insulating layer 44.

The converging electrode 45, the second insulating layer 44, the gate electrode 43 and the first insulating layer 42 have the cathode electrode 4
An opening 47a is provided so as to expose 1.
The side wall surface of the opening 47a is formed by the processing surfaces of the focusing electrode 45, the second insulating layer 44, the gate electrode 43, and the first insulating layer 42. In order to realize a smooth emitted electron trajectory, It is preferable that the overall shape is such that the opening dimension decreases from the upper side toward the bottom side. Further, the upper end of the side wall surface of the opening provided in the second insulating layer 44 is recessed from the front end of the focusing electrode 45, and the upper end of the side wall surface of the opening provided in the first insulating layer 42 is the front end of the gate electrode 43. And the focusing electrode 45 and the gate electrode 43
Has a structure in which an electric field of a desired intensity can be efficiently formed in the opening 47a by reducing the thickness toward the tip. The electron emission portion 48 is made of polysilicon, and has a columnar portion 48c embedded at the bottom of the opening 47a.
And a conical sharpened portion 48t integrally formed with the columnar portion 48c.

Hereinafter, a method of manufacturing the field emission device according to the fourth embodiment will be described with reference to FIGS.

[Step-400] First, a plurality of strip-shaped cathode electrodes 41 made of chromium (Cr) and extending in parallel with the row direction are provided on a support 40 made of a glass substrate.
Subsequently, on the support 40 including the cathode electrode 41, S
A first insulating layer made of iO _{2 is} formed by a CVD method. The thickness of the first insulating layer 42 is set to about 0.7 μm. Next, a chromium layer is formed on the entire surface of the first insulating layer 42 by a sputtering method, and the chromium layer is patterned to form a plurality of strip-shaped gate electrodes 43 extending parallel to the column direction. (A)).

[Step-410] Next, a second insulating layer 44 of SiO ₂ is formed on the entire surface to a thickness of about 1.2 μm by the CVD method. Further, a chromium layer is formed on the entire surface of the second insulating layer 44 by a sputtering method, and a predetermined patterning is performed to form a focusing electrode 45. (See FIG. 15B).
Here, the pattern of the focusing electrode 45 is
This is a pattern in which a large number of circular holes are arranged in the same manner as in FIG.

[Step-420] Next, a resist layer 46 is formed in a predetermined pattern on the focusing electrode 45, and the focusing layer 45 and the second insulating layer 4 are formed using the resist layer 46 as a mask.
4. By sequentially etching the gate electrode 43 and the first insulating layer 42, a circular opening 47 in which the cathode electrode 41 is exposed at the bottom can be formed as shown in FIG. Here, the side wall surfaces of the openings provided in the focusing electrode 45, the second insulating layer 44, the gate electrode 43, and the first insulating layer 42 are inclined. This inclination is caused by the oxygen flow rate in the etching gas. For example, a condition for intentionally lowering the etching resistance of the resist layer 46, such as an increase in the ratio, is employed, and the pattern edge of the resist layer 46 is gradually retreated as the etching proceeds.
However, it is not limited to such a method. Therefore, the opening diameter of the opening 47 is not uniform in the depth direction, and the diameter of the opening 47 is about 0.5 μm near the focusing electrode 45.
In the vicinity of No. 3, the diameter is about 0.35 μm. That is, the tip of the focusing electrode 45 is recessed from the tip of the gate electrode 43. The original purpose of the focusing electrode 45 is to correct only the trajectories of electrons that are likely to deviate greatly from the direction perpendicular to the cathode electrode 41. If the aperture diameter of the focusing electrode 45 is too small, the electron emission of the field emission device will be reduced. The efficiency may be reduced. However, if the focusing electrode 45 has a larger opening than the gate electrode 43 as described above, that is, the opening provided in the focusing electrode 45 by appropriately controlling the etching conditions of the focusing electrode 45 and the gate electrode 43. If the diameter of the gate electrode 43 is smaller than the diameter of
It is extremely preferable that only a necessary convergence effect can be obtained without hindering electron emission.

[Step-430] Next, as shown in FIG. 16B, an electron emitting portion 48 is formed in the opening 47. The formation of the electron-emitting portion 48 is performed in the same manner as in [Step-110] to [Step-140] of the first embodiment, in which the entire surface of the conductive material layer is formed, the entire surface of the mask material layer is formed, and the mask pattern is formed. And a process combining etching of a conductive material layer. After that, by performing isotropic etching, an opening 47a is formed in the opening 47 by retreating the side wall surface of the opening provided in the first insulating layer 42 and the second insulating layer 44. FIG. The field emission device shown is obtained. Next, a display device is completed by performing the same steps as [Step-150] of the first embodiment.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. The details of the structure of the field emission device, the details of the processing conditions and the materials used in the method of manufacturing the field emission device, and the details of the structure of the display device to which the field emission device is applied are examples, and may be appropriately changed, selected, and combined. It is possible. For example, the field emission device described in the second and third embodiments may be provided with the focusing electrode described in the fourth embodiment. The cap layer described in the second embodiment or the third embodiment may be provided.

[0085]

As is clear from the above description, in the field emission device of the present invention, since the tip of the electron emission portion is made of a polycrystalline or amorphous conductive material, it is necessary to obtain a conical shape. The surface of the tip portion of the electron-emitting portion is smoothed at the time of processing, and the dimensions and the shape are highly uniform, so that the electron-emitting characteristics of the field emission device are uniform. When the electron-emitting portion has a cap layer at the tip, the electron-emitting efficiency and durability are improved. In the display device of the present invention to which such a field emission device is applied, even when the screen is enlarged, variation in luminance between pixels is suppressed, and a long life is achieved.

In the method of manufacturing a field emission device according to the present invention, the conical shape of the tip of the electron emission portion can be obtained by a series of self-aligned processes. Accordingly, not only the complexity of the process is reduced, but also in the case where a large-area cathode panel is to be manufactured, the electron-emitting portion having a uniform size and shape is formed over the entire surface of the cathode panel. It is possible to easily cope with an increase in the screen size of the display device. Since a self-aligned process can be applied, the number of photolithography steps can be reduced, and further, the investment in manufacturing equipment can be reduced, the processing time can be shortened, and the manufacturing cost of a field emission device and a display device can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a field emission device according to a first embodiment.

FIG. 2 is a schematic sectional view illustrating a configuration example of a display device of the present invention.

3A and 3B are schematic cross-sectional views illustrating a method for manufacturing the field emission device according to the first embodiment, in which FIG.
(B) represents a step of forming a conductive material layer.

4A to 4C are schematic cross-sectional views illustrating a method for manufacturing the field emission device according to the first embodiment, in which FIG. 4A is a process for forming a mask material layer, and FIG. 4B is a process for forming a mask pattern; Each step is represented.

FIG. 5 is a schematic cross-sectional view for explaining the method for manufacturing the field emission device of the first embodiment, following FIG. 4, showing a step of forming an electron emission portion.

6A and 6B are diagrams for explaining a mechanism of forming a self-aligned electron-emitting portion, wherein FIG. 6A is a schematic diagram showing a change in a surface profile of an object to be etched with progress of etching, and FIG.
Is a graph showing the relationship between the etching time and the thickness of the object to be etched at the center of the opening.

FIGS. 7A and 7B are schematic views illustrating the reason why a smooth surface is formed in anisotropic dry etching of a conductive material layer made of polysilicon; FIG. The state where the layer is formed,
(B) shows a state in which the conductive material layer is etched to form an electron emission portion.

FIG. 8 is a schematic sectional view showing a field emission device according to a second embodiment.

FIG. 9 is a schematic cross-sectional view showing a state where a cap layer is selectively grown in the method of manufacturing the field emission device of the second embodiment.

FIG. 10 is a schematic sectional view showing a field emission device according to a third embodiment.

11A and 11B are schematic cross-sectional views illustrating a method for manufacturing the field emission device according to the third embodiment, in which FIG. 11A shows a step of forming a refractory metal layer, and FIG. 11B shows a silicidation annealing step.

FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing the field emission device of the third embodiment, following FIG. 11, illustrating a step of forming an electron-emitting portion.

FIG. 13 is a schematic sectional view showing a modification of the field emission device of the third embodiment.

FIG. 14 is a schematic sectional view showing a field emission device according to a fourth embodiment.

15A and 15B are schematic cross-sectional views illustrating a method for manufacturing a field emission device according to a fourth embodiment, wherein FIG. 15A is a step of forming a conductive material layer for forming a gate electrode, and FIG. The respective steps of forming a conductive material layer are shown.

16A to 16C are schematic cross-sectional views illustrating a method for manufacturing the field emission device according to the fourth embodiment, wherein FIG. 16A is a step of forming an opening, and FIG. Respectively.

FIG. 17 is a partial schematic cross-sectional view showing a general configuration of a conventional display device.

18A and 18B are schematic cross-sectional views illustrating an example of a conventional method for manufacturing a Spindt-type field emission device, wherein FIG. 18A shows a state in which an opening is formed, and FIG. 18B shows a state in which a release layer is formed on a gate electrode. The respective formed states are shown.

FIG. 19 is a schematic cross-sectional view for explaining an example of a method for manufacturing a conventional Spindt-type field emission device, following FIG. 18, in which (A) shows a conical electron with the growth of a conductive material layer. (B) shows a state in which an emission portion is formed, and (B) shows a state in which an unnecessary conductive material layer is removed together with a release layer.

[Explanation of symbols]

10, 40: Support, 11, 41: Cathode electrode, 12: Insulating layer, 13, 43: Gate electrode,
15, 19, 47, 47a ··· Opening, 16 ··· Conductive material layer (for forming electron emitting portion), 16a ··· Concave, 16
t, 48t: pointed portion, 16c, 48c: columnar portion, 18, 28, 38, 48: electron emission portion, 17.
..Mask material layer, 17e ... Mask pattern, 2
0c, 23, 33... Cap layers, 21, 21e.
・ High melting point metal layer, 22 ・ ・ ・ High melting point metal silicide layer,
42 ... first insulating layer, 44 ... second insulating layer, 45
..Converging electrode, CP ... Cathode panel, AP
・ Anode panel, 100 ・ ・ ・ Transparent substrate, 101 ・
..Phosphor layer, 102... Anode electrode

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Sata 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5C031 DD09 DD17 DD19 5C036 EE02 EE14 EF01 EF06 EF09 EG12 EG15 EH06 EH08

Claims (18)

[Claims] (A) a cathode electrode formed on a support; (B) an insulating layer formed on the support and the cathode electrode; (C) a gate electrode formed on the insulating layer; (E) formed on the cathode electrode exposed on the bottom surface of the opening, penetrating the gate electrode and the insulating layer, and exposing the cathode electrode on the bottom surface; 1. A cold cathode field emission device comprising: an electron emission portion made of a crystalline or amorphous conductive material. 2. The cold cathode field emission device according to claim 1, wherein the conductive material constituting the electron emission portion is polysilicon or amorphous silicon. 3. The electron emission section according to claim 2, wherein the electron emission section comprises a columnar portion embedded in the bottom of the opening and a conical sharpened portion formed integrally with the columnar portion. 4. The cold cathode field emission device according to item 1. 4. The electron emission section according to claim 2, wherein the electron emission section has a cap layer on the tip surface, and the cap layer is made of a material having a higher electron emission efficiency than polysilicon or amorphous silicon. The cold cathode field emission device according to the above. 5. The cold cathode field emission device according to claim 4, wherein the material constituting the cap layer is a high melting point metal and / or a high melting point metal silicide. 6. The cold cathode field emission device according to claim 2, wherein a second insulating layer is further formed on the gate electrode, and a focusing electrode is formed on the second insulating layer. 7. A step of forming a cathode electrode on a support, (b) a step of forming an insulating layer on a support including on the cathode electrode, (c) a step of forming a gate electrode on the insulating layer. (D) forming an opening penetrating through the gate electrode and the insulating layer and exposing the cathode electrode at the bottom; and (e) forming a polycrystal for forming an electron emitting portion on the entire surface including the inside of the opening. (F) forming a mask pattern comprising a mask material layer in a plane arrangement capable of shielding a region of the conductive material layer located at the center of the opening; (G) etching the conductive material layer and the mask pattern under anisotropic etching conditions in which the etching rate of the conductive material layer is higher than the etching rate of the mask pattern; By the tip It has a conical shape, and manufacturing method of a cold cathode field emission device characterized by comprising an electron-emitting portion made of a conductive material layer to form in the opening from. 8. The semiconductor device according to claim 7, wherein said conductive material layer comprises a polysilicon layer or an amorphous silicon layer.
5. The method for manufacturing a cold cathode field emission device according to item 1. 9. In the step (e), a concave portion reflecting the step between the upper end surface and the bottom surface of the opening is formed on the surface of the conductive material layer. In the step (f), a mask is formed on the entire surface of the conductive material layer. Forming the material layer so that the surface is substantially flat, and etching the mask material layer until the flat surface of the conductive material layer is exposed, thereby forming a mask pattern including the mask material layer filling the recess. The method for manufacturing a cold cathode field emission device according to claim 8. In the step (g), before the etching front of the conductive material layer reaches the surface of the cathode electrode, the portion of the conductive material layer filling the bottom of the opening is left as a columnar portion of the electron emission portion. 9. The method according to claim 8, wherein the etching is completed. 11. After the step (g), (h) forming a cap layer made of a material having higher electron emission efficiency than polysilicon or amorphous silicon on the surface of the tip of the electron emission portion. The method for manufacturing a cold cathode field emission device according to claim 8, further comprising: 12. The method for manufacturing a cold cathode field emission device according to claim 11, wherein the material forming the cap layer is a high melting point metal and / or a high melting point metal silicide. 13. A material for forming the cap layer is a refractory metal, and in the step (h), a cap layer made of the refractory metal is selectively grown on the surface of the tip of the electron-emitting portion. 13. The method for manufacturing a cold cathode field emission device according to item 12. 14. A material forming the cap layer is a refractory metal silicide, and the step (h) further comprises: (h-1) a step of forming a refractory metal layer on the entire surface including the front end surface of the electron emission portion. (H-2) a step of reacting the tip surface of the electron-emitting portion with the high melting point metal layer by heat treatment to form a high melting point metal silicide layer; and (h-3) an unreacted portion of the high melting point metal layer. , So that
The method for manufacturing a cold cathode field emission device according to claim 12, comprising a step of obtaining a cap layer made of a high melting point metal silicide. 15. A pixel comprising a plurality of pixels, each pixel comprising: a plurality of cold cathode field emission devices; an anode electrode and a phosphor provided on a transparent substrate facing the plurality of cold cathode field emission devices. Each of the cold cathode field emission devices comprises: (A) a cathode electrode formed on a support; (B) an insulating layer formed on the support and the cathode electrode; and (C) an insulating layer formed on the support. (D) an opening which penetrates the gate electrode and the insulating layer and has a cathode electrode exposed at the bottom; and (E) a tip formed at the cathode electrode exposed at the bottom of the opening. A cold cathode field emission display device comprising: an electron emission portion having a conical shape and made of a polycrystalline or amorphous conductive material. 16. The cold cathode field emission display according to claim 15, wherein the conductive material forming the electron-emitting portion is polysilicon or amorphous silicon. 17. The device according to claim 16, wherein the electron-emitting portion has a cap layer on the surface of the tip portion, and the cap layer is made of a material having a higher electron-emitting efficiency than polysilicon or amorphous silicon. Cold cathode field emission display. 18. The cold cathode field emission display according to claim 17, wherein the material constituting the cap layer is a high melting point metal and / or a high melting point metal silicide.