KR20010019352A - A compressor of multiplier - Google Patents

Abstract

PURPOSE: A compressor of a multiplier is provided to compress partial data additionally generated from an operation of an encoder so that it can prevent a wrong operation of the multiplier caused from the calculation of the partial data and reduce a layout area. CONSTITUTION: The compressor(300) comprises a plurality of compressors(300_1, 300_2, 300_n-1, 300n). The compression units(300_1, 300_2, 300_n-1, 300n) includes a plurality of 4 by 2 compressors(COM1, COM2, COM3, COM5) and at least one 9 by 2 compressor(COM4) and compresses the partial data(P_DATA) from the encoder(10). The compressor(300) compresses not only the partial data with a bit number set in advance by the encoder(10), but also the partial data additionally generated by a minus symbol used in a calculation process within the decoder(10).

Description

Compressor of multiplier {A COMPRESSOR OF MULTIPLIER}

The present invention relates to a multiplier, and more particularly, to a compressor of a multiplier using a booth algorithm.

Referring to FIG. 1, a general multiplier includes an encoder 10, a compressor 30, and an adder 50. The multiplier uses a booth's algorithm to improve its operation speed. Here, the booth algorithm is a multiplication operation method for improving the multiplication operation speed by encoding a multiplier and a multiplicand of a plurality of bits and reducing the number of multiplication operations.

In this case, the encoder 10 is multiplied by external data (Y_DATA; Y0, Y1, ..., Yn-1, Yn) and multiplicative data (X_DATA; X0, X1, ..., Xn-1, Xn). It outputs partial product data (P_DATA [0:15]) encoded by. In this case, the multiplier data Y_DATA input to the encoder 10 is represented by operators as shown in Table 1 below by each encoder cell (not shown) in the encoder 10.

Y i + 1 Y i Y i-1 Recoded digit operator 0 0 0 0 0 × X 0 0 One +1 +1 × X 0 One 0 +1 +1 × X 0 One One +2 +2 × X One 0 0 -2 -2 × X One 0 One -One -1 × X One One 0 -One -1 × X One One One 0 0 × X

Thereafter, the multiplicative data X_DATA and the operators from the respective encoder cells are calculated and as a result, the partial data P_DATA is provided to the compressor 30. The compressor 30 provides the adder 50 with compressed data C_DATA obtained by compressing the partial data P_DATA from the encoder 10. The adder 50 outputs addition data A_DATA obtained by adding compressed data C_DATA from the compressor 30.

Referring to FIG. 2, the compressor 30 of FIG. 1 includes a plurality of compression units 30_1, 30_2,..., 30_n-1, 30_n. Each of the compression units 30_1, 30_2, ..., 30_n-1, 30_n includes 4-2 compressors COM1, COM2, ..., COMm-1, COMm. Each compression unit 30_1, 30_2, ..., 30_n-1, 30_n shown in FIG. 2 corresponds to a 32-bit multiplier, and each compression unit 30_1, 30_2, ..., 30_n-1, 30_n ) Has seven compressors (COM1, COM2, ..., COM6, COM7). Each of the compressors COM1, COM2,..., COM6, and COM7 compresses corresponding partial data P_DATA among partial data P_DATA [0: 15] outputted from the circuit of the preceding stage, that is, the encoder 10. One compression data (C_DATA) is output.

Referring to FIG. 3, each of the 4-2 compressors COM1, COM2, and COM5 of FIG. 2 includes full adders FA1, FA2,..., FA5, and FA6. Each of the full adders FA1, FA2, ..., FA5, FA6 corresponds to the full adder FA corresponding to the corresponding partial data P_DATA among the partial data P_DATA [0:15] from the encoder 10. The sum data SUM_DATA and the carry data CARRY_DATA obtained by adding the sum data SUM_DATA from and the full adder FA of the stage or the carry data CARRY_DATA from the outside are output. The compressed data C-DATA compressed by the respective 4-2 compressors COM1, COM2, and COM5 by the addition operation of the full adders FA1, FA2, ..., FA5, FA6 is Finally, it is provided to the adder 50.

However, in the multiplier for multiplying multipliers and multiplicative data (Y_DATA, X_DATA) of a plurality of bits (for example, 16, 24, 32, 40, 48, 56, 64 bits, etc.), the compressor 30 having the structure as shown in FIG. Some problems arise when is used. One of them is a problem in that the encoder 10 cannot process one bit partial data P_DATA that is additionally generated in the process of calculating the multiplier and multiplicative data Y_DATA and X_DATA. The 1-bit partial data P_DATA additionally generated at the encoder 10 is generated by the encoder cell of the encoder 10 generating operators as shown in [Table 1] and a partial product generation cell (not shown). ) Is generated by the sign of the operator in determining the output path of the multiplicative data (X_DATA) according to the corresponding operator.

For example, as shown in FIG. 2, 16-bit partial data P_DATA [0:15] and a negative sign are obtained from encoder 10 of the multiplier that multiplies 32-bit multiplier and multiplicative data Y_DATA and X_DATA. Assuming that one bit partial data P_DATA (not shown) is provided to the compressor 30 by an operator, the structure of the compression units 30_1, 30_2,..., 30_n-1, 30_n as shown in FIG. Compressor 30 having the above does not process the remaining one bit of partial data P_DATA. In a general multiplier, another operation must be performed in order to deal with this problem, which causes a problem of adding a complicated circuit for the operation.

An object of the present invention is to provide a compressor of a multiplier that compresses both partial data of a predetermined number of bits and additionally generated partial data in a multiplication operation.

1 is a block diagram showing the structure of a general multiplier;

2 is a block diagram showing the structure of the compressor of FIG.

3 is a block diagram showing the structure of a four-to-two compressor in the compressor of FIG.

4 is a block diagram showing the structure of a compressor according to the present invention;

5 is a block diagram showing the structure of the nine-to-two compressor of FIG.

* Description of the symbols for the main parts of the drawings *

10: encoder 30: compressor

50: adder

(Configuration)

According to one aspect of the present invention for achieving the object described above, the multiplier according to the present invention is a plurality of bits of the first partial data and the first partial data of the multi-bit multiplier data and the multi-bit multiplier data encoded Encoding means for outputting at least one bit of second partial data which is further generated by the sign thereof upon generation of; Compression means for outputting compressed data compressing the first and second partial data from the encoding means; And adding means for outputting the addition data obtained by adding the compressed data from the compression means as a multiplication result, wherein the compression means includes a plurality of compression parts for compressing corresponding partial data among the partial data; The compression unit includes a first group of compressors for compressing the first partial data and a second group of compressors for compressing corresponding partial data of the first and second partial data. Here, each of the first group of compressors is a four input two output compressor. And, each of the second group of compressors is a nine input two output compressor.

(Action)

By such an apparatus, not only partial data of the multiplier operator predetermined number of bits but also additionally generated partial data are simultaneously compressed.

(Example)

Hereinafter, reference will be described in detail with reference to FIGS. 4 to 5 according to a preferred embodiment of the present invention.

4, the compressor 300 of the multiplier according to the present invention includes a plurality of compression units 300_1, 300_2, 300_n-1, 300_n. Each of the compression units 300_1, 300_2, 300_n-1, and 300_n includes a plurality of four to two compressors COM1, COM2, COM3, and COM5 and at least one nine to two compressor COM4. Compress partial data (P_DATA) from At this time, the compressor 300 of the multiplier according to the present invention is additionally generated not only by the partial data P_DATA of the predetermined number of bits from the encoder 10 but also by the negative sign of the operator used in the calculation process in the encoder. It is characterized by compressing even partial data (P_DATA). As such, by compressing the partial data P_DATA that is additionally generated during the operation of the encoder 10, not only the malfunction of the multiplier 300 by the operation of the partial data P_DATA is prevented, but also the An increase in layout area is prevented.

4, the compressor 300 of the multiplier according to the present invention includes a plurality of compression units 300_1, 300_2, ..., 300_n-1, 300_n. Each of the compression units 300_1, 300_2,..., 300_n-1, 300_n includes a plurality of compressors COM1, COM2,..., COMm-1, COMm. Here, since FIG. 4 is an embodiment of a compressor implemented in a 32-bit multiplier, each of the compression units 300_1, 300_2,..., 300_n-1, 300_n uses compressors COM1, COM2, COM3, COM4, and COM5. Include.

Each of the compressors COM1, COM2, COM3, and COM5 of the compressors COM1, COM2, COM3, COM4, and COM5 includes four bits of partial data P_DATA and two bits of compressed data C_DATA and carry data CARRY. 4 to 2 compressors, which are not shown, and compressor COM4 is a 9 to 2 compressor that compresses 9 bits of partial data P_DATA into 2 bits of compressed data C_DATA and carry data CARRY. .

Referring to FIG. 5, the nine-to-two compressor COM4 of FIG. 4 generally includes seven full adders FA1, FA2,..., FA6, FA7. Adders FA1, FA2, FA3 of the adders FA1, FA2, ..., FA6, FA7 add the corresponding partial data P_DATA from encoder 10, although not shown, and The remaining adders FA4, FA5, FA6, FA7 add sum data SUM and carry data CARRY output from the adders FA1, FA2, FA3.

4 and 5, the operation of the compressor in the multiplier according to the present invention will be described in detail.

Referring back to FIGS. 1, 4, and 5, a multiplier using a booth algorithm generally includes an encoder 10, a compressor 30, and an adder 50, as shown in FIG. 1. The encoder 10 outputs a plurality of bits of partial data P_DATA obtained by encoding multiplier and multiplicative data Y_DATA and X_DATA from the outside. In this case, assuming that 32-bit multiplier and multiplicative data Y_DATA and X_DATA are respectively input to the encoder 10, 16-bit partial data P_DATA [0:15] will be output from the encoder 10. . However, since one bit of partial data P_DATA is additionally generated by a negative sign of operators in the calculation process in the encoder 10, 17 bits of partial data P_DATA [0:16] are generated from the encoder 10. Is output.

As such, when partial data P_DATA [0:16] of 17 bits is output from the encoder 10, the general compressor 30 additionally designs a compression circuit and compresses it. However, the addition of circuitry for compression not only increases the layout area of the multiplier, but also complicates the circuit forming the multiplier. In the multiplier according to the present invention, each of the compression units 300_1, 300_2, ..., 300_n-1, 300_n uses four-to-two compressors (COM1, COM2, COM3, COM5) and a nine-to-two compressor (C0M4). By implementing the above, the above problems are solved.

As shown in FIG. 1, assuming 32-bit multiplier data and multiplicative data Y_DATA and X_DATA are input from the outside, each compression unit 300_1, 300_2,. ... 300_n-1, 300_n include compressors COM1, COM2, COM3, COM4, COM5. The compressors COM1, COM2, and COM4 may compress the compressed data C_DATA and the carry data CARRY from the corresponding partial data P_DATA among the partial data P_DATA [0:16] from the encoder 10. Output The remaining compressors COM3 and COM5 output the compressed data C_DATA and the carry data CARRY obtained by compressing the compressed data C_DATA and the carry data CARRY from the corresponding compressor COM of the preceding stage. .

The compressed data C_DATA [0], C_DATA [1], ..., C_DATA [62], C_DATA [63] output from the compression units 300_1, 300_2, ..., 300_n-1, 300_n are shown in FIG. Like 1, it is finally added by the 64-bit adder 50 and output as the output result of the multiplier. In addition, the four-to-two compressors COM1, COM2 and COM5 of FIG. 2 are composed of six full adders FA1, FA2, ..., FA5, FA6 and the nine-to-two compressor COM4 of FIG. Is composed of seven full adders FA1, FA2, ..., FA6, FA7, the increase in layout area of the compressor of the multiplier according to the present invention is minimized. Also, in the processing speed, the compressor of the multiplier according to the present invention has the same processing speed as the compressor of the general multiplier.

As mentioned above, the compressor 300 of the multiplier according to the present invention is a four-to-two compressors (COM1, COM2, COM3, COM5) and a nine-to-two compressor for compressing a plurality of bits of partial data from the encoder 10. And a plurality of compression units 300_1, 300_2,..., 300_n-1, and 300_n including COM4. Of course, the compressors 300_1, 300_2,..., 300_n-1, 300_n compressors have a multiplier of several bits (for example, 16, 24, 32, 40, 48, 56, 64 bits, etc.) and It is determined by calculating the multiplicative data (Y_DATA, X_DATA). As such, by compressing the partial data P_DATA additionally generated during the operation of the encoder, not only the malfunction of the multiplier 300 by the operation of the additionally generated partial data P_DATA is prevented, but also the multiplier 300 Increase in the layout area is prevented.

In the above, the compressor of the multiplier according to the present invention is shown according to the above description and drawings, but this is merely an example, and various changes and modifications are possible without departing from the technical idea of the present invention.

As described above, by compressing the partial data additionally generated from the encoder, not only the malfunction of the multiplier by the operation of the additionally generated partial data is prevented, but also the increase in the layout area of the multiplier is prevented.

Claims (3)

Encoding means for outputting a plurality of bits of first partial data encoding a plurality of multiplier data and a plurality of multiplicative data and at least one bit of second partial data additionally generated by a sign thereof when the first partial data is generated; and; Compression means for outputting compressed data compressing the first and second partial data from the encoding means; Adding means for outputting addition data obtained by adding the compressed data from the compression means as a multiplication result; The compression means, Comprising a plurality of compression unit for compressing the corresponding partial data of the partial data, Each compression unit, A first group of compressors for compressing the first partial data, and And a second group of compressors for compressing corresponding partial data of the first and second partial data. The method of claim 1, A multiplier of four input two output compressors. The method of claim 1, Wherein each of the second group of compressors is a nine input two output compressor.