KR20010018359A - late-write type semiconductor memory device of minimizing power consumption - Google Patents

Abstract

PURPOSE: A late-write type semiconductor memory device which power consumption is minimized is provided to prevent unnecessary decoding operation and reading operation upon bypass reading operation. CONSTITUTION: A semiconductor memory device has a pre-decoder which is for selecting a word-line of memory cells and an output selecting circuit. The output selecting circuit outputs data to be bypassed to a data output buffer for a bypass operation beside data from the memory cell selectively. A decoding inhibiting device(50) make the word line of the memory cells corresponding to row address disable by providing a decoding inhibiting signal to a row decoder. The decoding inhibiting signal inhibits decoding operation in response to a bypass signal output from a bypass adder(5) upon bypass operation. The decoding inhibiting device(50) has a plurality of inverters(23,24) inverting the bypass signal.

Description

Late-write type semiconductor memory device of minimizing power consumption

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to late write type semiconductor memory devices such as high speed static RAM (hereinafter, referred to as SRAM).

As the processing speed of a system increases, SRAM as a cache memory capable of processing data at high speed is required. In order to meet this demand, synchronous SRAMs that perform read / write operations in synchronization with clocks have emerged. As the number of memory cells increases, more input / output pads (I / O pads) are required in the semiconductor memory device. A method of using common I / O to reduce the number of input / output pads while having more memory cells is known. have. In the case of using common I / O, an unaddressed dead cycle is shown in FIG. 2 of US Pat. No. 5,761,150 to prevent a collision between the output data and the data to be written when switching from read operation to write operation. This is a limiting factor in processing speed. Therefore, we have come to use the late write function to reduce the dead cycle.

As one of the prior arts for a synchronous type semiconductor memory device having such a late write function, a late write type having an effect of reducing the overall time required for write data and increasing the margin of write operation. SRAM is disclosed in US Pat. No. 5,717,653, which was invented by Suzuki and patented February 10, 1998. A semiconductor memory device as disclosed in the above-described patent inputs a write address input from the outside at the time of performing a late write operation to the address decoder by several cycles in the device and selects a word line and a bit line. The data input signal inputted from the outside after being delayed several cycles from the write address input is transmitted to the write driver to perform the write operation after several cycles.

As a result, the write data is written to the memory cell in the cycle after the write cycle by the late write function. In order to realize the late write function described above, a circuit for holding the write address and the write data until the next write cycle is additionally required. In the case of a late write, the last write data and address are stored in the memory cell without being written directly for the bypass read function. When the stored address is the same as the address applied in the read cycle, the data stored in the previous cycle, that is, the write cycle immediately before the output cycle, instead of the data read from the memory cell is immediately output as read data, which is called a bypass read function.

Problems of the prior art during the bypass read are as follows. In the case of the bypass read, since the data stored in the write cycle before the read cycle is valid data, the data of the memory cell does not need to be read. In this case, the decoding operation for designating the memory cell corresponding to the applied address is required. This is performed and a read operation is performed so that data of the memory cell is still read. That is, even in the bypass read, data is read from the memory cell corresponding to the address, which is compared with the write data stored in the write cycle before the read, and then the final read data is output as the output data as the data passed selectively. Therefore, there is a problem that power consumption is unnecessarily generated. Therefore, there has been a problem in that power consumption is large due to unnecessary operations during bypass read, for example, a read operation of a memory cell or an address decoding operation.

Accordingly, an object of the present invention is to provide a late write type semiconductor memory device capable of solving the above-mentioned problems.

Another object of the present invention is to provide a late write type static random access memory capable of minimizing power consumption by preventing unnecessary decoding and read operations during the bypass read operation.

According to the present invention for achieving the above object, a row decoder for selecting a word line of a memory cell; A semiconductor memory device including an output selection circuit for selectively outputting data to be bypassed to a data output buffer for a bypass operation in addition to the data from the memory cell, the semiconductor memory device comprising: a bypass signal output from a bypass summer in a bypass operation; And providing a decoding prohibition signal for inhibiting a decoding operation in response to the row decoder to deactivate the word line of the memory cells corresponding to the row address.

Preferably, the decoding prohibition unit may include inverters that invert the bypass signal of the bypass summer and provide the current sink node of the row decoder, wherein the row decoder is divided into a main low decoder and a section low decoder. It may be a section low decoder.

According to the above configuration, unnecessary operations during the bypass operation, for example, an address decoding operation for selecting a memory cell and a read operation for sensing and amplifying data from the memory cell are not performed, thereby minimizing power consumption.

1 is a schematic block diagram of a conventional semiconductor memory device to which the present invention can be applied.

2 and 3 are circuit diagrams showing a decoding prohibition unit and a connection thereof according to embodiments of the present invention; and

4 is a detailed circuit diagram of the section low decoder in FIGS. 2 and 3;

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that in the drawings, the same or similar parts to each other are described with the same or similar reference numerals for convenience of description and understanding.

First, a detailed description of the problem of high power consumption in bypass operation of a conventional semiconductor memory device will be described in detail before the description of the present invention without any intention other than to provide a more thorough understanding of the present invention.

Fig. 1 schematically shows the structure of the bypass lead scheme in a conventional late write type semiconductor memory. Referring to the figure, the external address is stored in the address buffer 1 until the next address is applied in synchronization with the clock XSA, and the write address is stored in the write address register 2 after one cycle at the time of writing. At the time of reading, the address of the address buffer 1 is applied, and at the time of writing, the address of the write address register 2 is applied to the decoder 13 through the multiplexer 3. The last write address is still stored in the write address register 2 during the transition from the write operation to the read operation. In order to realize the bypass read function during the read operation, the address of the address buffer 1 is compared with the address previously stored in the write address register 2 to check whether it is the same. Specifically, the corresponding address bits are compared with the exclusive OR gate 4 and the result is generated as the signals CA1, CA2, ..., CAn and provided to the bypass summer 5. The bypass summer 5 normally generates a bypass signal BYP for the bypass read operation as the logic level " high " when the addresses are the same. The bypass signal BYP is provided to the data clock generator 6 and the data clock generator 6 generates a bypass control signal KBYP in response. The write data stored in the data input buffer 10 is applied to the data output buffer 9 through the multiplexer 8 by generating the bypass control signal KBYP. Bypass data applied to the data output buffer 9 is finally output to the outside of the chip by the off-chip driver 11. On the other hand, when the addresses are not the same, the data clock generator 6 generates the pipe control signal KPIPE accordingly. The word line of the memory cell array 12 is selected by the decoder 13 so that the cell data is read from the selected memory cell and the data DLAT / DLATB sensed and amplified by the main sense amplifier 14 is transmitted through the multiplexer 7. It is applied to the output buffer 9. The normal read data applied to the data output buffer 9 is finally output to the outside of the chip by the off-chip driver 11.

In the above-described structure of FIG. 1 and the operation thereof, even when the bypass signal BYP is generated in the bypass summer 5 because the addresses of all bits coincide in the exclusive OR gate 4, the externally applied address is applied. Is decoded by the decoder 13 through the multiplexer 3 and the memory cells are selected to be amplified in the sense amplifier 14 and reach the multiplexer. Since it is a bypass lead, no KPIPE signal is generated, and DIN-BYP of the multiplexer 8 is provided to the data output buffer 9 by the KPIPE signal. That is, in the case of the bypass read, there is no need to perform a decoding operation for selecting a memory cell and a read operation for sensing and amplifying cell data. Therefore, in the prior art, there has been a problem in that power consumption is large due to unnecessary operations such as a read operation of a memory cell or an address decoding operation during bypass read.

Therefore, in the present invention, as shown in Figs. 2 and 3, the decoding prohibition section between the section low decoder 30 in the row decoder 13 and the bypass summer 5 for selecting the word line of the memory cell. Connect (50, 51). The decoding prohibitors 50 and 51 provide the current suppression node of the section low decoder 30 with a decoding prohibition signal for prohibiting the decoding operation in response to the bypass signal output from the bypass adder during the bypass operation. . As a result, the section word line of the memory cells corresponding to the row address is disabled.

2 and 3 are circuit diagrams showing a decoding prohibition unit and a connection relationship thereof according to embodiments of the present invention, and FIG. 4 is a detailed circuit diagram of the section low decoder 30 in FIGS. 2 and 3. The circuit structure of FIG. 4 generates section wordline signals SWLij0-n in response to the main wordline signal MWL and the decoding row address DRAij0-n, and is well known in the art, and thus, further description thereof will be omitted.

In FIG. 2, the decoding prohibition unit 50 includes an inverter 20 for inverting the bypass signal of the bypass summer and a current of the section low decoder 30 in response to an output of the inverter 20. An isolation transistor 21 for operatively separating the current sink node NO1 from the ground node. Therefore, when the bypass signal BYP is provided as " high " during the bypass read operation, the output of the inverter 20 becomes low, and the isolation transistor 21 is turned off. As a result, the current sink node NO1 of the section low decoder 30 having the structure as shown in FIG. 4 is operably separated from the ground node, so that the word line decoding operation is blocked at the source, and thus, in the row direction. The selected section wordline specifying memory cells may not be boosted. Accordingly, since the data stored in the memory cell is not developed in the bit line pair, the operation of the sense amplifier is the same as that of the disable, thereby minimizing the current consumption. On the other hand, when the bypass read operation is not performed, the output of the inverter 20 becomes high, and the isolation transistor 21 is turned on. Therefore, since the current sink node NO1 of the section low decoder 30 having the structure as shown in FIG. 4 is operatively connected to the ground node, a normal word line decoding operation is performed, thereby performing row memory cells. The selected section wordline that boosts them is boosted.

Referring to FIG. 3, the decoding prohibiting unit 51 inverts the bypass signal BYP of the bypass summer 5 to directly the current sink node NO2 of the section low decoder 30. It can be seen that it is composed of the inverters (23, 24) providing. That is, the output of the inverter 24 is directly connected to the source terminal of the N-type MOS transistor N1 of FIG. Therefore, when the bypass signal BYP is provided as " high " during the bypass read operation, the output of the inverter 24 becomes high, and the transistor N1 in Fig. 4 is turned off and eventually The current sink node NO1 is operatively separated from the ground node of the inverter 24 so that the decoding operation is blocked.

Therefore, a decoding operation for selecting unnecessary memory cells and a read operation for sensing and amplifying cell data are prevented during bypass read, thereby preventing unnecessary current flow, thereby saving power.

According to the present invention as described above, it has the effect of reducing the power consumption by minimizing unnecessary operation during the bypass operation. Therefore, there is an advantage that the performance is improved in the entire system employing the semiconductor memory device.

Claims (4)

A row decoder for selecting a word line of a memory cell; A semiconductor memory device comprising: an output selection circuit for selectively outputting data to be bypassed to a data output buffer for bypass operation in addition to data from the memory cell; Decoding such that word lines of memory cells corresponding to a row address are disabled by providing the row decoder with a decoding prohibition signal for inhibiting a decoding operation in response to a bypass signal output from the bypass summer in the bypass operation. A late write type semiconductor memory device comprising a prohibition portion. The late write type semiconductor of claim 1, wherein the decoding prohibiting unit comprises inverters which invert the bypass signal of the bypass summer and provide the inverter to a current sink node of a section low decoder in the row decoder. Memory device. The inverter of claim 1, wherein the decoding prohibiting unit operates an inverter for inverting the bypass signal of the bypass summer, and a current sink node of a section low decoder in the row decoder from a ground node in response to an output of the inverter. A late write type semiconductor memory device, characterized in that consisting of isolation transistors for isolation. Address input buffer; Data input buffer; A write address storage unit for outputting a write address from the address input buffer by a predetermined cycle when writing after a predetermined cycle; A plurality of comparison units for comparing a read address of the address input buffer with a write address delayed by a predetermined cycle of the write address storage unit and generating a coincidence signal when they are the same; A multiplexer for selectively outputting the read address or the delayed write address in response to a write control signal; A memory cell array having a plurality of memory cells connected to intersections of rows and columns; A row decoder for selecting a word line of memory cells corresponding to the selection address output through the multiplexer; A sense amplifier for sensing and amplifying data stored in the memory cell; A write driver for transferring write data to be written to a selected memory cell; A bypass adder for generating a bypass signal for determining whether a bypass operation is performed by summing the coincidence signals of the comparators; The word line of the memory cells corresponding to the row address is provided by providing a decoding inhibit signal to the current sink terminal of the row decoder to inhibit the operation of the row decoder only when the bypass signal is output from the bypass summer. A decoding prohibition unit for disabling; A data clock generator for generating a control clock for determining a bypass operation or a normal operation according to the output state of the bypass summer; An output selector for selectively outputting data obtained from the memory cell or data of the data input buffer according to a control clock of the data clock generator; And And a data output buffer configured to latch output data provided from the output selector to an off-chip driver.