KR20010018357A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a defect of a cell capacitor and to improve an operating characteristic of a memory cell, by easily guaranteeing overlap margin of a buried contact hole and a bar pattern of a storage electrode while using a conventional photolithography process, and by increasing misalign margin of the buried contact hole and the bar pattern. CONSTITUTION: An interlayer dielectric(60) is formed on a silicon substrate(10). An etch mask layer pattern where an etching groove is incline-etched in a desired portion of the interlayer dielectric, is formed on the interlayer dielectric. The exposed interlayer dielectric in the etching groove is etched to form a buried contact hole(63) for exposing a portion of the silicon substrate for a buried contact by using the etch mask layer. A bar pattern of a storage electrode electrically connected to the portion for the buried contact and overlapping the buried contact hole, is selectively formed on the interlayer dielectric.

Description

Method for manufacturing semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to increase the margin of mismatch between the buried contact hole and the bar pattern of the storage electrode to prevent the failure of the cell capacitor.

In general, an increase in the cell capacitance of a DRAM improves the readability of the memory cell and decreases the soft error rate, thus greatly contributing to improving the memory characteristics of the cell. As the density of memory cells increases, the area occupied by unit cells in one chip decreases, which leads to a reduction in the area of the cell capacitor. Therefore, it is necessary to increase the capacitance of the cell capacitor along with increasing the integration of the unit cell.

Recently, many studies have been continuously introduced to increase cell capacitance, most of which are related to the structure of the storage electrode constituting the cell capacitor, such as Fujitsu's pin structure electrode, Toshiba's box ( Box structure electrodes, cylindrical structure electrodes of Mitsubishi Corp., and the like are mainstream. Attempts to increase the capacitance of cell capacitors by improving the structure of the storage electrodes have been criticized for their manufacturability due to problems such as limitations of design rules and increased error rates due to complex processes. Thus, there has been a growing need for a new cell capacitor manufacturing method that overcomes these problems.

Meanwhile, a COB (capacitor over bitline) cell having a cell capacitor formed on a bit line has been introduced to prevent bad contact of a bit line as a structure suitable for a 64M DRAM cell or a 256M DRAM cell.

However, in the conventional COB structure cell capacitor, when the bar pattern of the storage electrode is formed on the interlayer insulating layer by a photolithography process, the bar is not formed in the contact hole due to the lack of overlap margin with the mem contact hole of the interlayer insulating layer. Poor phenomena where the pattern mismatches exceed the mismatch allowable margin are likely to occur frequently. As a result, in the selective etching of the polysilicon for forming the bar pattern, some of the polysilicon layers in the buried contact hole are etched, which causes a failure of the cell capacitor and further deteriorates the operation characteristics of the memory cell.

However, at present, it is difficult to increase the size of the bar pattern in order to increase the overlap margin with the buried contact hole because the gap between the bar patterns of the highly integrated semiconductor chip is no longer difficult. Therefore, development has been made in the direction of reducing the width of the buried contact hole, but the current photolithography process has reached its limit.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which misalignment between a buried contact hole and a bar pattern of a storage electrode is allowed to be prevented, thereby preventing a defect of a cell capacitor.

1 is a layout showing the structure of a DRAM (DRAM) applied to the method of manufacturing a semiconductor device according to the present invention.

2 is a cross-sectional view taken along the line A-A of FIG.

3 is a cross-sectional view taken along the line B-B of FIG.

4 to 9 is a process chart showing a semiconductor device manufacturing method according to the present invention.

The semiconductor device manufacturing method according to the present invention for achieving the above object is

Forming an interlayer insulating film on the silicon substrate which has been subjected to a predetermined process;

Forming a pattern of an etch mask layer on the interlayer insulating layer, wherein the etch mask layer is disposed on the desired portion of the interlayer insulating layer;

Etching the exposed interlayer dielectric layer in the etch groove using the etch mask layer to form a etch contact hole for exposing a portion to be immersed in the silicon substrate; And

And selectively forming a bar pattern of a storage electrode electrically connected to the portion to be contacted with the buried contact and overlapping the buried contact hole on the interlayer insulating layer.

Preferably, the etching mask layer is formed of a polysilicon layer that is the same as the bar pattern of the storage electrode. In addition, a lower portion of the bar pattern of the storage electrode is formed as the etching mask layer.

Accordingly, the present invention can reduce the width of the upper portion of the contact hole by more than the CD (critical dimension) of the conventional photolithography process to enlarge the overlap margin of the bar pattern of the contact hole and the storage electrode and further increase the margin of mismatch. have.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram of a DRAM applied to a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. For convenience of description, the description will be made with reference to FIGS. 1 to 3.

As shown in FIG. 1, word lines W / L are wired in a longitudinal direction while passing through a channel region between a source / drain S / D of a corresponding transistor, and bit lines B / L. ) Cross the word lines (W / L) vertically with the transistors interposed therebetween, and extend in the lateral direction, and the source (S) of the transistor passes through the D / C contact hole and the corresponding bit line (B / L). Cell pads, which are electrically connected to each other, are connected by overlapping the drains (D) of each transistor, and the bar patterns of the storage electrodes defined by the double-dotted lines overlap the corresponding cell pads. Electrically connected via

As shown in FIG. 2, an isolation layer 11 for isolating the active region is formed in the field region of the silicon substrate 10, and the gate oxide film is formed on the channel region between the source / drain (S / D) of the transistor. 13, a gate electrode 20 corresponding to a word line W / L is formed on a portion of the gate oxide film 13 and the isolation layer 11, and an insulating film is formed on the gate electrode 20. 30 is formed, spacers 40 of insulating films are formed on both side walls of the gate electrode 20, and the cell pad 50 is formed between neighboring gate electrodes 20 so as to be connected to the drain D. The bar pattern 80 of the storage electrode overlaps the cell pad 50 with the interlayer insulating layer 60 therebetween.

Here, the gate electrode 20 may be formed of a lower barrier metal layer 21 and a high melting point metal layer 23 in order to reduce the resistance of the word line. The insulating film 30 may be formed of a lower nitride film 31 and an upper high temperature oxide film 33.

As shown in FIG. 3, the isolation layer 11 is formed in the field region of the silicon substrate 10 with the drain D of each transistor interposed therebetween, and the cell pad 50 overlaps the drain D. And the bit line 70 is positioned in the interlayer insulating film 60 higher than the cell pad 50 between the adjacent cell pads 50, and the bar pattern 80 of the storage electrode is inclined of the interlayer insulating film 60. The cell pattern 50 is electrically connected to the cell pad 50 by the same material as the bar pattern 80 filled in the etched contact hole 63. The width W1 of the upper portion of the mold contact hole 63 is wider than the width W2 of the lower portion, and the width W3 of the bar pattern 80 is wider than the width W1 of the upper portion of the mold contact hole 63. The bit line 70 may be formed of a lower barrier metal layer 71 and an upper tungsten layer 73.

A method of manufacturing a semiconductor device configured as described above will be described with reference to FIGS. 4 to 9. The same code | symbol is attached | subjected to the part same as the part of FIG. 2 and FIG.

Referring to FIG. 4, first, as shown in FIG. 2, the isolation layer 11 is formed in a field region of the silicon substrate 10 by, for example, a shallow trench isolation (STI) process. Thereafter, the gate oxide film 11 is grown on the active region of the silicon substrate 10 by a thermal oxidation process, and the polysilicon layer 21 is laminated on the entire surface of the silicon substrate 10 including the gate oxide film 11. And a silicide layer, for example, a tungsten silicide layer 23, is formed thereon. Then, an insulating film 40 made of, for example, a lower nitride film 41 and an upper high temperature oxide film 43 is stacked on the tungsten silicide layer 23. Subsequently, the insulating layer 40 is left only in a portion corresponding to the word line of FIG. 1 by a photolithography process, and the insulating layer 40 in the remaining portion is removed until the tungsten silicide layer 23 is exposed. Next, using the remaining pattern of the insulating film 40 as a mask, the exposed silicide layer 23 and the polysilicon layer 21 are etched until the gate oxide film 13 below is exposed to the word line ( 20).

After the formation of the word line 20 is completed, a pattern of a photoresist film (not shown) having an opening exposing an active region of each transistor is formed on the resultant structure, and the photoresist film and the word line 20 are used as a mask. Thus, a lightly doped drain (LDD) region is formed by implanting impurities of a desired conductivity type into the active region of each transistor at low concentration. Then, a thick insulating film for the spacer 40 is stacked on the front surface of the silicon substrate 10 and etched back until the active region is exposed to form spacers 40 on both sidewalls of the word line 20. Thereafter, a pattern of a photoresist film (not shown) having an opening that exposes the active region of each transistor is formed on the resultant structure, and the photoresist, the word line 20 and the spacer 40 are used as a mask to form a desired pattern in the active region. A high concentration of ions are implanted to form a source / drain (S / D).

After the formation of the source / drain (S / D) is completed, a polysilicon layer is deposited on the resultant structure to a thickness for the cell pad 50, which is then defined by the advantaged line of FIG. 1 by a photolithography process. The pattern of the cell pad 50 is overlapped on the corresponding drain D by leaving the polysilicon layer and removing the remaining polysilicon layer.

After formation of the cell pad 50 is completed, a first interlayer insulating film, for example, a BPSG film, is thickly deposited on the resultant structure to sufficiently fill the void space between the cell pads 50 and to planarize the surface, and then mechanically It is planarized by a chemical mechanical polishing process. Subsequently, a contact hole is formed in the interlayer insulating layer 60 of the contact hole of FIG. 1 for electrical connection between the source and the bit line by using a photolithography process, and then a bit line is formed on the interlayer insulating layer 60 including the contact hole. A barrier metal layer 71 of Ti / TiN material and a high melting point metal, for example, a tungsten layer 73 are sequentially stacked. Thereafter, the tungsten layer 73 and the barrier metal layer 71 of the portion for the bit line of FIG. 1 are left by using a photolithography process, and the tungsten layer 73 and the barrier metal layer 71 of the remaining portion are removed to remove the bit line ( 70) is formed. Thus, the bit line 70 and the source S are electrically connected.

After the formation of the bit line 70 is completed, a thick layer of the first interlayer insulating film and the same second interlayer insulating film is thickly stacked on the resultant structure for surface planarization, and the surface is planarized by an etch back process to form a first interlayer insulating film. An interlayer insulating film 60 made of a second interlayer insulating film is formed. The thickness T1 of the interlayer insulating film 60 is preferably determined in consideration of the lower width W2 of the buried contact hole 63 to be formed in a subsequent process.

Referring to FIG. 5, after the formation of the interlayer insulating film 60 is completed, the polysilicon layer 81 to serve as an etch mask of the interlayer insulating film 60 in a subsequent inclined etching process on the interlayer insulating film 60. Laminated. Here, the thickness of the polysilicon layer 81 is lower than the width W2 of the polysilicon layer 81 to be formed in the subsequent inclined etching process in order to increase the ease of forming the buried contact hole 63 and mismatch allowance margin of FIG. 7. ), It is preferable to determine a thickness of 500 to 4000 kPa. The polysilicon layer 81 is the same as the material of the bar pattern 80 of the storage electrode to be formed, which is shown in FIG.

Subsequently, a pattern of the photosensitive film 75 having an opening 76 for exposing a portion to be contacted, for example, a portion of the upper surface of the cell pad 50, is formed on the interlayer insulating film 60. Typically, the width W of the opening 76 is determined to be the smallest dimension that can be formed in the photographic process.

Referring to FIG. 6, by using the pattern of the photosensitive film 75 as an etching mask, the exposed polysilicon layer 81 in the opening 76 is inclinedly etched until the interlayer insulating film 60 is exposed. An etching groove 82 is formed. Here, the upper width of the etching groove 82 corresponds to the width W of the opening of the photosensitive film 75, and the lower width W1 of the etching groove 82 is smaller than the width W. This serves to reduce the width of the upper portion of the buried contact hole 63 of FIG. 7 to be formed in a subsequent process to a width W1 that is greater than or equal to the limit of the photolithography process.

Referring to FIG. 7, after the inclined etching of the polysilicon layer 81 is completed, the remaining pattern of the photosensitive film 75 of FIG. 6 is removed. Thereafter, using the polysilicon layer 81 as an etching mask, the exposed interlayer insulating layer 60 in the etching groove 82 is inclinedly etched until a portion of the cell pad 50 is exposed to form the etch contact hole 63. Form. The lower width W2 of the buried contact hole 63 is smaller than the upper width W1.

Of course, a portion of the silicon substrate 10 itself as a portion to be etched contact may be exposed by a etch contact hole (not shown) of the interlayer insulating film 60.

Referring to FIG. 8, the polysilicon layer 81 may be completely filled in the contact hole 63 for electrical contact with the cell pad 50, and may be formed to a thickness necessary for forming the bar pattern 80 of the storage electrode. A polysilicon layer 83 of the same quality is laminated on the interlayer insulating film 60.

Referring to FIG. 9, a pattern of the photosensitive film 77 for overlapping the buried contact hole 63 is then formed on the polysilicon layer 83 in the region defined by the dashed-dotted line shown in FIG. 1 and formed into an etching mask. The exposed portion of the polysilicon layer 83 is etched until the interlayer dielectric layer 60 is exposed to form the bar pattern 80 of the storage electrode. In this case, the polysilicon layer 81 forms a lower portion of the bar pattern 80 of the storage electrode.

Finally, the pattern of the photoresist layer 77 is removed to complete the bar pattern 80 of the storage electrode as shown in FIG. 3.

Therefore, the upper width W1 of the buried contact hole 63 is reduced to less than or equal to the CD that can be formed in the current photolithography process, thereby securing a margin for overlapping the bar pattern 80 in the buried contact hole 63. Is easy. This makes it possible to secure a margin of mismatch between the buried contact hole and the bar pattern while using the existing photolithography process as it is.

As described above, according to the present invention, a pattern of a polysilicon layer in which an interlayer insulating layer is stacked on a silicon substrate on which a bit line is formed and an inclined etched groove is positioned in a portion of the interlayer insulating layer in which a mem contact hole is to be formed is formed. By using this as an etch mask layer, the exposed interlayer insulating film in the etch groove is etched to form a etch contact hole in which the width of the upper portion is reduced to more than the CD (critical dimension) of the current photolithography process. Thereafter, the silicon contact hole may be filled, and a polysilicon layer is stacked to a thickness required for the bar pattern of the storage electrode, and then selectively etched to form a bar pattern of the storage electrode overlapped with the memory contact hole.

Therefore, the present invention can easily secure the overlap margin between the buried contact hole and the bar pattern of the storage electrode while using the conventional photolithography process as it is, and further increase the margin of mismatch between the buried contact hole and the bar pattern. have. As a result, defects of the cell capacitors can be prevented and further, operating characteristics of the memory cells can be improved.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

Forming an interlayer insulating film on the silicon substrate which has been subjected to a predetermined process; Forming a pattern of an etch mask layer on the interlayer insulating layer, wherein the etch mask layer is disposed on the desired portion of the interlayer insulating layer; Etching the exposed interlayer dielectric layer in the etch groove using the etch mask layer to form a etch contact hole for exposing a portion to be immersed in the silicon substrate; And And selectively forming a bar pattern of a storage electrode electrically connected to the portion to be contacted with the buried contact hole on the interlayer insulating layer. The method of claim 1, wherein the etching mask layer is formed of a polysilicon layer that is the same as the bar pattern of the storage electrode. The method of claim 2, wherein the lower portion of the bar pattern of the storage electrode is formed as the etching mask layer.