KR20010018009A - Asymmetric digital subscriber line system using Qswitch - Google Patents

Abstract

PURPOSE: An ADSL(Asymmetric Digital Subscriber Line) using a Q switch is provided to automatically achieve signal conversion between a configuration block using a power of 3 volts and a configuration block using a power of 5 volts in an ADSL interface unit, without the necessity of any additional conversion logic for power control. CONSTITUTION: A cell interface unit(31) receives down ATM cell data outputted from a network interface unit(21) through a cell bus and outputs the input up ATM cell data to the network interface unit(21) through the cell bus. An ATM cell MUX/DEMUX(32) demultiplexes the down ATM cell data received through the cell interface unit(31) and multiplexes the input up ATM cell data. A cell delineation unit(33) receives the down ATM cell data demultiplexed in the ATM cell MUX/DEMUX(32) and disassembles the input ADSL frame into up ATM cell data. A framer/interface unit(34) configures the down ATM cell data received at the cell delineation unit(33) into an ADSL frame and executes interfacing with an external system. A DMT(Discrete Multi Tone) processor(35) executes DMT modulation for the ADSL frame configured in the framer/interface unit(34) and DMT demodulation for an input digital ADSL signal. An analog front end(36) converts the DMT modulated digital ADSL signal into an analog signal and converts an inputted analog ADSL into a digital ADSL signal. A line driver/receiver(37) converts 4 wires for the analog ADSL signal converted at the analog front end(36) into 2 wires and converts 2 wires for an inputted analog ADSL signal into 4 wires. A hybrid transformer(38) executes impedance matching for the analog ADSL signal outputted through the line driver/receiver(37) and outputs it to a splitter(12). The hybrid transformer(38) receives an analog ADSL signal inputted through the splitter(12) after impedance matching. A CPU(39) controls the operation of the cell interface unit(31), the ATM cell MUX/DEMUX(32) and the cell delineation unit(33). An A/D chipset interface/DSP(40) executes an exchange function for control information, status information and initialization to the CPU(39) and an MP(Message Protocol). A Q switch(41) converts control signals, clock signals, reset signals and 16-bit TDMA data necessary between the CPU(39), the framer/interface unit(34), the DMT processor(35), the analog front end(36) and the A/D chipset interface/DSP(40), without the necessity of controlling power additionally.

Description

Asymmetric digital subscriber line system using Qswitch

The present invention provides a 5 V power supply in an ADSL interface unit by providing a Qswitch in an ADSL interface unit in a DSLAM (Digital Subscriber Line Access Multiplexer) system of an asymmetric digital subscriber line (ADSL) system. The present invention relates to an ADSL system using a cue switch that enables signal conversion to be automatically performed without separate power control between a component block used and a component block using a 3V power supply.

In general, ADSL system provides not only telephone service but also interactive service such as Video Of Demand (VOD) service, data service, high speed internet service, etc. by using existing telephone line. As a system capable of doing this, as shown in FIG. 1, a VOD server 1 for providing a VOD service, an Internet server 2 for providing an Internet service, the VOD server 1 and an Internet server ( ATM switch 3 for ATM cell processing and switching of service data and control signals provided by 2), and the ATM cell processed data and control signals at the ATM switch 3 are modulated into digital ADSL signals and then converted into analog signals. After converting, multiplexing with Plain Old Telephone Service (POTS) call signal output from telephone exchanger 13 and transmitting through existing telephone line (Central Office; hereinafter referred to as 'CO') 4), a splitter 5 for receiving an analog signal of the CO 4 transmitted through a telephone line and separating the digital signal into a digital ADSL signal and a POTS call signal, and a splitter 5 separated from the splitter 5. And an ADSL subscriber unit 6 which demodulates the digital ADSL signal into original service data and control signals and outputs it to a PC.

The CO 4 of the ADSL system configured as described above includes a DSLAM 11 for modulating data and control signals output from the ATM switch 3 into a digital ADSL signal and converting the data into an analog signal, and the DSLAM 11. It consists of a splitter 12 for multiplexing the analog ADSL signal and the POTS call signal output from the telephone exchanger 13 and transmitting it through a telephone line, and an NMS (Network Management System) 14 for efficiently managing a network. In this case, the DSLAM 11 is a network interface unit 21 for matching with the ATM switch 3, a control and management unit 22 for controlling and managing the overall operation of the DSLAM 11, and the control and management unit Under the control of 22, the ADSL interface unit 23 converts the ATM cell data output from the network interface unit 21 into a digital ADSL signal and converts the same into an analog signal.

The ADSL system configured as described above is configured to use a 3V power supply and a building block using a 5V power supply in the ADSL interface unit 23 to satisfy the requirements of high-speed and low power. The block is used together to implement the system configuration.

Accordingly, in the related art, a diode is connected to the VCC stage for signal conversion between a component block using a 5V power supply and a component block using a 3V power supply, and an RC delay circuit, a load capacitance, a passive element, and the like. By using a proper value to configure a conversion logic (Conversion Logic) for a separate power control, this configured conversion logic to be provided in the ADSL interface (23).

However, it is not easy to implement such a conventional conversion logic, it is difficult to design a new type of configuration block using a 3V power supply for low power, as well as a power loss (Damage) and Propagation delay occurs, and it is difficult to solve a heating problem, which is a main problem of the ADSL interface unit 23.

At this time, the heating of the ADSL interface unit 23 itself causes a problem that may cause anxiety of the system and become a major cause of failing to obtain satisfactory ADSL performance from the ADSL interface unit 23.

In addition, there is a disadvantage in that it takes a high cost when ASIC is designed to design a new type of building block.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to provide a cue switch in the ADSL interface in the DSLAM of the ADSL system, and to use a 5V power supply in the ADSL interface and a configuration block using the 3V power supply. It is to provide an ADSL system using a cue switch that enables signal conversion to be automatically performed without satisfying conversion logic for separate power supply control to satisfy high-speed and low power requirements.

1 is a block diagram of a typical asymmetric digital subscriber line system;

2 is a block diagram illustrating an asymmetric digital subscriber line interface unit using a cue switch according to the present invention.

<Explanation of symbols for main parts of drawing>

31: cell bus interface unit 32: ATM cell mux / demux

33: Cell Deletion Unit 34: Framer / Interface Unit

35: DMT Processor 36: Analog Front End

37: line driver / receiver 38: hybrid converter

39: CPU 40: A / D chipset interface / DSP

41: Cue switch

ADSL system using the cue switch of the present invention for achieving this object, the CPU using a 5V power supply and the framer / interface unit using a 3V power supply, a DMT processor, an analog front end using the ADSL interface in the ADSL system After the A / D chipset interface / DSP is installed, the control signal, clock signal, reset signal, and 16-bit TDMA data of each component block are automatically connected through this cue switch without additional power control, thereby providing 5V power supply. It is characterized in that the signal conversion is automatically performed between the configuration block using the and the configuration block using the 3V power supply.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the ADSL system using a cue switch according to the present invention.

FIG. 2 is a block diagram of an ADSL interface unit 23 using a cue switch according to the present invention. The downlink ATM cell data output from the network interface unit 21 is received through a cell bus and inputted. Demultiplexes the cell bus interface unit 31 for outputting upstream ATM cell data to the network interface unit 21 through a cell bus and the downlink ATM cell data received through the cell bus interface unit 31; Multiplexed ATM cell mux / demux 32 and multiplexed upstream ATM cell data to the cell bus interface unit 31 and demultiplexed in the ATM cell mux / demux 32, respectively. A cell delineation unit 33 for receiving the downlink ATM cell data of the cell, decomposing the input ADSL frame into the upstream ATM cell data, and outputting the same to the ATM cell mux / demux 32; Each down ATM received at the nation unit 33 A framer / interface section 34 configured to configure cell data in an ADSL frame, an input ADSL signal in an ADSL frame, and interface with an external system, and an ADSL frame configured in the framer / interface section 34. The DMT processor 35 performs a DMT (Discrete Multi Tone) modulation, DMT demodulates the input digital ADSL signal, and converts the DMT modulated digital ADSL signal into an analog signal by the DMT processor 35, and inputs the analog signal. An analog front end (36) for converting a digital ADSL signal into a four-wire (2) wire for the analog ADSL signal converted from the analog front end (36) to two wires, and an analog input A line driver / receiver 37 for converting two wires to an ADSL signal into four wires, and an analog output through the line driver / receiver 37. Hybrid transformer 38 for impedance matching the ADSL signal and outputting the split signal to the splitter 12, and receiving and matching the analog ADSL signal input through the splitter 12, and the cell bus interface unit 31. ), A CPU 39 for controlling the operation of the ATM cell mux / demux 32, the cell delivery unit 33, the framer / interface unit 34, the DMT processor 35, and an analog front end 35 A / D chipset interface unit / DSP (Digital Signal Processor) that controls the operation of the CPU 39 and performs control functions, status information, and initialization with the CPU 39 and the message protocol (MP). 40, a control signal, a clock signal, required between the CPU 39 and the framer / interface unit 34, the DMT processor 35, the analog front end 35, and the A / D chipset interface unit / DSP 40; Queue switch for converting reset signal and 16-bit TDMA data without power control It is composed of 41.

That is, the CPU 39 is a component block using 5V power, and the framer / interface unit 34, the DMT processor 35, the analog front end 35, and the A / D chipset interface unit / DSP 40 Is a component block using a 3V power source, and the signal switch is automatically performed without a separate power control between the component block using a 5V power source and the component block using a 3V power source using the cue switch 41. .

Referring to the operation of the ADSL interface unit 23 configured as described above, when transmitting the downlink ATM cell data, the cell bus interface unit 31 receives the downlink ATM cell data of the network interface unit 21 through the cell bus. After demultiplexing the downlink ATM cell data in the ATM cell mux / demux 32, each downlink ATM cell data is received through the cell delivery unit 33.

Then, the framer / interface unit 34 configures the downlink ATM cell data of the cell delivery unit 33 into an ADSL frame, and then DMT modulates the data through the DMT processor 35, followed by the analog front end 36. After converting the DMT-modulated digital ADSL signal into an analog signal, the 4-wire for the analog ADSL signal is converted into 2 wires through a line driver / receiver 37, and then the line driver / The analog ADSL signal output through the receiver 37 is matched to output to the splitter 12.

On the contrary, when transmitting the uplink ATM cell data, when the hybrid converter 38 receives the impedance matched analog ADSL signal input through the splitter 12, the line driver / receiver 37 receives two signals corresponding to the analog ADSL signal. After converting the wire into four wires, the analog signal is converted into a digital ADSL signal through an analog front end 36.

Subsequently, after the DMT demodulates the converted digital ADSL signal in the DMT processor 35, a framer / interface unit 34 configures the DMT demodulated ADSL signal into an ADSL frame, and then the cell dilation unit 33 continues. Decomposes the ADSL frame into upstream ATM cell data, and then multiplexes the upstream ATM cell data through an ATM cell mux / demux 32, and then the multiplexed uplink ATM cell data in a cell bus interface unit 31. To the network interface unit 21 via the cell bus.

At this time, the CPU 39 controls operations of the cell bus interface unit 31, the ATM cell mux / demux 32, and the cell delivery unit 33, and controls the A / D chipset interface unit / DSP ( 40 controls the operation of the framer / interface unit 34, the DMT processor 35, and the analog front end 35, and exchanges control information, status information, and initialization functions with the CPU 39 and the MP. Perform.

The cue switch 41 is necessary between the CPU 39 and the framer / interface unit 34, the DMT processor 35, the analog front end 35, and the A / D chipset interface unit / DSP 40. Control signals, clock signals, reset signals, and 16-bit TDMA data are converted without additional power control.

The A / D chipset interface unit / DSP 40 interfaces with the CPU 39 through an internal data memory access (IDMA) port, and includes a framer / interface unit 34, a DMT processor 35, and an analog front end ( It controls all the functions of 36) and collects and interfaces overall information on booting, initialization, MP execution and error status information.

The cue switch 41 is a read signal, a write signal, an IDMA port selection signal, an address latch signal, an address signal, an interrupt signal, a clock signal, a reset signal, input and output from the CPU 39 using a 5V power supply, 16-bit TDMA data interfaces to framer / interface section 34, DMT processor 35, analog front end 35, A / D chipset interface section / DSP 40 using 3V power supply without any separate power control Input / output to the framer / interface unit 34, the DMT processor 35, the analog front end 35, and the A / D chipset interface unit / DSP 40, and conversely, the framer / interface unit 34 and the DMT processor ( 35), analog front end 35, A / D chipset interface / DSP 40 read signal, write signal, IDMA port selection signal, address latch signal, address signal, interrupt signal, clock signal, reset signal, 16 Bit TDMA data as it is inter It is paced to input / output to the CPU 39 using the 5V power supply.

As described above, signal conversion is automatically performed without using a cue switch 41 to prevent a power loss that can be given to a component block using 3V power.

As described above, according to the present invention, by providing a cue switch in the ADSL interface unit, it is possible to freely convert control signals and clock signals necessary between a component block using a 5V power supply and a component block using a 3V power supply. It reduces power dissipation and propagation delays for power-using building blocks and eliminates the need for separate circuit design and chip development, resulting in significant functional and economic benefits.

Claims (1)

VOD server 1, Internet server 2, ATM switch 3, DSLAM 11, splitter 12, telephone exchanger 13, CO (4) consisting of NMS 14, splitter In the ADSL system which consists of (5) and ADSL subscriber part 6, The ADSL interface unit 23 in the DSLAM 11 receives downlink ATM cell data output from the network interface unit 21 through a cell bus, and inputs upstream ATM cell data through the cell bus. The cell bus interface unit 31 outputted to the cell 21 and the downlink ATM cell data received through the cell bus interface unit 31 are demultiplexed, and the input uplink ATM cell data is multiplexed to multiplex the cell bus interface unit. ATM cell mux / demux 32 outputting to 31 and each of the downlink ATM cell data demultiplexed by the ATM cell mux / demux 32 are received, and the input ADSL frame is respectively an uplink ATM cell. A cell demultiplexer 33 for decomposing the data into the ATM cell mux / demux 32 and outputting downlink ATM cell data received by the cell demultiplexer 33 into an ADSL frame, Input ADSL signal to ADSL frame A DMT processor 35 configured to DMT-modulate an ADSL frame configured in the framer / interface unit 34 and the framer / interface unit 34 and DMT demodulate the input digital ADSL signal. And an analog front end 36 for converting the DMT modulated digital ADSL signal into an analog signal and converting the input analog signal into a digital ADSL signal, and converting the analog front end 36 in the DMT processor 35. A line driver / receiver 37 for converting 4 wires for the analog ADSL signal to 2 wires and 2 wires for the input analog ADSL signal for 4 wires, and an output through the line driver / receiver 37 The analog ADSL signal is output to the splitter 12 by impedance matching, and the analog ADSL signal input through the splitter 12 is impedance-matched. CPU 39 for controlling operations of the hybrid converter 38, the cell bus interface unit 31, the ATM cell mux / demux 32, and the cell deliberate unit 33, and the framer / An A / D chipset that controls the operation of the interface unit 34, the DMT processor 35, and the analog front end 35, and performs control functions, status information, and initialization with the CPU 39 and the MP. Control required between the interface unit / DSP 40, the CPU 39 and the framer / interface unit 34, the DMT processor 35, the analog front end 35, and the A / D chipset interface unit / DSP 40 An asymmetric digital subscriber line system using a cue switch, comprising: a cue switch 41 for converting a signal, a clock signal, a reset signal, and 16-bit TDMA data without additional power control.