KR100230833B1 - The modem time slot allocation circuit in large scale communication processing system of telephone network adaptation apparatus - Google Patents

Abstract

The present invention relates to a time slot assignment circuit for allocating timeslots to a plurality of modems located in subscriber modem connections of a telephone network matching device.

These timeslot allocation circuits include bidirectional buffers 501 and 502 which transfer addresses / data transmitted through the L-bus in a specific direction according to a control signal; A first board timeslot allocator 510 for latching data of a lower byte from a bidirectional buffer to provide first to sixteenth timeslot allocation signals for the first board; The second board timeslot allocator 520 is provided to latch the data of the upper byte from the bidirectional buffer to provide the 17th to 32nd timeslot allocation signals for the second board, thereby treating one subhighway as two boards. In this case, the circuit of the present invention can be used to accurately allocate timeslots.

Description

Modem Time Slot Allocation Circuit in Telephone Network Matching Device of Mass Communication System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a telephone network matching device for a large-capacity communication processing system, and more particularly to a modem timeslot of a telephone network matching device (TNAS) for allocating timeslots to a plurality of modems located at subscriber modem access portions of the telephone matching device. It relates to an allocation circuit.

In general, a public telephone network is a communication network for transmitting voice signals to other subscribers in a network by performing circuit switching according to call requests of telephone subscribers, and a packet switching network is a communication network for transmitting digital data between computers through packet switching. Although these networks tend to be integrated with each other as the B-ISDN is promoted, they are still composed of individual networks, so the procedures for exchanging services between networks have been very complicated.

Almost all households and companies are subscribed to the public telephone network and are used most widely, but the service is mainly voice-based telephone service. However, as the information society progresses, data transmission between computers is widely required, and various information providers are on the rise and the demand for access to packet networks is rapidly increasing. Therefore, the type of service connected to the packet switching network has been increased by using the telephone line used in general homes, and for this purpose, an information communication processing system has been introduced into the connection between the public telephone network and the packet network.

In the conventional communication processing system, as the network evolves, a wide variety of networks, such as an ISDN network, a frame relay network, an ATM network, and the Internet, have been newly established. In order to connect them integrally and to further increase processing capacity, FIG. As shown, it has been improved with a large capacity communication processing system.

1 is a block diagram illustrating a general mass communication processing system, wherein the mass communication processing system 100 includes a telephone network matching device (TNAS) 110 for connecting to a public telephone network 101, an ISDN network 102, and the like. ISDN matching device (INAS: 130) for connection, packet network matching device (PNAS: 120) for connection with packet communication network 103, ATM network matching device (ANAS :) for connection with high speed (ATM) communication network 104 140), frame network matching device (FNAS: 150) for connection with frame relay network 105, internet matching device (KNAS: 160) for connection with internet 106, high speed switch for connecting each matching device with each other Module (HSSF: 170), unit system management device for network management (LOAMS: 180), etc. to connect subscribers (PC or hightel terminals) connected to public telephone networks or ISDN to information providers (IP) connected to other networks. give.

Referring to FIG. 1, a telephone network matching device (TNAS) 110 is a high speed switch module 170 for matching a trunk signal with a digital relay line (E1 or T1) of an electronic switchgear, a number system and a signaling method used in a telephone network. ) To connect subscribers connected to the public telephone network (101) to other subscribers such as the packet network (103) by performing the function of connecting the public telephone network (101), collecting statistics and delivering billing information about the user's service use It is a device that connects to the database of the information provider (IP) connected to the network. The conventional telephone network matching device is configured as shown in FIG. 2 so that one telephone network matching device can accommodate 96 channels, and one entire system can accommodate 10 telephone network matching devices to accommodate 960 channels in total. It is supposed to be.

2. Description of the Related Art A conventional telephone network matching device includes a trunk interface module (TNIF: 210), a subscriber modem connection (TDLA; 220, 221), a high data processing assembly (HDPA; 230, 231), as shown in FIG. , A text service processor assembly (TSPA) 250, and a high speed network adapter (HSNA) 241, and the trunk interface module 210 includes a digital trunk line matching board (Extended T1 trunk). Interface Assembly / Extended CEPT trunk Interface Assembly: ETIA / ECIA; 211, T1 clock Generation switch Interface / CEPT clock Generation switch Interface Assembly: TGIA / CGIA; 212, Text Signal Transition Assemply: STA; 213), Universal Signaling Transciever Assembly (USTA; 214), Telephone Network Processor Assembly (TNPA; 215), Alarm Access Control Assembly (AACA) 216) to link users connected to the telephone network of the mass communication processing system with information providers built on the packet network.

Referring to FIG. 2, the service processing unit (TSPA) 250 is duplexed into two boards, and the high speed switching interface unit HSNA 240 and 241 and the plurality of subscribers for interworking with the high speed switching fabric HSHS 170. It is responsible for controlling the modem connection unit (TDLA: 220, 221) and the data processing unit (HDPA: 230, 231). That is, the main functions of the service processing unit (TSPA) 250 provide a telephone network subscriber interface and management, data processing of subscribers and information providers, high speed switch interface (HSNA) interworking, and service control and self maintenance.

The signal of the public telephone network subscriber is designated by the trunk matching module (TNIF: 210), and is transmitted to the data processing unit (HDPA: 230, 231) at the RS-232C level through the corresponding modem of the subscriber modem connection (TDLA: 220, 221). In this case, one subscriber modem connection unit (TDLA) accommodates 16 channels, so two boards are connected to each other in order to process one subhighway (32 channels), and one board is connected to 32 channels for one data processing unit (HDPA). I can accept it. Therefore, six subscriber modem connections (TDLA) and three data processing units (HDPA) are required to process 96 channels (three subhighways).

The data processor (HDPA: 230, 231) transmits and receives data in units of 32 channels / PBA, and transmits X.3 parameters to the received data to the service processor (TSPA: 250) through the transmission and reception queues, which are determined in 132 byte units, respectively. do. The service processing unit (TSPA) 250 transmits packet related information to the high speed switch interface unit (HSNA: 240, 241), and the high speed switch interface unit (HSNA: 240, 241) transmits this data to the high speed switch module (HSSF: 170 of FIG. 1). Through the packet network matching device (PNAS: 120 of Figure 1) through.

Motorola's MC68030 / 50MHz is used as the main processor of the service processor (TSPA: 250) and Motorola's MC68360, an IPC (Inter Processor Communication) dedicated communication processor, is used for data communication with the data processor (HDPA: 230,231). Data is transmitted in an interrupt manner through 1M bytes of common memory. The data processor (HDPA: 230, 231) uses Motorola's MC68360 as the main processor and controls four slave processors. The main processor of the data processor (HDPA: 230, 231) transmits and receives data in 2 Mbps serial communication between the slave and the service processor (TSPA: 250).

In FIG. 2, the digital relay line matching board (ETIA / ECIA: 211) matches 4T1 or 3E1. When the 4T1 is matched, the “ETIA” board is used and when the 3E1 is matched, the “ECIA” board is used. The aggregation board (TGIA / CGIA: 212)) receives the reference clock to generate the system clock, handles the subhighway switching function, and the signal service board (USTA: 214) is an R2 MFC and DTMF known as a standard for inter-station relay. It handles tones and performs services related to tones. The alarm access control unit (AACA: 216) collects hardware alarms, determines a status, reports the maintenance alarm, and performs a matching function with the maintenance processor. The telephone network matching processor (TNPA: 215) communicates with the service processor (TSPA) 250 and controls each device.

In Figure 2, the telephone network matching module (TNIF: 210) provides access to the public telephone network 101 through a PCM transmission line of 1.544 Mbps T1 or 2.048 Mbps E1, collects outgoing subscriber numbers by R2 MFC signaling, and subscriber information. Is transmitted to the service processing unit (TSPA) 250. When the reception of the service processing unit TSPA 250 is confirmed, the service processing unit TSPA is connected to the information provider IP connected to the packet network matching device 120 via the high speed switch module HSSF 170. That is, the telephone network matching device 200-1 to 200-10 connects modems in response to various modems of telephone subscribers, multiplexing function of digital data, communication protocol processing function, raw charging data collection function, Handle each of the subsystem maintenance itself.

In such a telephone network matching device, 16 modems are accommodated in one subscriber modem connection, and two subscriber modem access boards handle one subhighway (32 channels), thereby efficiently allocating timeslots to multiple modems. Is needed.

Accordingly, the present invention has been made to meet the above necessity, and provides a modem timeslot allocation circuit for allocating time slots to a plurality of modems through an L-bus in a telephone network matching device of a mass communication processing system. Its purpose is to.

In order to achieve the above object, the circuit of the present invention is connected to a digital trunk of a public telephone network to transmit / receive a predetermined number of E1 data, and extract a clock from the data received from the trunk to provide a synchronizer clock. A trunk interface for processing R2 MFC signaling and switching E1 data and subhighway (SHW) data; A processor interface unit for exchanging subhighway data with the trunk interface unit, processing non-blocking digital switching, and communicating control information with the trunk interface via an L-bus; One board has 16 codecs, 16 modem chips, and 16 RS-232C interfaces to handle 16 channels of DS0 levels, and two boards are grouped to transmit the processor interface and one subhighway data. A plurality of subscriber modem connections for receiving / processing and communicating control information with the processor interface via an L-bus; A plurality of data processing units for multiplexing and demultiplexing by transmitting / receiving 32 sets of RS-232C data to and from the subscriber modem access unit and outputting the multiplexed data through a serial bus; Transmit and receive data through the serial bus with the plurality of data processing units, transfer data through the VME bus, exchange call processing related control information through the S-bus with the processor interface unit, and maintain the telephone network matching device. Service processing unit for processing; And a high speed switch interface unit connected to the service processor through a VME bus and connected through a high speed switch module and a TAXI bus, wherein the telephone network matching device of the high capacity communication processing system comprises: address / data transmitted through the L-bus; A bidirectional buffer transferring the signal in a specific direction according to the control signal; A first board timeslot allocator for latching data of a lower byte from the bidirectional buffer to provide first to sixteenth timeslot allocation signals for a first board; And a second board timeslot allocator for latching data of the upper byte from the bidirectional buffer to provide the 17th to 32nd timeslot allocation signals for the second board.

1 is a block diagram showing the overall configuration of a large capacity communication processing system;

2 is a block diagram showing a conventional telephone network matching device in a mass communication processing system;

3 is a block diagram showing a telephone network matching device to which the present invention is applied;

4 is a detailed block diagram of a subscriber modem access unit shown in FIG. 3;

5 is a block diagram showing a timeslot allocation circuit according to the present invention;

6A to 6H illustrate examples of timeslot allocation according to the present invention.

* Explanation of symbols for main parts of the drawings

101: public telephone network (PSTN) 301: L-bus

302: S-bus 303: RS-232C

304: serial bus 305: VME bus

306a, 306b: TAXI bus 310: trunk interface (TNIA)

312: processor interface (TPIA) 314: subscriber modem connection (TDIA)

316: data processing unit (HDPA) 318: service processing unit (TSPA)

319a, 319b: high speed switch interface 401: L-bus matching

402, 403: timeslot allocation controller 404: modem control unit

405: Board ID Buffer 406: Buffer

410-1 to 410-16: Codec 420-1 to 420-16: Modem

430-1 to 430-16: RS-232C interface unit 501,502: Bidirectional buffer

503 and 504: latch 510: first board timeslot allocation unit

520: the second board timeslot allocation unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the telephone network matching device to which the present invention is applied includes a trunk interface unit (TNIA; 310) that is directly connected to the public telephone network 101 and accommodates 4E1. Telephone Processing Interface Assembly (TPIA; 312), Subscriber Modem Interface (Text Data Interface Assembly: TDIA; 314), Highly Data Processing Assembly (HDPA: 316), Text Service Processor Assembly (TSPA; 318), It consists of a high speed network interface (High Speed Network Ad Apartment: HSNA; 319a, 319b).

Comparing FIG. 3 with FIG. 2, it can be seen that the telephone network matching device to which the present invention is applied has a very compact structure. Here, since the subscriber modem connection unit 314 capable of accommodating 16 channels can process one subhighway (SHW: 32 channels) in two sets, 2x4 = 8 boards are required to process 4E1. The data processor 316 correspondingly requires four boards (32 channels / board). The service processor 318 is redundant to improve reliability, and the high speed switch interface units 319a and 319b may also be duplicated.

Referring to FIG. 3, a trunk interface unit (TNIA) 310 may be connected to a public telephone network 101 to accommodate 4E1, and switch four time slots SHW to the processor interface unit 312 by switching time slots. It performs the digital trunk interface (TLI) function and link signal matching (LSI) function. The trunk interface unit (TNIA: 310) is connected to the processor interface unit 312 through the L bus 301 and is controlled by the processor interface unit (TPIA: 312) using a public telephone network (PSTN: 101) using the CEPT method. It is matched with relay circuit between stations and transmits / receives signal information of relay line using tone and R2 signal system. At this time, the transmission speed of the CEPT method (E1) is "2.048Mbps", and the line code "HDB3" is used.

The trunk interface (TNIA: 310) also accepts R2 signals, provides a ring back tone, and incorporates a network synchronizer to synchronize the transmission bits of the trunk line. The 2.048 MHz clock extracted from is used, and the local clock generated by the network synchronization circuit of the trunk interface 310 is 16.384 MHz. That is, the trunk interface unit 310 is provided with a network synchronization circuit to generate 16.384 MHz synchronized with 2.048 MHz extracted from the trunk line, and then divides it and is required by the processor interface unit 312 and the subscriber modem connection unit 314. Various clocks (4M, 2M, 8KHz clock) are provided.

Looking at the transmission operation is performed through the trunk interface 310, four sub-highway (SHW0 to SHW3) data consisting of 32 time slots input from the digital switch of the processor interface (TPIA: 312) is the trunk interface unit Channel matching is performed at the digital switch MT8980 of step 310 and input to the CEPT framer. The CEPT framer of the trunk interface unit 310 formats the subhighway data (SHW Data) and the signal data (Signalling Data) to the CEPT format, and performs HDB3 line coding at the line interface unit and then converts the unipolar-bipolar (U / B) into Output to CEPT type PCM trunk line.

On the contrary, the reception process receives the CEPT format data from the PCM relay line, switches the time slots in the trunk interface 310 to access the subhighway data, and processes various alarms, error detection, and signaling. The frame synchronization (FS: 8KHz) clock and the 4MHz clock required are generated by the network synchronization circuit of the trunk interface 310.

Meanwhile, the link signaling matching (LSI) function of the trunk interface unit (TNIA) 310 is an R2 MFC signal transmission / reception and a tone supply function. When the trunk interface unit 310 receives a scissors request from the trunk line, the trunk interface unit 310 transmits the scissors request information to the processor interface unit TPIA: 312, and the processor interface unit TPIA: 312 receives the request from the trunk. The input data channel is connected to the R2 signal receiving processor of the trunk interface unit. The trunk interface unit (TNIA) 310 receives a signal input from the trunk line, translates the signal, and transmits the signal to the processor interface unit (TPIA: 312). The trunk interface unit (TNIA) 310 provides forward and backward signals required by the R2 signaling method. In addition, the trunk interface 310 performs a tone providing function. Since only a ring back tone is required due to system characteristics, the trunk interface unit 310 continuously allocates a tone channel.

The processor interface unit TPIA: 312 processes control processing through the L-bus 301 for various events generated by the trunk interface unit TNIA: 310 and the subscriber modem connection unit TDIA: 314. It has a function of collecting various alarms of a device. In addition, a call-related communication is performed through the S bus 302 with a service processor (TSPA) 318, which is a higher processor. The processor interface unit TPIA 312 employs a Motorola multi-protocol processor (MC68302 IMP) to reduce and simplify circuit, power, and component density. Motorola's MC68302 is a high-performance processor that has a variety of peripheral devices that require a control structure in the existing 68000 CPU, and basically provides various interfaces required by a conventional processor.

As shown in FIG. 4, the subscriber modem connection unit (TDIA: 314) includes a buffer 406, codecs (CODECs 410-1 to 410-16), modems 420-1 to 420-6, and an RS232C interface unit ( 430-1 to 430-16), the L-bus matching unit 401 for interfacing the L-bus with the processor interface unit (TPIA: 312), the time slot assignment controllers 402 and 403, and read / write control data to the modem. The modem controller 404 and the board ID buffer 405 are provided. Accordingly, one subscriber modem connection unit 314 may include 16 codecs (CODECs 410-1 to 410-16), 16 modems 420-1 to 420-16, and 16 RS-232C interface units 430-1 to 430-16) are provided to accommodate 16 channels, and two boards are grouped to process one subhighway (32 channels).

The subscriber modem connection unit 314 is a text data line interface board for matching the information retrieval terminal connected to the public telephone network 101. The information retrieval terminal subscriber and data processing unit of the telephone network via the trunk interface unit TNIA 310 is used. (HDPA: 316) to provide a match. In addition, it provides a mode that can automatically detect the modulation method of the information search terminal. The board accommodates 16 channels, and is connected to the trunk interface 310 and the processor interface 312 through the L-bus 301. The subscriber modem access unit (TDIA: 314) modulates the digital data inputted from the data processing unit (HDPA: 316), filters the signal, and converts the digital data into a digital code signal by the PCM method to condense them into multiple communication paths. On the contrary, the PCM signal is demodulated and then transmitted to the data processing unit (HDPA) 316.

Referring to FIG. 3, the service processor TSPA 318 may include a high speed switch interface unit HSNA 319a and 319b and a data processor HDPA 316 for interworking with the high speed interconnect module HSSF 170 of FIG. 1. It is in charge of controlling function. The main functions of the service processing unit (TSPA) 318 provide the interface and management of subscribers of the telephone network, data processing of subscribers and information providers, interworking with the HSNA, and service control and self-maintenance functions.

The data processor (HDPA: 316) transmits and receives data in units of 32 channels / board, and assigns X.3 parameters to the received data and transmits them to the service processor (TSPA: 318) through the transmission and reception queues defined in units of 132 bytes. do. The service processing unit (TSPA) 318 transmits the packet related information to the high speed switch interface unit (HSNA: 319a, 319b) via the VME bus 305, and the high speed switch interface unit (HSNA: 319a, 319b) transmits this data. The high speed switch module (HSSF: 170 of FIG. 1) is transferred to the corresponding packet network matching device (PNAS: 120 of FIG. 1).

Motorola's MC68030 / 50MHz is used as the main processor of the service processor (TSPA: 318) and Motorola's MC68360, an IPC dedicated communication processor, is used for data communication with the data processor (HDPA: 316). Data is transmitted in an interrupt manner through 1M bytes of common memory. The data processor (HDPA: 316) uses Motorola's MC68360 / 25MHz as the main processor and controls four slave processors. The main processor of the data processor (HDPA: 316) transmits / receives data with the slave and the service processor (TSPA: 318) in 2 Mbps serial communication.

In FIG. 3, the trunk interface unit 310, the processor interface unit 312, and the subscriber modem connection unit 314 are connected by the L-bus 301, and the processor interface unit 312 and the service processor 318 are connected to each other. The bus 302 is connected, and the data processor 316 and the service processor 318 are connected to the serial bus 304. The service processing unit 318 and the high speed switch interface unit 319a and 319b are connected through the VME bus 305, and the subscriber modem connection unit 314 and the data processing unit 316 are connected to a plurality of RS-232Cs 303. The high speed switch interface units 319a and 319b are connected to the high speed switch module HSSF through the TAXI bus (100Mbps: 306a, 306b).

4 is a detailed block diagram of the subscriber modem access unit shown in FIG. 3, and FIG. 5 is a block diagram showing a modem timeslot allocation circuit according to the present invention.

Referring to FIG. 4, the subscriber modem connection unit TDIA is roughly divided into a path through which PCM data is transmitted through the subhighway SHW and a path through which control data is transmitted from the processor interface TPIA through the L-bus. . As shown in the figure, one subscriber modem connection 400 includes 16 codecs 410-1 to 410-16, 16 modems 420-1 to 420-16, and 16 RS232C interfaces 430-. 1 to 430-16 are provided to accommodate 16 channels, and one subhighway is processed through two subscriber modem connections.

32 channels are loaded on the subhighway SHW0 received from the trunk side via the buffer 406, and one of these timeslots is selected and decoded by the codecs 410-1 to 410-16. The selected time slot is determined by the frame synchronization signals FS0 to FS15 of the timeslot allocation controller. The analog voice band signals decoded by the codecs 410-1 to 410-16 are amplified by a reception amplifier (not shown) and then input to the modems 420-1 to 420-16, and demodulated by the modem to output digital data. . This digital data is output to the data processing unit HDPA as received data through the RS-232C matching units 430-1 to 430-16.

On the contrary, the transmission digital data received from the data processing unit HDPA to the RS-232C matching units 430-1 to 430-16 is input to the modems 420-1 to 420-16 through the transmission data terminal, and the modem ( 410-1 to 410-16 are modulated into analog voice band signals and input to codecs 410-1 to 410-16 through a transmission amplifier (not shown), and PCM data from codecs 410-1 to 410-16. Is coded and output through the buffer 406. At this time, the transmission and reception PCM data has a rate of 8bit x 8KHz = 64 Kbit / s, and the voice band is usually 300Hz to 3400Hz. TXD, RXD, DTR, CTS, and DCD signal lines are used for the RS-232C interface between the modem and the data processor. The meaning of each signal line is as known.

On the other hand, the control data between the processor interface (TPIA) and the subscriber modem connection (TDIA), the L-bus matching unit 401, the timeslot allocation controller (402, 403), the modem controller 404, the board ID buffer 405 Is passed through.

After the processor interface enables the board ID buffer 405 with a read signal (/ SRD), the board ID is read. When the processor writes a predetermined address and data on the L-bus, latches control data through the subscriber modem connection. To assign timeslots. At this time, the 8-bit control data latched from the L-bus is CLK, DATA, CH0, CH1, CH2, CS0, CS1. CLK is a clock for transmitting 8-bit serial control data input through the DATA line, and CH0 to CH2 are control signals for selecting one channel among eight channels that can be allocated by the timeslot allocation controllers 402 and 403. , CS0 is a chip select signal for selecting the first timeslot allocation controller 402 from the two timeslot allocation controllers 402 and 403 used for the 16 channels, and CS1 is the second time slot allocation controller 403. Chip selection signal for selection.

Accordingly, the first timeslot allocation controller 402 and the second timeslot allocation controller 403 receive the control data and generate a frame synchronization signal for selecting 16 timeslots from FS0 to FS15 to provide the corresponding codec.

In addition, the modem controller 404 includes an address buffer and reads / writes a modem by receiving control data for controlling the modem unit when a predetermined address is input. For example, when the predetermined data is output after writing a predetermined address, 16 modems are written. Provides ring detection signals (RINGD 0 to RINGD 15) for starting the corresponding ones of the modem chips, and outputs a predetermined address and reads data. The TPIA can read it.

As described above, the operation performed between the subscriber modem access unit (TDIA) and the processor interface unit (TPIA) through the L-bus accesses a specific board according to an address determined for each board as shown in the following table. Or writes the board ID, the ring detection signal RINGD, or the hook off signal HOOK OFF.

TABLE 1

Address (Hexadecimal) Lead / light Control Target Board Control operation 201000 light TDIA1 Timeslot Allocation Control 201002 lead " BoardID Reed 201004 light " Ring detection signal light 201006 lead " Hook off state lead 202000 light TDIA2 Timeslot Allocation Control 202002 lead " BoardID Reed 202004 light " Ring detection signal light 202006 lead " Hook off state lead 203000 light TDIA3 Timeslot Allocation Control 203002 lead " BoardID Reed 203004 light " Ring detection signal light 203006 lead " Hook off state lead 204000 light TDIA4 Timeslot Allocation Control 204002 lead " BoardID Reed 204004 light " Ring detection signal light 204006 lead " Hook off state lead 205000 light TDIA5 Timeslot Allocation Control 205002 lead " BoardID Reed 205004 light " Ring detection signal light 205006 lead " Hook off state lead 206000 light TDIA6 Timeslot Allocation Control 206002 lead " BoardID Reed 206004 light " Ring detection signal light 206006 lead " Hook off state lead

As shown in the above table, the control operation for each board includes time slot assignment control (write) for allocating time slots to a plurality of modems, a board ID read for reading a board ID for board identification, and for starting a modem. There is a modem write operation for writing a ring detection signal RINGD to the modem, and a modem read operation for reading a hook off signal HOOK OFF to grasp the state of the modem. This control operation is performed by the L-bus read / write operation for a specific address as shown in the above table. For example, in order to activate a specific modem of the TDIA 5 board, the specific data is written to the address "205004H".

Here, the L-bus is briefly described. In order to reduce signal lines, the L-bus is multiplexed with address and data lines, and is capable of addressing up to 23 external devices on its own. That is, the AD15-0 is a multiplex bus in which addresses and data are loaded at different times. Address 15-0 is loaded first while the address enable (/ AE) signal is active, and then data 15-0 is loaded while the data enable (/ DE) signal is active. The device select (/ SEL17-0) signal is the address the processor outputs to select the device, and SCLK is the system clock on the bus. The address enable (/ AE) signal indicates the address is loaded on the AD15-0 bus, which indicates that the signal is low and that the address is valid on the falling edge of the first SCLK. The data enable (/ DE) signal indicates that data is loaded on the AD 15-0 bus. This signal is low and indicates that data is valid on the first SCLK rising edge. The read (/ SRD) signal is a signal indicating that the processor is reading data of the device, and the write (/ SWR) signal is a signal indicating that the processor is writing data to the device. The wait (/ WAIT) signal is a signal that the device waits for the processor to wait when the device has a delay (for example, a slow processing device) and fails to load data immediately after the address latch. The data type (/ CD) signal is high for normal data and low for CODEC data, and the bus width (/ BW) signal is high if the data being operated is bytes and low if it is a word. Here, "/" in front of the signal indicates that it is an active low signal.

Referring to FIG. 5, the timeslot allocation circuit according to the present invention includes bidirectional buffers 501 and 502, latches 503 and 504, a first board timeslot allocator 510, and a second board timeslot allocator 520. Each time slot assignment unit 510 or 520 receives a latch 511 for latching control data and a latched control data and outputs first to eighth frame synchronization signals FS0 to FS7. An allocation controller (TSAC0: 512) and a second timeslot allocation controller (TSAC1: 513) for receiving the latched control data and outputting the ninth to sixteenth frame synchronization signals (FS8 to FS15).

In FIG. 5, the AD15-AD0 bus of the L bus is connected to the bidirectional buffers 501 and 502, and the address outputs of the bidirectional buffers 501 and 502 are latched by the first latch 504 and the second latch 503, and the bidirectional buffer. The lower byte data of the latch is latched by the latch 511 of the first board timeslot allocator 510, and the upper byte data of the bidirectional buffer is latched by the latch of the second board timeslot allocator 520. The control data latched by the latch 511 is CLK, DATA, CH0, CH1, CH2, CS0, CS1 as described above. CLK is a clock for transmitting 8-bit serial control data input through the DATA line, CH0 to CH2 are control signals for selecting one channel among eight channels that can be allocated by the timeslot allocation controller, and CS0 is A chip select signal for selecting a first timeslot allocation controller in two timeslot allocation controllers used for 16 channels, and CS1 is a chip select signal for selecting a second time slot allocation controller.

When the CS0 signal is low, the first timeslot assignment controller 512 receives the channel information and the control data, generates a frame synchronization signal for allocating eight timeslots from FS0 to FS7, and provides the corresponding codec to the corresponding codec. When the CS1 signal is low, the second timeslot allocation controller 513 receives the channel information and the control data, generates a frame synchronization signal for allocating eight timeslots from FS8 to FS15, and provides the corresponding codec to the corresponding codec. do.

The second board timeslot allocator 520 is configured in the same manner as the first board timeslot allocator 510 to latch the upper byte data, and then, according to the latched control data, a third timeslot allocation controller and a fourth time slot allocator 520. The timeslot assignment controller generates frame synchronization signals from FS16 to FS31 and provides them to the corresponding codec.

6A to 6H illustrate examples of timeslot allocation according to the present invention. Referring to FIG. 6A, in the latched lower byte, D0 is a clock CLK, and 1 and 0 are repeated to provide clock information. D1 is control data DATA for allocating timeslots. It is input and shows information about the timeslot. That is, the control data DATA is inputted in serial 8 bits. When all 8 bits are input, the control data DATA indicates T0, T1, T2, T3, T4, T5, R, and X from the lower byte. T0 to T5 represent information on timeslots. D2 represents the chip select signal CS0, D3 represents the chip select signal CS1, and D4 to D6 represent channel signals for distinguishing eight channels that can be processed by one timeslot allocation controller.

6A is an example of assigning timeslots 0 to 3 timeslots 3 to channels 0 to 3, and FIG. 6B is an example of assigning timeslots 4 to 7 timeslots to channels 4 to 7, and FIG. This is an example of assigning timeslot 8 to timeslot 11 to channel 11. 6D to 6H are examples of allocating timeslot 12 to timeslot 31 to channels 12 to 31 in the same manner.

As described above, the telephone network matching device of the high-capacity communication processing system according to the present invention can easily set up a modem by allocating time slots to a plurality of modems. In particular, when one subhighway is processed by two boards, the time slot can be accurately allocated using the circuit of the present invention.

Claims (3)

It is connected to a digital trunk of a public telephone network and transmits / receives a predetermined number of E1 data, extracts a clock from the data received from the trunk, provides a network synchronizer clock, processes R2 MFC signaling, and handles E1 data and subhighway ( SHW) trunk interface unit 310 for switching data; A processor interface unit 312 for exchanging sub-highway data with the trunk interface unit, processing non-blocking digital switching, and communicating control information with the trunk interface via an L-bus; One board has 16 codecs, 16 modem chips, and 16 RS-232C interfaces to handle 16 channels of DS0 levels, and two boards are grouped to transmit the processor interface and one subhighway data. A plurality of subscriber modem connections 314 for receiving and processing and communicating control information with the processor interface via an L-bus; A plurality of data processing units 316 for multiplexing and demultiplexing by transmitting / receiving 32 sets of RS-232C data with a set of subscriber modem accessing units and outputting the multiplexed data through a serial bus; Transmit and receive data through the serial bus with the plurality of data processing units, transfer data through the VME bus, exchange call processing related control information through the S-bus with the processor interface unit, and maintain the telephone network matching device. Service processing unit 318 for processing; And a high speed switch interface unit (319a, 319b) connected to the service processor through a VME bus and connected through a high speed switch module and a TAXI bus. Bidirectional buffers 501 and 502 which transmit address / data transmitted through the L-bus in a specific direction according to a control signal; A first board timeslot allocator (510) for latching data of a lower byte from the bidirectional buffer to provide first to sixteenth timeslot allocation signals for a first board; And a second board timeslot allocator 520 for latching data of the upper byte from the bidirectional buffer to provide the 17th to 32nd timeslot allocation signals for the second board. A modem time slot assignment circuit in a telephone network matching device. The method of claim 1, wherein the first board timeslot allocator 510, A latch for latching lower byte data from the bidirectional buffer, a first timeslot allocation controller that receives the latched control data and provides first to eighth timeslot allocation signals, and receives the latched control data And a second timeslot allocation controller for providing ninth to sixteenth timeslot allocation signals. The method of claim 1, wherein the second board timeslot allocator 520, A latch for latching higher byte data from the bidirectional buffer, a first timeslot allocation controller that receives the latched control data and provides a 17th to 24th timeslot allocation signal, and receives the latched control data And a second timeslot assignment controller for providing a twenty-fifth to thirty-second timeslot assignment signal.

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