KR100326521B1 - Logic Conversion Apparatus For xDSL Modem System - Google Patents

Abstract

The object of the present invention is to use the Q switch only for upstream clock synchronization, downstream clock synchronization, hardware reset, interrupt, ADSL parallel Indirect Direct Memory Access (IDMA) port, and DSP address line, which are essential in ADSL 3V logic. It is to provide logic conversion device of xDSL system that implements logic conversion by connecting with 5V logic such as main CPU, CDB and reset logic. The logic converter of the xDSL system according to an embodiment of the present invention for achieving the above object is a 3V logic of the duplex transmit signal having 5V logic provided in the CDB area in the subscriber-mode modem of the xDSL broadband system implementing the ATM interface It converts into a duplex transmission signal having a DSL and provides it to the ADSL primer, and the duplex clock, the simplex received signal, and the simplex clock provided by the ADSL primer having 3V logic, respectively, the duplex clock and the simplex received signal having 5V logic. And a Q switch provided to the CDB by converting to a simplex clock.

Description

Logic Conversion Apparatus for XDSL Modem System

The present invention relates to an xDSL system such as ASL (Asymmetric Digital Subscriber Line), VDSL, HDSL, etc. In particular, a logic conversion device of an xDSL system that selects only necessary control signals and clock signals to perform logic conversion using a Q switch. It is about.

Conventional modems have a problem in that they are difficult to configure by using a passive element and an active element in a separate logic conversion form or a new form of logic is difficult. Thus, it was difficult to achieve the desired speed and low power and to solve the heating problem, which is a major problem of ADSL modems. The heating of ADSL by itself can cause system instability, which can be a major cause of failing to obtain satisfactory ADSL performance from the subscriber's modem and cause the trouble of having to fan inside the modem.

Thus, the implementation of 3V low power logic is essential. However, if the conversion problem between the 3V logic and the 5V logic is not solved, there is a problem in that the circuit design is limited, and the high cost of ASIC is required to configure the desired logic.

Accordingly, an object of the present invention is to provide a Q switch for only upstream clock synchronization, downstream clock synchronization, hardware reset, interrupt, ADSL parallel Indirect Direct Memory Access (IDMA) port, and DSP address lines, which are essential in ADSL 3V logic. By connecting to 5V logic such as main CPU, CDB, reset logic, etc., it is to provide logic conversion device of xDSL system that implements logic conversion.

1 is a block diagram of a general ADSL system.

2 is a detailed block diagram of the ADSL central station in FIG.

3 is a block diagram of a logic converter of a control portion in an ADSL modem system according to an embodiment of the present invention.

4 is a block diagram of a logic converter in ATU-R that is a subscriber end in an ADSL modem system in accordance with an embodiment of the present invention.

5 is a block diagram of a logic converter in ATU-C that is a telephone station in an ADSL modem system according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

17,37,67: Q switch 27,57: CDB

47,77: ADSL Framer

The logic converter of the xDSL system according to an embodiment of the present invention for achieving the above object is a 3V logic of a duplex transmit signal having 5V logic provided in the CDB area in the subscriber-mode modem of the xDSL broadband system implementing the ATM interface It converts into a duplex transmission signal having a DSL and provides it to the ADSL primer, and the duplex clock, the simplex received signal, and the simplex clock provided by the ADSL primer having 3V logic, respectively, the duplex clock and the simplex received signal having 5V logic. And a Q switch provided to the CDB by converting to a simplex clock.

In addition, the logic converter of the xDSL system according to an embodiment of the present invention for achieving the above object is a read signal, write having a 5V logic provided from the CPU in the subscriber-mode modem of the xDSL broadband system implementing the ATM interface Signal, IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal respectively with 3V logic read signal, write signal, IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal To the ADSL control DSP, and the signal used as the flag output of the DSP with the 3V logic provided by the ADSL control DSP, and the signal and address signals used as interrupts for IDMA page downloads and IDMA MP message responses. Q switch for converting into a signal and an address signal provided to the CPU All.

In addition, the logic converter of the xDSL system according to an embodiment of the present invention for achieving the above object is to provide a simplex transmission signal having 5V logic provided in the CDB in the telephone station modem of the xDSL broadband system implementing the ATM interface. It converts into a simplex transmission signal having 3V logic and provides it to the ADSL primer, and the duplex received signal having the 3V logic, the duplex sync clock, and the simplex sync clock respectively provided by the ADSL primer have a duplex received signal having 5V logic. And a Q switch which is converted into a duplex sync clock and a simplex sync clock and provided to the CDB.

In addition, the logic converter of the xDSL system according to an embodiment of the present invention for achieving the above object, in the telephone station modem of the xDSL broadband system that implements the ATM interface, the read signal, write signal having 5V logic provided from the CPU , IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal into read signal, write signal, IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal each having 3V logic. 5V logic is converted to the ADSL control DSP, and the signal used as the flag output of the DSP with the 3V logic provided by the ADSL control DSP, the signal and address signals used as interrupts for IDMA page downloads and IDMA MP message responses. And a Q switch which is converted into a signal and an address signal provided to the CPU. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a network configuration of an ADSL broadband access system according to the present invention.

An important feature of the ADSL system is that it can provide high-speed digital services simultaneously on existing twisted pair copper networks without interfering with the analog old telephone service (POTS).

It is a technology that increases bandwidth to simultaneously transmit multimedia information such as voice, graphic, and video while using existing telephone line. Therefore, it is receiving attention as a service network that can deliver multimedia information to subscribers without incurring network installation cost.

Thus, new services can be created that can be provided to telephone subscribers such as high speed internet, online access and telecommuting, and video on demand (VOD). In addition, there is no need to install a new line, so it is possible to implement the service more economically and faster than using other systems.

The line coding scheme of ADSL includes DMT (Discret Multi-Tone) and CAP (Carrierless Amplitude). The line coding method is a technology that modulates and demodulates digital data and transmits it on a twisted pair. Among them, the DMT method, which is set by the American National Standards Institute (ANSI), has a downlink rate of up to 8 Mbps and an uplink of 640 kbps Data can be delivered at the rate.

The broadband access system proposed in the present invention has advantages such as flexibility of use bandwidth and flexibility of service using various traffic characteristics through ATM based transmission.

The basic block of the ADSL broadband access system according to the embodiment of the present invention is an ADSL central station connected to an ATM switch 3 connected to an Internet network 1 through an ISP 2 and a public switched telephone network (PSTN) 4. (Central Office) 5, the ADSL central station (5) and the copper pair, connected to the telephone (6) and PC (8), ADSL network access system and subscriber located in the Digital Loop Carrier (DLC) It consists of an ADSL subscriber modem 7 located in the home (home, office).

The operation of the ADSL broadband access system configured as described above will be described in detail as follows.

The ADSL network access system is connected to a backbone network, that is, a data backbone network and an ATM network, and the PSTN network 4 is connected to a subscriber line. The interface between the PC (8) or the TV, the subscriber terminal, and the ADSL subscriber system uses the ATM Forum's 25Mbps or Ethernet 10BaseT connection and does not affect the subscriber's use of the telephone.

The POTS splitter mixes analog telephony services and digital ADSL services so that the original telephony service and the new high-speed service are mixed on the twisted pair.

ADSL network access system connects ATM 155Mbps OC-3c or ATM 45Mbps T3 from the broadband network to the uplink network access board, and the input data is multi / demultiplexed or switched on the ATM cell bus. Line Termination The modulated data via the ADSL transceiver of the board is mixed on the telephone line on the POTS splitter and transmitted to the subscriber.

The telephone line to the subscriber is separated through the POTS splitter in the subscriber modem. If only the modulated ADSL data is input to the ADSL subscriber system, the ADSL transceiver extracts the ADSL demodulation and ATM cell data from the ADSL frame, and the subscriber interface to the PC or TV is 25 Mbps ATM Forum 25 Mbps I / F TC + PMD The device connects to a PC (8) or TV via an UTP-3 (Unshield Twisted Pair-3) cable.

If the subscriber interface to the PC (8) or TV is Ethernet 10BaseT, the extracted ATM cell data is subjected to Ethernet packet data by performing segmentation & reassembly (SAR) function of ATM Adaptation Layer and VC-based demultiplexing. And then connected to the PC via the MAC controller and Ethernet line driver.

The upstream data transmitted from the subscriber via the ADSL subscriber system via the telephone line is separated from the telephone data in the POTS splitter function block of the ADSL network access system, and the separated telephone service data is connected to the central office telephone exchange.

The separated ADSL upstream data is extracted from the ADSL frame through the ADSL transceiver of the ADSL-LT board of the ADSL network access system, and then multiplexed on the ATM cell bus and connected to the broadband network through the uplink network access board.

The ADSL network access system controls and operates the ADSL-LT board and the uplink network access board, which are the ADSL subscriber boards, as well as the control / operation that collects subscriber information and network-related status information from these boards and delivers them to the ADSL network management system. The board operates under the SNMP agent protocol.

2 is a block diagram of an ADSL-LT, which is an ADSL subscriber interface board in an ADSL network access system.

ADSL-LT 45 is a cell bus interface control device that performs ATM cell multiplexing / demultiplexing on a cell bus, and multiplexes a cell stream into multiple cell streams to accommodate multiple subscriber interfaces within a board. Cell multiplexing device (Cell MUX) with demultiplexing, Transmission Convergence Sublayer of ATM physical layer, ie Idel cell insertion and removal, cell payload scramble / descramble, cell delineation, An ATM handler device that performs HEC checking and generation and converts an ATM UTOPIA interface into a modem byte interface, an ADSL transceiver that performs ADSL frame forming, modulation / demodulation, and the like, an ADSL line driver, and the cell bus interface Microcontrollers respectively control devices, cell multiplexing devices, ATM handler devices, ADSL transceivers, and ADSL line drivers It consists of a processor.

The ADSL-LT board configured as described above is a modem including a splitter in a telephone company, which does not require a separate splitter board, and the modem includes a splitter function. Splitters with passive components do not need a separate power supply.

3 is a logic converter of an ADSL modem system according to an embodiment of the present invention, which is an ADSL transceiver unit-remote terminal end (ATU-R) of a subscriber station supporting an ATM interface and an ADSL transceiver unit (ATU-C) which is a telephone station. The logic converter of the control part at the central office end is shown.

As shown in FIG. 3, the Q switch 17, which is a logic converter of the ADSL modem system according to the embodiment of the present invention, has a read signal IRD_5V, a write signal IWR_5V, and IDMA having 5V logic provided from a CPU. The port select signal IS_5V, the address latch signal IAL, the interrupt recognition signal IACK_5V, the reset signal RESET_5, and the address signal AD15_5V to AD0_5V, respectively, the read signal IRD_3V having the 3V logic and the write signal IWR_3V. ), The IDMA port selection signal IS_3V, the address latch signal IAL, the interrupt recognition signal IACK_3V, the reset signal RESET_3V, and the address signals AD15_3V to AD15_3V are provided to the ADSL control DSP.

In addition, the Q switch 17, which is a logic converter of the ADSL modem system, is used as an interrupt for a signal (MP_IRQ_3V), IDMA page download and IDMA MP message answer, which is used as a flag output of a DSP having 3V logic provided by an ADSL control DSP. The signals IDMA_IRQ_3V and the address signals AD15_3V to AD0_3V used are converted into signals MP_IRQ_5V, IDMA_IRQ_5V, and address signals AD15_5V and AD0_5V having 5V logic and provided to the CPU.

The operation of the logic converter of the ADSL modem system according to the embodiment of the present invention configured as described above will be described in detail as follows.

An IDMA port is used to communicate with an ADSL DMT (Descrete Multi-Tone) transceiver from a central station external to an ADSL framer or a host system of a RT (Remot Terminal). The IDMA port is composed of a read signal IRD, a write signal IWR, an IDMA port select signal IS, an interrupt recognition signal IACK, an address latch signal IAL, an address signal AD15 to AD0, and the like. It is used to interface and boot to a Management Entity (ME) external to the DMT transceiver. The IDMA_IRQ signal is used as an interrupt for IDMA page downloads and IDMA MP message responses. MP_IRQ is used as a flag output of the DSP block, which interrupts the ME when one or more events occur and is configured by Configuration and Management Variables (CMVs).

These signals represent the interface between the 5V logic ME and the 3V DSP block and can be connected to each other using Q switches.

4 is a diagram illustrating a connection method of a modem including an ADSL primer side and an ATM TC side in ATU-R, which is a subscriber station supporting an ATM interface, as a logic converter of an ADSL modem system according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the Q switch 37, which is a logic converter of the ADSL modem system according to an exemplary embodiment of the present invention, converts a duplex transmission signal (DUPLX_TX_5V) having 5V logic provided from the CDB 27 area to 3V logic. The signal is converted into a duplex transmission signal DUPLX_TX_3V and provided to the ADSL framer 47.

In addition, the Q switch 37 includes a duplex clock (DUPLX_CLKO_3V), a simplex reception signal (SIMPLX_RX_3V), and a simplex clock (SIMPLX_CLKO_3V) provided by the ADSL framer 47 having 3V logic, respectively. It is converted into a clock (DUPLX_CLK0_5V), a simplex received signal (SIMPLX_RX_5V) and a simplex clock (SIMPLX_CLKO_5V) and provided to the CDB (27).

The operation of the logic converter of the ADSL modem system according to the embodiment of the present invention configured as described above will be described in detail as follows.

First, if the simplex received signal SIMPLX_RX_3V with 3V logic from ADSL framer 47 to Q switch 37 is provided with a synchronous clock SIMPLX_CLKO_3V with 3V logic, the Q switch 37 is provided with The simplex received signal (SIMPLX_RX_3V) and the synchronous clock (SIMPLX_CLKO_3V) having 3V logic are converted to 5V logic and provided to the CDB 27.

The duplex transmission signal DUPLX_TX_5V having the 5V logic provided from the CDB 27 is converted into the duplex transmission signal DUPLX_TX_3V having the 3V logic via the Q switch 37 and provided to the ADSL framer 47. do. At this time, the duplex synchronous clock (DUPLX_CLKO_3V) having the 3V logic provided by the ADSL primer 47 is converted into the duplex synchronous clock (DUPLX_CLKO-5V) having the 5V logic via the Q switch 37 and the CDB 27 Is provided.

As such, signals having 5V logic provided by the CDB 27 are converted into signals having 3V logic via the Q switch 37, and signals having 3V logic provided by the ADSL primer 47 are also converted. The Q switch 37 is converted into signals having 5V logic.

5 is a block diagram of a logic converter of an ADSL modem system according to an exemplary embodiment of the present invention.

As shown in FIG. 5, the Q switch 67, which is a logic converter of the ADSL modem system according to the embodiment of the present invention, converts the simplex transmission signal SIMPLX_TX_5V having the 5V logic provided from the CDB 57 into 3V logic. The signal is converted into a simplex transmission signal SIMPLX_TX_3V and provided to the ADSL framer 77.

In addition, the Q switch 67 has a 5V logic of the duplex received signal (DUPLX_RX_3V), the duplex synchronous clock (DUPLX_CLKO_3V) and the simplex synchronous clock (SIMPLX_CLKI_3V), respectively, having the 3V logic provided from the ADSL framer 77. The duplex reception signal DUPLX_RX_5V, the duplex synchronous clock DUPLX_CLKO_5V, and the simplex synchronous clock SIMPLX_CLKI_5V are converted to the CDB 57.

The operation of the logic converter of the ADSL modem system according to the embodiment of the present invention configured as described above will be described in detail as follows.

First, when a simplex transmission signal SIMPLX_TX_5V having 5V logic provided from the CDB 57 is provided to the Q switch 67, the Q switch 67 has a simplex transmission signal SIMPLX_TX_5V having the provided 5V logic. Is converted into a simplex transmission signal SIMPLX_TX_3V having 3V logic and provided to the ADSL framer 77.

At this time, the simplex synchronous clock (SIMPLX_CLKI_3V) having the 3V logic provided by the ADSL primer 77 is converted into the simplex synchronous clock (SIMPLX_CLKI_5V) having the 5V logic via the Q switch 67 and the CDB 57 ) Will be provided.

In addition, the duplex receive signal DUPLX_RX_3V and the duplex synchronous clock DUPLX_CLKO_3V provided by the ADSL primer 77 are passed through the Q switch 67 and the duplex receive signal DUPLX_RX_5V and duplex via the Q switch 67. After the conversion to the synchronous clock (DUPLX_CLKO_5V), it is provided to the CDB (57).

As described above, the present invention does not require a logic design and chip development for ASIC, and simply converts only necessary control signals and clock signals while implementing logic. The subscriber end (ATU-R) and the telephone end (ATU-C) By performing the two Q switches provided in each, an efficient xDSL system and a modem can be developed to induce a decrease in the price of the xDSL system and accelerate commercialization. Therefore, not only is the possibility and economic effect very large, but also has an effect that can be variously applied to the xDSL network access system that the demands and services are rapidly created in recent years.

Claims (4)

A subscriber end modem of an xDSL broadband system that implements an ATM interface, Converts a duplex transmission signal having 5V logic provided in the CDB region to a duplex transmission signal having 3V logic and provides it to the ADSL primer 47, and the duplex clock and simplex reception signal provided by the ADSL primer having 3V logic. And a Q switch for converting a simplex clock into a duplex clock, a simplex received signal, and a simplex clock having 5V logic, respectively, and providing the simplex clock to the CDB. A subscriber end modem of an xDSL broadband system that implements an ATM interface, Read signal, write signal, IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal having 5V logic provided from the CPU respectively, read signal, write signal, IDMA port selection signal, address It converts into latch signal, interrupt recognition signal, reset signal, and address signal to ADSL control DSP, and is used as flag output of DSP with 3V logic provided in ADSL control DSP, IDMA page download and IDMA MP message reply. And a Q switch for converting a signal and an address signal used as an interrupt for the signal into a signal and an address signal having 5V logic and providing the same to the CPU. A telephone station modem in an xDSL broadband system that implements an ATM interface, Converts the simplex transmission signal having the 5V logic provided by the CDB into the simplex transmission signal having the 3V logic and provides the ADSL framer, the duplex received signal having the 3V logic provided by the ADSL framer, the duplex sync clock and Logic converter of X-DSL modem system comprising a Q switch for converting a simplex synchronous clock into a duplex received signal having a 5V logic, a duplex synchronous clock and a simplex synchronous clock and providing the CDB to the CDB. . A telephone station modem in an xDSL broadband system that implements an ATM interface, Read signal, write signal, IDMA port selection signal, address latch signal, interrupt recognition signal, reset signal and address signal having 5V logic provided from the CPU respectively, read signal, write signal, IDMA port selection signal, address It converts into latch signal, interrupt recognition signal, reset signal, and address signal to ADSL control DSP, and is used as flag output of DSP with 3V logic provided in ADSL control DSP, IDMA page download and IDMA MP message reply. And a Q switch for converting a signal and an address signal used as an interrupt for the signal into a signal and an address signal having 5V logic and providing the same to the CPU.