KR20010017110A - Apparatus for detecting velocity of motor - Google Patents

Abstract

PURPOSE: A motor speed detector is provided to detect a reliable rotational speed of a motor by employing a low-speed peripheral device while maintaining the performance of a system using a high-speed CPU(central processing unit). CONSTITUTION: A motor speed detection device is composed of: a filter unit(1) filtering signals(A,B) input from an encoder; a digital filter unit(2) digital-filtering the output signals of the filter unit to a stable data; a control signal generating unit(3) receiving the output signals of the digital filter unit and generating control signals about a rotational direction command and a rotational degree countering function of a motor; and a multiple selection unit(13) selecting the outputs of first and second counter units(11,12) outputting a new value increased or decreased from the output value of the speed control unit and outputting the selected value to a speed control unit. While maintaining the performance of a system using a high-speed CPU, a reliable rotational speed of a motor is detected. Therefore, improved system performance and cost saving effect are obtained.

Description

Motor speed detector {APPARATUS FOR DETECTING VELOCITY OF MOTOR}

The present invention relates to a motor speed detecting device, and more particularly, to a motor speed detecting device suitable for detecting a rotational speed of a reliable motor using a low speed peripheral device while maintaining the performance of a system using a high speed CPI. will be.

In general, in order to control the speed of the motor, information on the motor speed is required, and an encoder is mainly used as a sensor for detecting the speed of such a motor.

The encoder is classified into an absolute encoder and an incremental encoder. Since the absolute encoder receives data in the form of serial communication, the data passing through the serial communication circuit becomes a quantitative value internally, but the incremental encoder is rotated. Since the rotation and position information of the motor is sent to the controller in the form of A, B, C, U, V, and W, a process of converting each signal back into quantitative data is required.

In the case of general incremental encoders, A and B signals, which are used as incremental data among the input signals, have a phase difference of 90 °, and are applied through an application-specific integrated circuit (ASIC) or a general-purpose programmable logic device (PLD). The rising edge and falling edge of the A and B signals passing through the dedicated receiver on the hardware are countered to obtain information on the position and speed of the motor.

In other words, if the count value is large in a certain period, the rotation speed of the motor is high. If the count value is small, the rotation speed of the motor is low, and the servo driver detects the rotation speed of the motor in this manner.

Of course, the motor rotates too slowly and the system can run relatively fast and have a constant count value in a few cycles, but this is something that needs to be considered internally in the controller, and the speed detector accurately delivers the actual encoder information to the controller. All you need is enough.

As described above, the M / T method using the encoder increment and the detection time for a certain period is the most reliable information, but the method of using the speed observer according to the rotational speed of the motor is also used.

On the other hand, for accurate control of the motor, the reliability of encoder information for feedback of rotational state must be guaranteed, and this reliability is closely related to the reliability of hardware that converts encoder information into quantitative form.

In recent years, the speed control cycle has been shortened due to the appearance of the CPU having high processing speed, which affects the design of the speed detection device that must operate at the same system speed.

The conventional motor speed detection apparatus will be described in detail with reference to the drawings.

1 is a block diagram illustrating a conventional motor speed detecting device. As shown in FIG. 1, a filter unit 1 for removing noise components of signals A and B input from an encoder (not shown) through filtering and ; A digital filter unit 2 for digitally filtering the output signals Ahf and Bhf of the filter unit 1 with stable data; Generates a control signal that receives the output signals Asf and Bsf of the digital filter unit 2 and generates a control signal (UP / DOWN, COUNTER-EN) for the motor rotation direction command and the motor rotation counter function. Part 3; By the counting operation according to the control signal (UP / DOWN, COUNTER-EN) of the control signal generator 3 to the rotation amount counter (4) for outputting the incremental data to the speed control unit via the data bus (DATA-BUS) In the drawing, reference numeral 'CLK' in the figure synchronizes the operation of each part with a system clock signal.

2 schematically shows a 16-bit counter circuit as an example of the rotation counter 4, in which flip-flops F / F-1 to F / F16 according to each bit are in series. The control signals UP / DOWN, COUNTER-EN and the system clock CLK of the control signal generator 3 are respectively input.

Hereinafter, the operation of the conventional motor speed detecting apparatus as described above will be described with reference to the input / output waveform diagram of FIG. 3, it is assumed that the rising point of the signal A output from the encoder occurs, and the control signals UP / DOWN and COUNTER-EN are UP / DOWN = 0 and COUNTER-EN = 1.

First, the filter unit 1 generates an output signal Ahf or Bhf by removing a noise component from a line drive type signal A or B input from an encoder as the motor and the servo drive are operated at a predetermined distance. .

In addition, the digital filter unit 2 has a fixed period (a, b, 3 cycles) in which the output signals Ahf and Bhf of the filter unit 1 are constant from the falling point of the system clock CLK. In the same manner, the output signals Asf and Bsf are output at the rising point D of the system clock CLK. At this time, if the output signals Ahf and Bhf of the filter unit 1 are not equally input for a certain period, the output signals Asf and Bsf of the digital filter unit 2 maintain the previous values.

Accordingly, the signals Ahf and Bhf passing through the filter unit 1 are applied to the internal circuit in the states Asf and Bsf that are determined to be stable inputs while passing through the digital filter unit 2.

In addition, the control signal generator 3 uses the output signals Asf and Bsf of the digital filter unit 2 to control signals UP / DOWN and COUNTER-EN through asynchronous simple combinational logic. ) At this time, since the simple combination type logic operates regardless of the system clock CLK, when the output signal Asf, Bsf of the digital filter unit 2 is applied at the rising point D of the system clock CLK, Generate control signal (UP / DOWN, COUNTER-EN) immediately.

The rotation amount counter 4 receives a control signal (UP / DOWN, CONUTER-EN) generated from the digital filter unit 2 at the falling point (e) of the system clock CLK to increase the counter value. Or reduce it. At this time, since the control signal (UP / DOWN, COUNTER-EN) is input from the digital filter unit (2) at the falling point (e) of the system clock (CLK), the speed control unit at the same time of the rotation amount counter (4) If the count value is read, the count value can be read when the operation of the rotation counter 4 is started. Therefore, in order to prevent this, the control signal COUNTER-EN at the rising point (bar) of the system clock CLK is prevented. Is maintained at '1', the speed controller allows the speed controller to read the count value of the revolution counter 4 so that the speed controller has completed the calculation at the rising point (bar) of the system clock CLK ( The actual counter value of 4) is input via the data bus, and the rotation amount counter 4 maintains the same output when there is no new input.

The above operation is always performed when the rising and falling points of the signals A and B output from the encoder occur, and the speed controller receives the generated counter value at a predetermined time interval, thereby returning the operation state of the motor. I can receive it.

On the other hand, each unit as described above is basically designed to operate in synchronization with the rising or falling point of the system clock (CLK). In this way, when the system is configured through synchronous logic, it is advantageous to calculate the timing relationship of each signal and the time for setup & holdup, and is particularly important when the information formed in the hardware logic is related to the data bus of the system.

However, in the conventional motor speed detecting device as described above, when a control signal is applied at the falling point (e) of the system clock, the rotation amount counter should output the correct output within a half period (rising point-bar) of the system clock. As can be seen from the 16-bit counter circuit of Fig. 2, when the bit value is changed from the lower bit to the upper bit by one input value, the processing time becomes longer.

In other words, for example, when the present value is 32767 (= 0X7FFF) and the next value is 32768 (= 0X8000), the count value must be passed after 15 flip-flops have been passed from 1 bit to 15 bits inside the revolution counter. Since the counting operation of the rotation amount counter is delayed, when the rising point (bar) of the system clock is reached in this situation, an unstable count value is output and the wrong speed information is input to the speed controller, thereby deteriorating the stability of the speed controller. In severe cases, abnormal behavior was caused.

In this case, the problem is solved by using an application-specific integrated circuit capable of high-speed processing or a high speed PLD or slowing down the system by lowering the performance of the system as a whole. The problem is inevitable.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to detect the rotational speed of a reliable motor using a low speed peripheral device while maintaining the performance of a system using a high speed CPI. It is to provide a motor speed detection device that can be.

1 is a block diagram of a conventional motor speed detection device.

2 is an exemplary view showing an example of a rotation amount counter in FIG.

3 is an input / output waveform diagram of each block in FIG.

4 is an exemplary diagram in which an embodiment of the present invention is blocked.

*** Explanation of symbols for main parts of drawing ***

1: filter unit 2: digital filter unit

3: control signal generator 11, 12: counter unit

13: Multiple selection

Motor speed detection apparatus for achieving the object of the present invention as described above comprises a filter for filtering the signals (A, B) input from the encoder; A digital filter for digitally filtering the output signal of the filter into stable data; A control signal generator which receives the output signal of the digital filter unit and generates a control signal for the rotation direction command of the motor and the rotation amount counter function operation of the motor; In response to the control signal of the control signal generator, a multi-selection unit is configured to select the outputs of the first and second counters that are increased and decreased, respectively, and output the new values by the feedback. Characterized in that the configuration.

Referring to the accompanying drawings of the motor speed detection apparatus according to the present invention as described above in detail as an embodiment as follows.

FIG. 4 is a block diagram illustrating an embodiment of the present invention. As shown therein, a filter unit 1 for removing noise components of signals A and B input from an encoder (not shown) through filtering is shown. ; A digital filter unit 2 for digitally filtering the output signals Ahf and Bhf of the filter unit 1 with stable data; Generates a control signal that receives the output signals Asf and Bsf of the digital filter unit 2 and generates a control signal (UP / DOWN, COUNTER-EN) for the motor rotation direction command and the motor rotation counter function. Part 3; According to the control signals (UP / DOWN, COUNTER-EN) of the control signal generator 3, the value outputted to the current speed controller through the data bus (DATA-BUS) is fed back and increased and decreased respectively to output a new value. It consists of a multi-selection unit 13 which selects the output signals of the counter units 11 and 12 and outputs them to the speed control unit through a data bus. It is a signal.

Hereinafter, the operation of the motor speed detection apparatus according to an embodiment of the present invention as described above will be described in detail.

Here, since the filter unit 1, the digital filter unit 2 and the control signal generator 3 operate in the same manner as in the prior art, detailed description thereof will be omitted.

First, the control signals UP / DOWN and COUNTER-EN output from the control signal generator 3 are output at the falling point e of the system clock CLK as shown in the waveform diagram of FIG. In this case, the counters 11 and 12 are configured with up and down counters of the same bit, and are predetermined by receiving a value input to the speed controller through the data bus DATA-BUS regardless of the system clock CLK. It is increasing and decreasing by logic to output new value.

In addition, the multi-selection unit 13 according to the control signal (UP / DOWN, COUNTER-EN) of the control signal generator 3 input from the falling point (e) of the system clock CLK (counter 11) Select the output of 12) and output it to the speed control part through the data bus at the rising point (bar) of the system clock CLK. This output value is fed back to the counter parts 11 and 12, and the system clock is returned. Regardless of CLK, new values that are increased or decreased are output from the counters 11 and 12.

Therefore, in response to the rising and falling points of the input signals A and B, the counters 11 and 12 have made count values before the rising and falling points of the input signals A and B occur. Since the multi selector 13 selects the outputs of the counters 11 and 12 and outputs them to the speed controller through the control signals UP / DOWN and COUNTER-EN applied from the signal generator 3, The final output takes only the selection time of the multiple selector 13.

In the present invention described above, the operation time of the counters 11 and 12 is irrelevant to the system clock CLK, but it is importantly influenced by the rising and falling points of the input signals A and B. That is, if the interval between the rising and falling points of the input signals A and B is longer than the operation time of the counters 11 and 12, the output value of the speed detector can maintain a stable state.

Even though the motor rotates very fast in a general system, the interval between the occurrence of the rising and falling points of the input signals A and B is very long compared to the system clock CLK. It becomes possible.

As described above, the motor speed detecting apparatus according to the present invention requires only the selection time of the multi-selection unit to detect the rotational speed of the motor, thereby preventing the reliability of the speed information and the malfunction of the system due to the operation delay of the conventional rotating amount counter. By doing so, it is possible to detect the rotational speed of the reliable motor by using the peripheral device of low speed while maintaining the performance of the system using the high speed CIE, thereby improving the system performance and reducing the cost.

Claims (2)

A filter unit for filtering signals A and B input from the encoder; A digital filter for digitally filtering the output signal of the filter into stable data; A control signal generator which receives the output signal of the digital filter unit and generates a control signal for the rotation direction command of the motor and the rotation amount counter function operation of the motor; In response to the control signal of the control signal generator, a multi-selection unit is configured to select the outputs of the first and second counters that are increased and decreased, respectively, and output the new values by the feedback. Motor speed detection device, characterized in that configured to. The motor speed detecting apparatus of claim 1, wherein the first and second counter units comprise up and down counters of the same bit.