KR20010015655A - Data processing device with means for counteracting analysis methods for the detection of a secret characteristic value - Google Patents

Abstract

A data processing device ( 1 ) which includes a circuit ( 2 ) with data processing means ( 17 ) which are suitable for processing data (DA) while utilizing a characteristic value (CV) and with sequencing means ( 15 ) which are arranged to execute an algorithm in order to control the data processing means ( 17 ) in conformity with this algorithm which comprises a given number N of sub-algorithms containing identical successions of algorithm steps, is additionally provided with order fixation means ( 29 ) which co-operate with the sequencing means ( 15 ) and whereby, each time when the algorithm is executed, an order can be fixed from a plurality of feasible orders for the execution of the N sub-algorithms.

Description

DATA PROCESSING DEVICE WITH MEANS FOR COUNTERACTING ANALYSIS METHODS FOR THE DETECTION OF A SECRET CHARACTERISTIC VALUE}

Data processing devices of the kind as described in the first paragraph and circuits of the kind as described in the second paragraph are used in various versions and include contact-types comprising integrated circuit components developed and marketed by the applicant. type) Well known from chip cards. In such known data processing apparatuses and also in known contact chip cards and in such known circuits and also in integrated circuit components which are also included in such contact type chip cards, the data processing means are formed by encryption means, which encryption The means performs an encryption operation on data applied to itself according to the "Data Encryption Standard (DES)" using a characteristic value applied to itself, that is, a secret key. During such encryption operation, a total of N = 8 so-called SBOX units are executed, and the SBOX results are calculated by each SBOX unit. All eight SBOX units are executed within the framework of the program constituting the algorithm, and each program block of the algorithm forms a sub-algorithm and corresponds to one SBOX unit. Each program block corresponding to one SBOX unit is characterized by an associated SBOX unit and contains a table containing entries. All SBOX unit entries are different. The table included in the SBOX unit or the entries in the table is used to determine the output data associated with the input data applied to the SBOX unit. However, the determination of output data related to such input data is performed using the same algorithm for linking input data and output data in all eight SBOX units, which represent each SBOX unit and each sub Each of the N program blocks constituting the algorithm is meant to include program instructions of the same sequence as algorithm steps. In a known data processing apparatus or known circuit, the N program blocks are executed invariably in the same order each time a program is executed.

During the execution of the encryption operation, a current peak pattern occurs in the area of the conductors configuration, which peak pattern is applied to program instructions, data processed by the encryption means, characteristic values used in the encryption means, i.e., the secret key of these encryption means. Depends. In a known data processing device or a known circuit, each current peak pattern so generated is also faced with a problem that arises in parts of the circuit or externally interrogated parts of the data processing device. do. The occurrence of each of the current peak patterns each time occurring in the portions supplies predetermined known data in an undefined number of times to perform the processing to the data processing means which processes the data using, for example, a characteristic value, and processing of this known data. It is used to ensure that the same current peak pattern thus generated is always under monitoring or detection, and therefore, it is detected using a correlation method or a comparison method in which the characteristic value used in the data processing means, that is, the encryption means, is complicated. It can be extracted from the current peak pattern. However, these methods are known and available methods.

Obviously, such a break of the secret key is undesirable because as a result the desired secret can no longer guarantee its authenticity.

The present invention includes a circuit composed of various circuit parts to which a supply voltage can be applied through the component parts of the conductors; A data processing means arranged to constitute a circuit to which a supply voltage can be applied, and to process data utilizing characteristic values; A data processing apparatus also comprising sequencing means configured to constitute a circuit to which a supply voltage can be applied, and to execute an algorithm to control the data processing means according to the algorithm, wherein the algorithm is an algorithm of the same sequence. And N number of sub-algorithms that can be executed in a predetermined order each time the algorithm is executed, and when processing data by the data processing means under the control of the sequencing means according to the algorithm. The processing causes a current peak pattern to be generated in the component area of the conductors, the pattern configuration of the current peak pattern being dependent on the algorithm steps, the processing data and the specific value.

The invention also consists of various circuit parts to which a supply voltage can be applied through the component parts of the conductors; Data processing means arranged to process data utilizing the characteristic value; The invention also relates to a circuit for a data processing apparatus comprising a sequencing means arranged to configure a circuit to which a supply voltage can be applied, and to execute an algorithm to control the data processing means according to the algorithm, wherein the algorithm is the same sequence. And N number of sub-algorithms which can be executed in a predetermined order every time the algorithm is executed, and when processing data by the data processing means under the control of the sequencing means according to the algorithm, The data processing causes a current peak pattern to be generated in the component area of the conductors, the pattern configuration of the current peak pattern being dependent on the algorithm steps, the processing data and the specific value.

It is an object of the present invention to avoid the above problems and to improve the data processing device or the circuit for an improved data processing device which can ensure a high degree of reliability in keeping the characteristic value secret through simple means and very few additional operations. Is to provide.

In order to achieve the above object, a data processing apparatus of the kind as described in the first paragraph according to the present invention further includes an order fixing means in which the circuit operates with the sequencing means, thereby executing each of the algorithms. At one time, one of a plurality of characteristic sequences for execution of the N sub-algorithms can be fixed.

Further, in order to achieve the above object, a circuit of the kind as described in the second paragraph according to the invention further comprises an order fixing means for operating with the sequencing means, whereby the algorithm One order of the plurality of executable sequences for execution of the N sub-algorithms may be fixed for each execution for.

By taking the steps according to the invention, the order of execution of the N sub-algorithms of an algorithm is determined even if all the algorithm steps in the series of all successively executed sub-algorithms are always the same during each execution of the algorithm. During each execution, the execution order of the N sub-algorithms cannot be determined from the data processing apparatus or the circuit outside of the data processing apparatus. Therefore, in order to use these peak patterns for analysis by the correlation method or the comparison method, it is difficult to compare the continuously generated current peak patterns generated by the continuous operation of the algorithm. Unwanted recognition or detection of a characteristic value, such as a secret key, used in data processing means such as a secret key, is in fact impossible or at least quite difficult.

The steps described in claims 2 and 3 or 7 and 8 of the claims are remarkable in their simplicity and the data processing device according to the invention or the data processing device according to the invention or the present invention. Since it can be easily carried out using the means already presented in the circuit according to the invention, it has proved to be very effective for the data processing according to the present invention or the circuit according to the present invention. With respect to the order selection means, it is noted that these order selection means preferably comprise only a part of all executable sequences for the execution of the N algorithms, but also for the execution of the N sub-algorithms in the order selection means. It is possible to simply provide all executable sequences.

The steps according to the invention are the data processing device according to claim 4 or the circuit claimed in claim 9 because of the very significant need to keep secrets in relation to the keys used in particular in the case of means for encrypting and / or decrypting data. It has been found to be particularly advantageous in

The data processing apparatus according to the present invention is formed of, for example, a computer or a personal computer arranged to execute encryption programs. The steps according to the invention have proven to be very suitable for a data processing device as described in claim 7 or a circuit as described in claim 14 because the risk of breaking characteristic values is particularly high in these cases.

These and other aspects of the invention will be apparent from the embodiments described below.

The present invention will be described in detail based on the embodiments as shown in the drawings, but not limited thereto.

Fig. 1 is a block diagram of an essential part of this relationship of the data processing apparatus in the first embodiment of the present invention.

2 shows three executions of the same program consisting of a total of N program blocks.

1 is a block diagram of a portion of a data processing apparatus formed by a data carrier 1 configured for wireless communication with a write / read station (not shown in FIG. 1 but provided for the purposes of this embodiment).

The data carrier 1 comprises a circuit 2 realized by the integration technique. The circuit 2 is composed of a plurality of circuit parts, which will be described in detail below. The circuit parts can be supplied with a supply voltage V through the component of the conductors 3, which supply voltage is a DC voltage. The generation of the supply voltage V will also be described in detail below.

The data carrier 1 comprises a receiver / transmitter means 4 comprising a transmitter coil 5. The receiver / transmitter means 4 is connected to the first connection part 6 and the second connection part 7 of the circuit 2. The transmitter coil 5 may be inductively coupled to a transmitting coil of a writing / reading station (not shown). These two transmitter coils cause an unmodulated carrier signal CS and an amplitude modulated carrier signal CSM whose amplitude is modulated in accordance with the data DA to be transmitted from the write / read station to the data carrier 1. In addition, the two transmitter coils have a load modulating carrier means (CSB) which can be generated by a load modulating means (not shown in FIG. 1) of the data carrier 1 or a circuit 2 of the data carrier 1. It is to be transmitted between two communication parties, namely the writing / reading station and the data carrier 1, thereby allowing the data to be transmitted from the data carrier 1 to the writing / reading station. The above are functions that have been known for a long time.

The supply voltage V is supplied by the unmodulated carrier signal CS transmitted from the write / read station to the data carrier 1 and the amplitude modulated carrier signal (CSM) transmitted from the write / read station to the data carrier 1. Can be obtained in 1). For this purpose, the unmodulated carrier signal CS and the amplitude modulated carrier signal CSM received by the receiver / transmitter means 4 are electrically connected to the first connection 6 and the first connection 6. It is applied to the supply voltage generating means 9 via the connecting portion (8). The supply voltage generating means 9 essentially consists of a rectifier stage and a voltage limiting means which prevents storage capacitors and unwanted overvoltages. The supply voltage generating means 9 can generate the aforementioned supply voltage V which can be output to the component part of the conductors 3 via the output 10 of the supply voltage generating means 9. The generated supply voltage V can be applied to various circuit parts of the circuit 2 via the component parts of the conductors 3. It is noted that the configuration of such conductors 3 may also include a conductive ground connection (not shown in FIG. 1 for the sake of brevity).

The data carrier 1 or the circuit 2 comprises a first data processing means 11 to which a supply voltage V can be applied via a supply input 12. In addition, the amplitude modulation carrier signal (CSM) output by the receiver / transmitter means 4 can be supplied to the first data processing means 11 via the connection portion 3A. The load modulated carrier signal CSB is obtained at the receiver / transmitter means 4 by the first data processing means 11 via another connection 13B connected to the second connection 7. In addition, the first BUS connection 14 connected to the sequencing means 15 is connected to the first data processing means 11. The sequencing means 15 are arranged to execute the first algorithm, thereby controlling the first data processing means 11 in accordance with the first algorithm.

The first data processing means 11 comprises demodulation means (not shown), so that the applied amplitude modulated carrier signal CSM can be demodulated. After demodulation of such an amplitude modulated carrier signal (CSM), the demodulated signal can be decoded if necessary. If necessary, additional processing operations may also be performed. After the execution of all processing operations, the first data processing means 11 outputs the data DA via the second BUS connecting portion 16 connected to the second data processing means 17.

The second data processing means 17 is arranged to process the data DA using the characteristic value CV. In this case, the second data processing means 17 is formed as a means for encrypting / decrypting data, and the secret key necessary for encryption and decryption is formed with the aforementioned characteristic value CV.

The second data processing means 17 includes a supply input 18, through which the supply voltage V can be supplied to the second data processing means 17. In addition, a third BUS connector 19 is connected to the second data processing means 17, the other end of which is connected to the sequencing means 15. The sequencing means 15 are also arranged to execute the second algorithm to control the second data processing means 17 in accordance with the second algorithm.

In the present embodiment for the data carrier 1 of FIG. 1, the circuit 2 comprises program storage means 20 operating with sequencing means 15, in which a second algorithm is used for the program P. Is stored in the form. The second algorithm, that is, the program P, includes, in this example, a predetermined number of N sub-algorithms formed of N program blocks PB1, PB2, PB3 ... PBN. This sub-algorithm formed of the program blocks PB1 to PBN includes the same series of algorithm steps formed by the program instructions CO1, CO2, CO3 ... COR in this example. N sub-algorithms, or N program blocks, may be executed in a predetermined order during each execution of the algorithm, i.e., program P, as will be described in detail below. The program storing means 20 is connected to the sequencing means 15 via a fourth BUS connecting portion 21, so that the interaction between the program storing means 20 and the sequencing means 15 is connected to the fourth BUS connecting portion 21. It is possible through. The program storage means 20 includes a supply input 22 through which the supply voltage V can be applied to the program storage means 20.

The circuit 2 also comprises a storage means 23 consisting of a data storage 24 and a characteristic value storage 25. The characteristic value storage section 25 is arranged to store the characteristic value CV. The storage means 23 includes a supply input 26 through which the supply voltage V can be applied to the storage means 23. The fifth BUS connector 27 is connected to the storage means 23, the other end of which is connected to the second data processing means 17. The bidirectional transmission between the second data processing means 17 and the storage means 23 and the transfer of the characteristic value CV from the storage means 23 to the second data processing means 17 are carried out by the fifth BUS connection 27. Can occur through As indicated by dashed lines in FIG. 1, a separate BUS connection 28 is provided between the characteristic value storage 25 and the second data processing means 17, which is connected to the characteristic value storage 25. ) And at least one characteristic value CV between the second data processing means 17.

The data DA applied from the first data processing means 11 to the second data processing means 17 via the second BUS connecting portion 16 is encrypted through an encryption operation process in the second data processing means 17. do. In the case of such an encryption operation, the generated encrypted data DA is applied to the data storage 24 of the storage means 23 via the fifth BUS connection 27 and stored there.

The data DA applied to the second data processing means 17 through the BUS connecting portion 27 and read from the data storage 24 of the storage means 23 is transferred from the second data processing means 17. The encrypted data DA can be encrypted during further encryption operations, which are then applied to the first data processing means 11 via the second BUS connection 16 for further processing there, and then finally encrypted. The load modulation is carried out via the connection 13B in accordance with the data DA, so that the load modulated carrier signal CSB is generated at the receiver / transmitter means 4.

Sequencing means 15 controls second data processing means 17 during the execution of the encryption operation. That is, the sequencing means 15 continuously reads the program instructions CO1 and CO2 from the program P stored in the program storage means 20 via the fourth BUS connecting portion 21, and then writes to the individual read program instructions. The corresponding processing step is executed in the second data processing means 17. During the processing of the data DA as described above by the second data processing means 17 under the control of the sequencing means 15 according to the program P stored in the program storage means 20, the conductor ( A current peak pattern is generated in the component region of 3). The pattern configuration of the current peak pattern then becomes dependent on the program instructions CO1, CO2 ... COR, the processed data DA, and the characteristic value CV.

The data carrier 1, or the circuit 2, is preferably a program stored in the program storage means 20, including an additional order lock means 29 in which the circuit 2 operates in conjunction with the sequencing means 15. When each of the formed algorithms is executed, one of the plurality of executable sequences for execution of the N sub-algorithms, that is, the N program blocks PB1, PB2... PBN, is configured to be fixed.

In this embodiment, the order fixing means 29 comprises an arbitrary number generator 30. The random number generator 30 includes a supply voltage input unit 31 through which the supply voltage V can be applied to the random number generator 30. The random number generator 30 is connected to the sequencing means 15 via a sixth BUS connection 32. Accordingly, each random number Z generated by the random number generator 30 can be applied to the sequencing means 15 via the sixth BUS connection 32. The order fixing means 29 including the random number generator 30 is executed by the random number Z generated by the random number generator 30 when executing the program P stored in the program storage means 20. It is determined and the order used to execute the N program blocks PB1 to PBN of the program P can be fixed.

For this reason, the order fixing means 29 also includes an order selecting means 33 included in the sequencing means 15. The order selecting means 33 comprises executable sequences for executing the N program blocks PB1 to PBN of the program P. FIG. Preferably, the order selection means 33 comprises only some of all executable orders. The order selection means 3 operates in conjunction with the random number generator 30. That is, the order selecting means 33 orders the order from the executable orders contained in the order selecting means 33 according to the random number Z received from the random number generator 30 via the sixth BUS connection 32. You can choose.

The first data processing means 11, the sequencing means 15, the second data processing means 17, the program storage means 20, the storage means 23 and the random number generator 30 are each of the circuit 2. And a supply voltage (V) is supplied to each part of this circuit by the component part of the conductor (3).

In the processing of the data DA by the second data processing means 17 and under the control of the sequencing means 15 according to the program P, the calculation of each of the data carrier 1 and the circuit 2 is shown in FIG. 2. The program blocks of PB1 to PBN will be described in detail below.

Second data configured to process the data DA using the characteristic value CV during the processing of the data in the data carrier 1 or during the processing of the data by the circuit 2 of the data carrier 1. Assume that the processing means 17 is continuously activated for three data processing cycles indicated by reference numerals RUN1, RUN2 and RUN3 in FIG. Before the first data processing period RUN1 of the second data processing means 17 reaches the middle of the data processing operation, the random number generator 30 is activated in an unexplained manner, and then the random number generator 30 Generates an arbitrary number Z1 which is applied to the order selection means 33 via the sixth BUS connection 32. Then, the order selecting means 33 executes the order of execution of the N program blocks PB1 to PBN of the program P, for example, according to the random number Z1 received from the random number generator 30. Select the order of (PB1, PB2, PB4, PB6, PB3, ... PB5 and PBN) as shown in the left column of 2. Thereafter, the program blocks PB1 to PBN are executed in the order described. All program instructions (CO1, CO2, ... COR, CO1, CO2, ... COR), etc. included in the program blocks are executed, which are consecutive program instructions. It means that (CO1, CO2 to COR) are executed N consecutive times in total as shown in the right column of FIG.

When the second data processing period RUN2 is executed during the data processing operation, the first random number generator 30 is activated again, and as a result, the random number generator 30 outputs the second random number Z2. The second random number Z2 is applied to the order selecting means 33 via the sixth BUS connecting portion 32, and the order selecting means 33 is arranged in a different order, for example as shown in the second column of FIG. The order of PB3, PB7, PBN, PB1, ... PB4 and PB2) is selected. Thus, the second data processing period RUN2 includes a completely different order of executing the N program blocks. However, the order of the program instructions CO1, CO2 to COR, etc. are still the same.

When the third data processing cycle RUN3 is executed in the middle of the assumed data processing operation, the random number generator 30 is activated again in the same manner as described above, so that the random number generator 30 is random number Z3. And then apply it to the sequencing means 15 or the order selection means 33 included in the sequencing means 15 via the sixth BUS connection 32. As a result, the order selecting means 33 performs another order of execution of the N program blocks PB1 to PBN, for example (PBN, PB1, PB4, PB6, PB3, .. as shown in the third column of FIG. Select the order of .PB7 and PB2). Thus, the third data processing period RUN3 also includes a new order for executing the N program blocks PB1 to PBN of the program P, while the order of the program instructions CO1, CO2 to COR is Still the same.

As will be apparent from the above description, in the circuit 2 of the data carrier or data carrier 1 shown in Fig. 1, the order of all program instructions COX of all program blocks PBX executed in succession. Although is the same for each program P execution, it can be seen that the execution order of the N program blocks PBX of the program P is different during execution of the program. Thus, it was found that the execution order of the N program blocks PBX of the program P cannot be detected from the outside of the data carrier 1 or the circuit 2 of the data carrier 1. As a result, it is also impossible to compare the successive orders of the current peak patterns to use these orders in the analysis using the correlation method, or to use the order of occurrence of the N current peak patterns, the N current peaks. One of the patterns occurs for the comparison method when executing each program block (PBX). Thus, it was found that undesirable detection or recognition of the characteristic value CV used in the second data processing means 17 is substantially impossible.

Another embodiment of the data carrier (not shown) has a wired logic circuit instead of the program storage means 20; This wire logic circuit works with the sequencing means 15 and comprises a wire algorithm, ie a hardware algorithm. This algorithm, ie the hardware stored in the wire logic circuit, is capable of analog control of the second data processing means 17 by the sequencing means 15.

The invention is not limited to the data processing apparatus, i.e., the data carrier 1 shown and described in connection with FIG. In the data carrier 1 shown in FIG. 1, the order selecting means 33 is configured to form part of the sequencing means 15, the order selecting means 33, implemented in hardware. In another embodiment of the data processing according to the present invention (not shown), the order selection means 33 may also be executed by a selection program, which is part of the program P stored in the program storage means 20. To form. The random order generator 30 operates directly with the second data processing means 17 via the BUS connection. Further, note that in the case of the data carrier 1 illustrated in FIG. 1, the program P stored in the program storage means 20 forms part of a larger program. Note that in the continuous program blocks PB1 to PBN illustrated in FIG. 2, the program blocks do not need to be executed immediately immediately. It is also possible to execute part of another program between the execution of two consecutive program blocks (PB).

Claims (14)

A circuit 2 composed of various circuit parts 11, 15, 17, 20, 23, 30 to which a supply voltage V can be applied through the component part of the conductors 3; Comprise such a circuit to which the supply voltage V can be applied, and comprising data processing means 17 arranged to process data DA utilizing the characteristic value CV; It also constitutes such a circuit to which the supply voltage V can be applied, and also performs sequencing means 15 arranged to execute an algorithm P to control the data processing means 17 according to this algorithm P. The algorithm (P) comprises a predetermined sequence of algorithm steps (CO1, CO2, ... COR) and includes a predetermined number of N subs that can be executed in a predetermined order each time the algorithm (P) is executed. Algorithm PB1, PB2, ... PBN, and when processing the data DA by the data processing means 17 under the control of the sequencing means 15 according to the algorithm P, The data processing causes a current peak pattern to be generated in the region of the components of the conductors 3, and the pattern configuration of the current peak pattern comprises the algorithm steps CO1, CO2, ... COR, the processing data DA And the data value device which depends on the characteristic value CV. As (1), The circuit (2) further comprises an order fixing means (29) for operating with the sequencing means (15), whereby the N sub-algorithms (PB1, PB2,... One of a plurality of executable sequences for execution of .PBN) is fixed. The method of claim 1, The order lock means 29 comprises a random number generator 30 and the N sub-algorithms PB1, PB2, ... PBN are executed by the order lock means 29 in each execution of the algorithm P. The order for execution is fixed, said order being defined by a random number (Z1, Z2, Z3) generated by said random number generator (30). The method of claim 2, The order lock means 29 comprises an order of execution for executing the N sub-algorithms PB1, PB2, ... PBN and operates with the random number generator 30. Further comprising the order selection means 33 selecting one order among the executable orders according to the random numbers Z1, Z2, Z3 received from the number generator 30. Device. The method of claim 1, A storage means 20 is provided which operates in conjunction with the sequencing means 15, wherein the algorithm P is a sub-algorithm PB1, PB2, comprising program instructions as an algorithm step CO1, CO2, ... COR. ... PBN) is stored in the form of a program comprising N program blocks. The method of claim 1, And a wire logic circuit operating in conjunction with said sequencing means and including said algorithm in wire form and thereby in hardware form. The method of claim 1, The data processing apparatus (1) is characterized in that the circuit (2) thereof is formed of a data carrier constituted by integration technology. The method of claim 1, The data processing apparatus characterized in that the data processing apparatus (1) is formed of a data carrier whose circuit (2) is constituted by integration technology. Consisting of various circuit parts 11, 15, 17, 20, 23, 30 to which a supply voltage V can be applied through the component part of the conductors 3; Data processing means 17 arranged to process the data DA utilizing the characteristic value CV; It also constitutes such a circuit portion to which the supply voltage V can be applied, and also performs sequencing means 15 arranged to execute the algorithm P to control the data processing means 17 according to this algorithm P. The algorithm (P) comprises N steps of algorithms (CO1, CO2, ... COR) of the same sequence and each time the algorithm (P) is executed, N number of sub-algorithms ( PB1, PB2, ... PBN), when processing the data DA by the data processing means 17 under the control of the sequencing means 15 according to the algorithm (P), the data processing Causes a current peak pattern to be generated in the component region of the conductors 3, and the pattern configuration of the current peak pattern comprises the algorithm steps CO1, CO2, ... COR, the process data DA and Data processing field that depends on the characteristic value CV As the circuit 2 for the teeth 1, The circuit (2) further comprises an order fixing means (29) for operating with the sequencing means (15), whereby the N sub-algorithms (PB1, PB2,... One of a plurality of executable sequences for execution of .PBN) is fixed. The method of claim 8, The order lock means 29 comprises a random number generator 30, and the order lock means 29 comprises N sub-algorithms generated by the random number generator 30 when the algorithms P are each executed. (PB1, PB2, ... PBN) A circuit for a data processing apparatus, characterized in that the order for executing the arbitrary numbers (Z1, Z2, Z3) is fixed. The method of claim 9, The order fixing means 29 comprises executable sequences for executing the N sub-algorithms PB1, PB2, ... PBN, and the order selecting means 33 working with the random number generator 30. ), And the order selection means 33 can select one of the executable orders according to the random numbers Z1, Z2, Z3 received from the random number generator 30. Circuit for data processing apparatus to be. The method of claim 8, Storage means 20, the storage means 20 operating together with the sequencing means 15, in which the algorithm comprises algorithm steps CO1, CO2 ... COR and And stored in the form of a program comprising N program blocks such as sub-algorithms (PB1, PB2, ... PBN) containing the same instruction. The method of claim 8, And a wire logic circuit operating in conjunction with said sequencing means, said wire algorithm comprising a wire algorithm and in hardware form. The method of claim 8, And said data processing means (17) comprise data encryption and / or decryption means. The method of claim 8, The circuit (2) is for a data processing device (1) consisting of data carriers, and the circuit (2) is configured for an integrated technology.