KR20010008583A - Method of forming metal-gate electrode in semiconductor device - Google Patents

Method of forming metal-gate electrode in semiconductor device Download PDF

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KR20010008583A
KR20010008583A KR1019990026500A KR19990026500A KR20010008583A KR 20010008583 A KR20010008583 A KR 20010008583A KR 1019990026500 A KR1019990026500 A KR 1019990026500A KR 19990026500 A KR19990026500 A KR 19990026500A KR 20010008583 A KR20010008583 A KR 20010008583A
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gate electrode
silicon nitride
tungsten
doped polysilicon
forming
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KR1019990026500A
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Korean (ko)
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박상욱
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김영환
현대전자산업 주식회사
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Publication of KR20010008583A publication Critical patent/KR20010008583A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Abstract

PURPOSE: A metal gate electrode formation method is provided to be capable of prohibiting a salicidation reaction while preventing diffusion of F and H ions into a silicon nitride film, by forming a silicon nitride film of about 20 - 30 angstrom on the surface of doped polysilicon at room temperature. CONSTITUTION: A metal gate electrode formation method includes sequentially forming a gate insulating film(102) and a doped polysilicon layer(104) on a semiconductor substrate(100). RF N2 plasma process is performed in the same chamber so that they can react with doped silicon, thus forming a thin silicon nitride film(106), on the doped polysilicon layer, for preventing compound generated by means of diffusion of ions within a tungsten film(108) to be formed later and a salicidation reaction. Tungsten of a high melting point is deposited on the thin silicon nitride film. Next, the stacked tungsten layer, the thin silicon nitride film and the polysilicon layer are patterned to form a gate electrode(G).

Description

반도체소자의 금속 게이트전극 형성방법{Method of forming metal-gate electrode in semiconductor device}Method of forming metal gate electrode in semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 고집적화 및 고속화에 적용할 수 있도록 도프트 폴리실리콘 상부에 고융점 금속으로서 텅스텐층을 형성하는 반도체소자의 금속 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a metal gate electrode of a semiconductor device in which a tungsten layer is formed as a high melting point metal on a doped polysilicon to be applied to high integration and high speed of a semiconductor device. .

대개 반도체소자의 게이트전극은 도프트 폴리실리콘을 사용하여 도전성을 갖고 있는데, 반도체 장치의 고집적도에 따라 디자인룰이 작아질 경우 폴리실리콘의 높은 비저항으로 인해 면저항이 증가하게 된다. 그러면, 게이트전극의 면저항이 증가하면 집적회로 내에서 신호 전송 시간이 지연되어 소자의 동작속도 향상에 문제가 된다.In general, the gate electrode of the semiconductor device is conductive by using doped polysilicon. When the design rule decreases according to the high density of the semiconductor device, the sheet resistance increases due to the high specific resistance of the polysilicon. Then, when the sheet resistance of the gate electrode is increased, the signal transmission time is delayed in the integrated circuit, which causes a problem in improving the operation speed of the device.

이러한 문제점을 해결하기 위하여, 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 안정한 텅스텐(W), 티타늄(Ti), 코발트(Co) 등의 고융점 금속을 추가하여 게이트 전극을 형성하고 있다.To solve this problem, a gate electrode is formed by adding high melting point metals such as tungsten (W), titanium (Ti), and cobalt (Co) that have low specific resistance and stable at high temperature as a gate electrode material. .

도 1은 종래 기술에 의한 텅스텐 게이트전극의 형성방법을 설명하기 위한 수직 단면도로서, 이를 참조하여 텅스텐의 게이트전극 제조 공정을 설명하고자 한다.1 is a vertical cross-sectional view for explaining a method of forming a tungsten gate electrode according to the prior art, with reference to this will be described the gate electrode manufacturing process of tungsten.

우선, 반도체 기판으로서 실리콘기판(10)에 게이트 절연막(12)을 형성하고, 그 상부에 도프트 폴리실리콘층(14)을 형성한다. 그리고, 상기 도프트 폴리실리콘층(14) 상부에 텅스텐을 증착하여 텅스텐층(16)을 형성한다.First, a gate insulating film 12 is formed on a silicon substrate 10 as a semiconductor substrate, and a doped polysilicon layer 14 is formed thereon. The tungsten layer 16 is formed by depositing tungsten on the doped polysilicon layer 14.

그리고, 게이트 마스크를 이용한 포토리소그래피 공정을 실시하여 순차 적층된 텅스텐층(16)과 도프트 폴리실리콘층(14) 및 게이트 절연막(12)을 패터닝하여 게이트전극(G)을 형성한다.Then, a photolithography process using a gate mask is performed to pattern the tungsten layer 16, the doped polysilicon layer 14, and the gate insulating layer 12 that are sequentially stacked to form a gate electrode G.

상기 텅스텐(16)의 증착 공정시 텅스텐은 WF6를 H2로 환원시켜 증착되기 때문에 각각 1019∼1020atoms/㎤과 1021∼1023atoms/㎤의 농도로 F과 H가 텅스텐층 내에 함유된다. 텅스텐막(16) 내에 함유된 불소(F)와 수소(H) 원자는 후속 열공정 진행시 게이트 절연막 쪽으로 확산하여 그 두께를 증가시키거나 도프트 폴리실리콘층과 게이트 절연막 계면에 고정 전하 집중(fixed charge center)현상을 발생하여 GOI(Gate Oxide Integrity) 특성을 저하시킨다.In the deposition process of tungsten 16, tungsten is deposited by reducing WF 6 to H 2 , so that F and H are in the tungsten layer at concentrations of 10 19 to 10 20 atoms / cm 3 and 10 21 to 10 23 atoms / cm 3, respectively. It is contained. The fluorine (F) and hydrogen (H) atoms contained in the tungsten film 16 diffuse to the gate insulating film in the subsequent thermal process to increase its thickness or to fix fixed charges at the doped polysilicon layer and the gate insulating film interface. charge center phenomena occur to reduce GOI (Gate Oxide Integrity) characteristics.

또한, 텅스텐막(16)과 도프트 폴리실리콘막(14)의 계면에서 확산반응에 의해 살리시데이션(salicidation) 반응이 일어나서 도 1의 ⓒ에서와 같이 W2Si, WSi2, WSi 등의 실리사이드(silicide) 물질이 생성된다. 이로 인하여, 게이트전극의 비저항이 변화하게 되어 트랜지스터의 전기적인 특성이 변화하게 된다.In addition, a salicidation reaction occurs at the interface between the tungsten film 16 and the doped polysilicon film 14 by a diffusion reaction. As shown in ⓒ of FIG. 1, silicides such as W 2 Si, WSi 2 , and WSi ( silicide) material is produced. As a result, the specific resistance of the gate electrode is changed to change the electrical characteristics of the transistor.

이러한 텅스텐 금속을 갖는 게이트전극의 전기적 특성 개선을 위하여 F, H의 이온 확산과 살리시데이션 반응을 억제할 수 있는 전도성 확산방지막이 요구되고 있다. 이때, 전도성 확산방지막의 조건은 첫째, 열적 안정성이 있으면서 텅스텐과 도프트 폴리실리콘과의 반응성이 적으며, 둘째, 텅스텐과 도프트 폴리실리콘과의 일함수 차가 적어 플랫 밴드(flat band) 변화를 유발시키지 않으며, 셋째, 전기전도도가 커야한다.In order to improve the electrical characteristics of the gate electrode having such a tungsten metal, there is a need for a conductive diffusion barrier that can suppress ion diffusion and salicide reactions of F and H. At this time, the conditions of the conductive diffusion barrier are first, thermal stability and less reactivity between tungsten and doped polysilicon, and second, due to the small work function difference between tungsten and doped polysilicon causes a flat band change Third, the electrical conductivity must be large.

이러한 조건을 만족하는 물질은 티타늄질화막(TiN), 텅스텐질화막(WN) 및 실리콘질화막(SiN)등이 있다. 티타늄질화막은 티타늄과 도프트 폴리실리콘간의 반응성 때문에 티타늄실리사이드 현상을 발생하므로 이를 사용하는데 한계가 있으며, 텅스텐 질화막의 경우에는 게이트 식각 공정시 텅스텐과 도프트 폴리실리콘사이의 식각 선택비 차이에 따라 식각 공정의 마진을 확보하는데 어려움이 있었다.Materials satisfying these conditions include a titanium nitride film (TiN), a tungsten nitride film (WN), and a silicon nitride film (SiN). Titanium nitride has a limitation in using titanium silicide due to the reactivity between titanium and doped polysilicon, and in the case of tungsten nitride, the etching process depends on the difference in etching selectivity between tungsten and doped polysilicon during the gate etching process. Had difficulty securing margins.

이를 위해서 텅스텐 금속의 게이트 전극의 제조 공정시 도프트 폴리실리콘층 상부에 전도성 확산방지막으로서 실리콘질화막(SiN)을 이용하게 되었다. 이 실리콘질화막 공정은 통상적으로 실리콘(Si)을 증착하고 N2O 분위기에서 어닐링을 실시하거나 NH3플라즈마 질화처리 또는 N+이온을 주입하는 방법들을 사용하였다.To this end, a silicon nitride film (SiN) is used as a conductive diffusion barrier on the doped polysilicon layer during the manufacturing process of the tungsten metal gate electrode. This silicon nitride film process typically used a method of depositing silicon (Si), annealing in an N 2 O atmosphere, or NH 3 plasma nitridation or implanting N + ions.

그러나, N2O분위기 어닐링과 NH3플라즈마 질화처리법의 경우에는 고온에서 복합형 기체를 사용함에 따라 제조 공정이 복잡하며 도프트 폴리실리콘내 도펀트 농도분포가 변화되는 써멀 버젯(thermal budget)에 의한 문제점이 수반된다. 그리고, N+이온 주입법의 경우에는 결함이 다수 포함된 실리콘질화막이 종종 형성되어 확산방지기능과 식각 특성이 저하된다.However, in the case of N 2 O atmosphere annealing and NH 3 plasma nitridation, a complex gas is used at high temperature, which makes the manufacturing process complicated and a problem due to a thermal budget in which the dopant concentration distribution in the doped polysilicon is changed. This is accompanied by. In addition, in the case of N + ion implantation, a silicon nitride film including many defects is often formed, and the diffusion preventing function and the etching characteristics are deteriorated.

또한, 0.15㎛ 디자인 룰 이하의 텅스텐 구조의 게이트전극에 있어서, 이러한 실리콘질화막의 두께가 약 30Å보다 두꺼울 경우 그 막 자체의 유전특성에 기인된 플랫 밴드(flat band) 및 일함수(work function) 등의 변화가 발생하게 되어 결과적으로 트랜지스터의 전기적 특성 및 GOI특성이 열화된다.In addition, in a tungsten-structured gate electrode having a design rule of 0.15 탆 or less, when the thickness of the silicon nitride film is thicker than about 30 mW, a flat band due to the dielectric properties of the film itself, a work function, etc. Change occurs, resulting in deterioration of the transistor's electrical and GOI characteristics.

본 발명의 목적은 상기한 종래기술의 문제점을 해결하기 위하여 텅스텐 금속의 게이트전극의 텅스텐과 도프트 폴리실리콘층 사이에 확산 방지 및 살리시데이션 반응 억제용 실리콘질화막을 형성할 때 상온에서 RF N2플라즈마 공정을 실시하여 도프트 폴리실리콘 표면에 결정상태가 우수한 실리콘질화막을 30Å이하로 형성시킴으로써 제조 공정이 단순하면서도 GOI 및 트랜지스터의 전기적인 특성을 개선할 수 있는 반도체소자의 금속 게이트전극 형성방법을 제공하는데 있다.An object of the present invention is to solve the above problems of the prior art RF N 2 plasma at room temperature when forming a silicon nitride film for preventing diffusion and salicide reaction between the tungsten and the doped polysilicon layer of the gate electrode of tungsten metal By forming a silicon nitride film having excellent crystal state on the doped polysilicon surface of 30 Å or less by carrying out the process, it provides a method of forming a metal gate electrode of a semiconductor device that can simplify the manufacturing process and improve the electrical characteristics of GOI and transistor. have.

도 1은 종래 기술에 의한 텅스텐 게이트전극의 형성방법을 설명하기 위한 수직 단면도,1 is a vertical cross-sectional view for explaining a method of forming a tungsten gate electrode according to the prior art,

도 2는 본 발명에 따른 텅스텐 게이트전극의 구조를 나타낸 수직단면도,2 is a vertical sectional view showing a structure of a tungsten gate electrode according to the present invention;

도 3a 내지 도 3e는 도 2에 도시된 텅스텐 게이트전극의 제조 공정을 나타낸 공정 순서도.3A to 3E are process flowcharts illustrating a manufacturing process of the tungsten gate electrode illustrated in FIG. 2.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100: 실리콘기판 102: 게이트 절연막100: silicon substrate 102: gate insulating film

104: 도프트 폴리실리콘층 106: 실리콘질화박막104: doped polysilicon layer 106: silicon nitride thin film

108: 텅스텐층108: tungsten layer

G: 게이트전극G: gate electrode

상기 목적을 달성하기 위하여 본 발명은 게이트 절연막이 형성된 반도체 기판 상부에 도프트 폴리실리콘층과 텅스텐층이 적층된 게이트전극을 형성함에 있어서, 반도체기판 상부에 게이트 절연막, 도프트 폴리실리콘층을 순차적으로 형성하는 단계와, 도프트 폴리실리콘층 상부에 동일 챔버에서 RF N2플라즈마 공정을 실시하여 도프트 폴리실리콘과 반응시켜 이후 형성될 텅스텐막내의 이온 확산과 살리시데이션 반응에 의해 생성되는 화합물을 방지하는 실리콘질화박막을 형성하는 단계와, 실리콘질화박막 상부에 고융점의 텅스텐을 증착하여 텅스텐층을 형성하는 단계와, 적층된 텅스텐층, 실리콘질화박막 및 폴리실리콘층을 패터닝하여 반도체소자의 게이트전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention forms a gate electrode in which a doped polysilicon layer and a tungsten layer are stacked on a semiconductor substrate on which a gate insulating film is formed, and sequentially forms a gate insulating film and a doped polysilicon layer on a semiconductor substrate. Forming and performing an RF N 2 plasma process on the doped polysilicon layer in the same chamber to react with the doped polysilicon to prevent a compound produced by ion diffusion and salicide reaction in the tungsten film to be formed subsequently. Forming a silicon nitride thin film, depositing a high melting point tungsten on the silicon nitride thin film to form a tungsten layer, and patterning the stacked tungsten layer, silicon nitride thin film and polysilicon layer to form a gate electrode of the semiconductor device. It characterized by comprising the step of forming.

본 발명에 따르면, 텅스텐 금속 게이트 제조 공정시 도프트 폴리실리콘 증착 공정의 후속 처리로서 RF N2플라즈마 질화처리 공정에 의해 약 20∼30Å의 실리콘질화박막을 상온에서 도프트 폴리실리콘의 표면에 형성하여 실리콘질화막의 F 및 H 이온에 대한 확산 방지기능과 살리시데이션 반응의 억제 기능에 의해 GOI 및 트랜지스터의 전기적 특성을 개선한다.According to the present invention, a silicon nitride thin film of about 20 to 30 microseconds is formed on the surface of the doped polysilicon at room temperature by an RF N 2 plasma nitridation process as a subsequent treatment of the doped polysilicon deposition process in the tungsten metal gate manufacturing process. The electrical properties of the GOI and the transistor are improved by the diffusion preventing function of the silicon nitride film and the suppression of the salicide reaction to the F and H ions.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 텅스텐 게이트전극의 구조를 나타낸 수직단면도로서, 본 발명은 반도체기판으로서 실리콘기판(100) 상부에 형성된 게이트 절연막(102)과, 그 위에 순차적으로 적층된 도프트 폴리실리콘층(104) 및 텅스텐층(108)으로 구성된 게이트 전극에 있어서, 상기 도포트 폴리실리콘층(104)과 텅스텐층(108) 사이에 도전성 이온의 확산을 방지하면서 살리시데이션 반응을 억제하고자 RF N2플라즈마 질화처리 공정에 의해 약 20∼30Å 두께로 형성된 실리콘질화박막(106)을 포함하고 있다.2 is a vertical cross-sectional view showing a structure of a tungsten gate electrode according to the present invention, the present invention is a semiconductor insulating film 102 formed on the silicon substrate 100 as a semiconductor substrate, and a doped polysilicon layer sequentially stacked thereon A gate electrode composed of a 104 and a tungsten layer 108, an RF N 2 plasma for suppressing the salicide reaction while preventing diffusion of conductive ions between the doped polysilicon layer 104 and the tungsten layer 108. The silicon nitride thin film 106 formed by the nitriding process is about 20-30 micrometers in thickness.

도 3a 내지 도 3e는 도 2에 도시된 텅스텐 게이트전극의 제조 공정을 나타낸 공정 순서도로서, 이를 참조하면 본 발명의 텅스텐 게이트전극의 형성 방법은 다음과 같다.3A to 3E are process flowcharts illustrating a manufacturing process of the tungsten gate electrode shown in FIG. 2. Referring to this, a method of forming a tungsten gate electrode according to the present invention is as follows.

우선, 도 3a에 도시된 바와 같이 실리콘기판(100)에 게이트 절연막(102)을 50Å∼100Å 두께로 형성하고, 그 상부에 도프트 폴리실리콘층(104)을 500Å∼1000Å 두께로 형성한다. 이때, 도프트 폴리실리콘층(104)은 반응기체로 SiH4를 사용하고 도펀트로서 PH3을 사용하여 각각 1.1:1.5 ∼ 1.5:1.8의 혼합비로 사용하여 500℃∼700℃ 온도에서의 CVD(chemical vapor deposition) 방법을 이용한다.First, as shown in FIG. 3A, the gate insulating film 102 is formed on the silicon substrate 100 to have a thickness of 50 μs to 100 μs, and a doped polysilicon layer 104 is formed on the silicon substrate 100 to a thickness of 500 μs to 1000 μs. At this time, the doped polysilicon layer 104 is a CVD (chemical) at a temperature of 500 ℃ to 700 ℃ using a mixture ratio of 1.1: 1.5 to 1.5: 1.8 using SiH 4 as a reactor and PH 3 as a dopant vapor deposition) method.

도 3b에 도시된 바와 같이, N+ 이온과 실리콘간의 반응성을 촉진하기 위하여 인-시튜(in-situ) 공정으로 Ar 플라즈마 공정을 실시하여 상기 도프트 폴리실리콘층(104)의 표면을 활성화한다. 이때, 플라즈마 안정성을 확보하기 위한 공정 압력과 유속은 각각 3∼8mTorr, 10∼30sccm으로 하는 것이 바람직하다.As shown in FIG. 3B, an Ar plasma process is performed in an in-situ process to activate the surface of the doped polysilicon layer 104 to promote reactivity between N + ions and silicon. At this time, the process pressure and the flow rate for ensuring plasma stability are preferably set to 3 to 8 mTorr and 10 to 30 sccm, respectively.

도 3c에 도시된 바와 같이, 상기 도프트 폴리실리콘층(104) 상부에 동일 챔버에서 RF N2플라즈마 공정을 실시하여 도프트 폴리실리콘과 반응시켜 이후 형성될 텅스텐막 내의 이온 확산과 살리시데이션 반응에 의해 생성되는 화합물을 방지하는 실리콘질화박막(106)을 약 20∼30Å 두께로 형성한다. 이때, 질화처리 공정은 플라즈마의 안정성을 확보하기 위한 공정 압력과 유속을 각각 2∼5mTorr, 10∼50sccm으로 하는 것이 바람직하다.As shown in FIG. 3C, an RF N 2 plasma process may be performed on the doped polysilicon layer 104 in the same chamber to react with the doped polysilicon to cause ion diffusion and salicide reaction in the tungsten film to be formed. The silicon nitride thin film 106 which prevents the compound produced by this is formed in about 20-30 micrometers in thickness. At this time, in the nitriding treatment step, the process pressure and the flow rate for securing the stability of the plasma are preferably set to 2 to 5 mTorr and 10 to 50 sccm, respectively.

한편, 일반적으로 통상의 실리콘질화막(SiNx)은 하기와 같은 화학반응에 의해 생성된다.On the other hand, in general, a conventional silicon nitride film (SiNx) is produced by the following chemical reaction.

N2→ N + NN 2 → N + N

SiH4→ Si + 2H2 SiH 4 → Si + 2H 2

Si + N → SiNxSi + N → SiNx

이러한 화학반응은 반응자유 에너지값이 음의 값이 되는 약 850∼1000℃에서 진행된다.This chemical reaction proceeds at about 850-1000 ° C. where the free reaction energy value becomes negative.

그러나, 본 발명에서와 같이 RF N2플라즈마를 이용하는 경우에는 플라즈마내의 활성화된 N+이온과 도프트 폴리실리콘 표면 원자간의 반응에 의하여 SiNx 형성에 요구되는 하기 화학반응이 상온에서 진행된다.However, when using an RF N 2 plasma as in the present invention, the following chemical reaction required for SiN x formation is performed at room temperature by reaction between activated N + ions in the plasma and doped polysilicon surface atoms.

N → N++ e- N → N + + e -

N++ Si → SiNxN + + Si → SiNx

여기서, N+는 플라즈마내에 활성화된 질소이온, e-는 플라즈마 방전시 방출전자이다.Here, N + is nitrogen ion activated in the plasma, and e is electrons emitted during the plasma discharge.

또한, 본 발명의 RF 방전으로 플라즈마를 형성시킨면 DC방전 플라즈마에 비하여 동일전하 누적층 형성이 억제되어 반응 이온의 척력(repulsion) 현상(정전기적 척력에 의해 동일전하의 이온이 반응표면으로 이동하지 못함)이 배제되므로 Si과 N+간들의 표면 이동도가 증가되어 결과적으로 결정성이 우수한 실리콘질화막이 빠른 질화 속도로 형성된다.In addition, when the plasma is formed by the RF discharge of the present invention, the formation of the same charge accumulation layer is suppressed as compared with the DC discharge plasma, and the repulsion phenomenon of the reaction ions (the electrostatic repulsion does not move the ions of the same charge to the reaction surface). Since the surface mobility between Si and N + is increased, a silicon nitride film having excellent crystallinity is formed at a high nitriding rate.

도 3d에 도시된 바와 같이, 실리콘질화박막(106) 상부에 고융점의 텅스텐을 1000Å∼1500Å의 두께로 증착하여 텅스텐층(108)을 형성한다. 이때, 텅스텐층(108)의 증착 공정은 반응기체로서 WF6와 H2를 사용하며 그 혼합비를 2∼3.5 : 1∼1.8로 하고, 350℃∼450℃의 온도에서 CVD 방법을 이용한다.As shown in FIG. 3D, a high melting point tungsten is deposited on the silicon nitride thin film 106 to a thickness of 1000 GPa to 1500 GPa to form a tungsten layer 108. At this time, the deposition process of the tungsten layer 108 uses WF 6 and H 2 as the reactor body, the mixing ratio is 2 to 3.5: 1 to 1.8, and the CVD method is used at a temperature of 350 ° C to 450 ° C.

이어서 도 3e에 도시된 바와 같이, 게이트 마스크를 이용한 포토리소그래피 공정을 실시하여 상기 순차적으로 적층된 텅스텐층(108), 실리콘질화박막(106) 및 폴리실리콘층(104)을 패터닝하여 반도체소자의 게이트전극(G)을 형성하고 그 패턴에 맞추어 게이트 절연막을 식각하여 본 발명의 게이트전극을 완성한다.3E, a photolithography process using a gate mask is performed to pattern the sequentially stacked tungsten layer 108, the silicon nitride thin film 106, and the polysilicon layer 104 to gate the semiconductor device. An electrode G is formed and the gate insulating film is etched according to the pattern to complete the gate electrode of the present invention.

상기한 바와 같이 본 발명에 따른 게이트전극 형성방법을 이용하면, 텅스텐 게이트전극의 제조시 텅스텐 증착전에 인시튜 플라즈마 질화처리에 의해 도프트 폴리실리콘 표면에 실리콘질화박막을 형성함으로써 다음과 같은 장점을 가질 수 있다.As described above, the method of forming the gate electrode according to the present invention has the following advantages by forming a silicon nitride thin film on the doped polysilicon surface by in-situ plasma nitridation before tungsten deposition during the production of the tungsten gate electrode. Can be.

첫째, 텅스텐층이 실리콘질화막 상부에 증착되는 경우 텅스텐층의 W와 실리콘질화막의 N원자간의 화학적 친화력을 통하여 접착강도의 향상과 동시에 균일한 에너지밴드를 나타내는 텅스텐층(W)/실리콘질화막(SiNx)/도프트 폴리실리콘층 계면이 확보됨에 따라 플랫 밴드의 변화가 감소되므로 트랜지스터 특성을 개선시킬 수 있다.First, when the tungsten layer is deposited on the silicon nitride layer, the tungsten layer (W) / silicon nitride layer (SiNx) exhibits a uniform energy band while improving adhesion strength through chemical affinity between the W of the tungsten layer and the N atoms of the silicon nitride layer. As the / doped polysilicon layer interface is secured, the change of the flat band is reduced, thereby improving transistor characteristics.

둘째, 본 발명은 실리콘질화막의 텅스텐층내의 F 및 H 이온과 도프트 폴리실리콘내의 P이온에 대한 확산방지와 살리시데이션 반응의 억제기능을 통하여 GOI 특성을 개선할 수 있다.Second, the present invention can improve GOI characteristics by preventing diffusion and suppression of salicide reactions of F and H ions in the tungsten layer of the silicon nitride film and P ions in the doped polysilicon.

셋째, 본 발명의 실리콘질화막은 텅스텐/도프트 폴리실리콘의 계면에서 도프트 폴리실리콘의 소모에 의한 계면 그루빙(grooving) 현상을 억제하므로 균일한 계면을 확보할 수 있다.Third, since the silicon nitride film of the present invention suppresses interfacial grooving due to consumption of doped polysilicon at the interface of tungsten / doped polysilicon, a uniform interface can be secured.

넷째, 본 발명의 실리콘질화막은 후속 열공정시 도프트 폴리실리콘내의 도펀트 재분포 현상을 억제하여 도프트 폴리실리콘의 저항 균일성을 배가시킬 수 있는 효과가 있다.Fourth, the silicon nitride film of the present invention has an effect of doubling the resistance uniformity of the doped polysilicon by suppressing the dopant redistribution in the doped polysilicon during the subsequent thermal process.

Claims (5)

게이트 절연막이 형성된 반도체 기판 상부에 도프트 폴리실리콘층과 텅스텐층이 적층된 게이트전극을 형성함에 있어서,In forming a gate electrode in which a doped polysilicon layer and a tungsten layer are stacked on a semiconductor substrate on which a gate insulating film is formed, 상기 반도체기판 상부에 게이트 절연막, 도프트 폴리실리콘층을 순차적으로 형성하는 단계;Sequentially forming a gate insulating layer and a doped polysilicon layer on the semiconductor substrate; 상기 도프트 폴리실리콘층 상부에 동일 챔버에서 RF N2플라즈마 공정을 실시하여 도프트 폴리실리콘과 반응시켜 이후 형성될 텅스텐막내의 이온 확산과 살리시데이션 반응에 의해 생성되는 화합물을 방지하는 실리콘질화박막을 형성하는 단계;A silicon nitride thin film is formed on the doped polysilicon layer by performing an RF N 2 plasma process in the same chamber to react with the doped polysilicon to prevent a compound produced by ion diffusion and salicylation reaction in the tungsten film to be formed. Forming; 상기 실리콘질화박막 상부에 고융점의 텅스텐을 증착하는 단계; 및Depositing tungsten with a high melting point on the silicon nitride thin film; And 상기 적층된 텅스텐층, 실리콘질화박막 및 폴리실리콘층을 패터닝하여 반도체소자의 게이트전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 금속 게이트전극 형성방법.And forming a gate electrode of the semiconductor device by patterning the stacked tungsten layer, the silicon nitride thin film and the polysilicon layer. 제 1항에 있어서, 상기 실리콘질화박막의 두께는 20∼30Å으로 하는 것을 특징으로 하는 반도체소자의 금속 게이트전극 형성방법.The method of forming a metal gate electrode of a semiconductor device according to claim 1, wherein the silicon nitride thin film has a thickness of 20 to 30 GPa. 제 1항에 있어서, 상기 RF N2플라즈마 공정시 13.56MHz의 파형을 갖는 플라즈마를 사용하며 플라즈마의 안정성을 확보하기 위하여 공정 압력을 2∼5mTorr, 유속을 10∼50sccm로 하는 것을 특징으로 하는 반도체소자의 금속 게이트전극 형성방법.The semiconductor device of claim 1, wherein a plasma having a waveform of 13.56 MHz is used in the RF N 2 plasma process, and a process pressure is 2 to 5 mTorr and a flow rate is 10 to 50 sccm in order to ensure plasma stability. Method of forming a metal gate electrode. 제 1항에 있어서, 상기 실리콘질화박막 형성하기 전에 N+ 이온과 실리콘간의 반응성을 촉진하기 위하여 인-시튜 공정으로 Ar 플라즈마에 의해 도프트 폴리실리콘층의 표면을 활성화하는 것을 특징으로 하는 반도체소자의 금속 게이트전극 형성방법.The metal of the semiconductor device of claim 1, wherein the doped polysilicon layer is activated by an Ar plasma in an in-situ process to promote reactivity between N + ions and silicon prior to forming the silicon nitride thin film. Gate electrode formation method. 제 4항에 있어서, 상기 Ar 플라즈마 공정시 그 압력을 2∼5mTorr, 유속을 10∼50sccm로 하는 것을 특징으로 하는 반도체소자의 금속 게이트전극 형성방법.The method of claim 4, wherein the pressure is 2 to 5 mTorr and the flow rate is 10 to 50 sccm during the Ar plasma process.
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WO2014014802A1 (en) * 2012-07-16 2014-01-23 Texas Instruments Incorporated Method of reducing formation of sige abnormal growths on polycrystalline electrodes for strained-channel pmos transistors

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