KR20010008511A - Mehtod of forming IPO layer of MML device - Google Patents

Abstract

PURPOSE: A method for forming an interfacial insulating layer of a merged memory logic is provided to selectively enlarge a space between gate electrodes of a memory cell area, by deteriorating a step coverage wherein a deposition ratio between an upper part of a topology and a lateral part of a topology is adjusted below 1/2 when forming a blocking layer using IPO. CONSTITUTION: In a method for forming an interfacial insulating layer of a merged memory logic including a memory cell array and a peripheral circuit, a cell transistor and an analog transistor are respectively formed on a memory cell area(100) and a peripheral circuit area(200). The cell transistor and the analog transistor include a gate electrode(16) and a source/drain area(20). Oxide material is selectively deposited on an upper part of a gate electrode of the memory cell array area. At this time, a pressure is lowered and a gas quantity is regulated so that an oxide material is deposited on a substrate of a peripheral circuit area. A blocking layer(24a, 24b) is formed to have 1/2 thickness ratio. An interfacial insulating layer is formed on the substrate including both the memory cell area and the peripheral circuit area.

Description

Method of forming interlayer insulating film of composite semiconductor device {Mehtod of forming IPO layer of MML device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a composite memory device, and more particularly, to a method for forming an interlayer insulating film of a composite semiconductor device having excellent gap filling in a composite semiconductor device having different arrangement intervals of elements.

In recent years, as a semiconductor device has been integrated with a memory cell array such as a DRAM (Dynamic Random Access Memory) array and its peripheral circuits together in one chip, a device without sacrificing individual circuit performance and manufacturing cost is required. It is possible to achieve high integration and high speed effectively.

However, in the semiconductor device having high integration, a step difference is largely generated between the memory cell array and the area of the peripheral circuit due to the high density of word lines, high capacity capacitors, and multilayer wiring structures. The step between the memory cell and the peripheral circuit area is a cause for making the manufacturing process of the multi-layered metal wiring difficult, and the planarization of the interlayer insulating film, which serves as electrical insulation, has emerged as an important process.

1 is a vertical cross-sectional view of a semiconductor device in which an interlayer insulating film is formed before forming a contact electrode in a conventional composite semiconductor device.

Referring to FIG. 1, a manufacturing process of a conventional semiconductor device is as follows.

First, a device isolation film 12 is formed on a silicon substrate 10 as a semiconductor substrate, a gate oxide film 14, a doped polysilicon film 16, and an oxide film 18 as a hard mask are stacked on the entire surface of the substrate, and a memory is formed. The gate electrodes of the cell transistors 50 are formed on the substrate of the memory cell array region 100 by patterning the layers 18, 16, and 14 by using a photomask and an etching process using a gate mask of a cell array and a peripheral circuit. Gate electrodes of the analog transistors 150 are formed on the substrate of the peripheral circuit region 200. As a result, the pitches of the gate electrodes disposed in the memory cell array region 100 and the peripheral circuit region 200 of the substrate 10 are different.

Subsequently, a conductive impurity is implanted into the substrate in which only the memory cell array region 100 is opened to form the source / drain region 20 of the cell transistor.

Next, the nitride film 22 is deposited on the entire surface of the substrate, and only the peripheral circuit region 200 is opened, followed by dry etching the nitride film 22 to form sidewall spacers on sidewalls of the gate electrode of the analog transistor 150. 22 '). The source / drain region 20 ′ of the analog transistor 150 is formed by ion implanting conductive impurities only into the substrate of the peripheral circuit region 200.

Next, an interpoly oxide (IPO) of about 200 to 500 kV is deposited as a blocking layer 24 which insulates the lower and upper structures on the entire surface of the substrate and prevents impurities from the upper layer from diffusing into the lower layer. An excellent BPSG (Boro Phospho Silicate Glass) is deposited thickly to form an interlayer insulating film 26 and then planarized by a chemical mechanical polishing process.

Subsequently, although not shown in the drawings, a wiring process for vertically connecting the lower transistor and the upper wiring is performed after the interlayer insulating film process of the composite semiconductor device is completed as described above.

On the other hand, the plug manufacturing process, which is a vertical wiring connecting a bit line or a capacitor lower electrode and a cell applied in a highly integrated semiconductor memory device, has absolutely insufficient space between the gate electrode of the memory cell array region 100. In order to overcome the slight misalignment generated in the mask step, a Self Aligne Contact (SAC) method is used.

That is, in the cell region 100 in which the plug electrode is formed, the nitride film 22 having a large etch selectivity and an etch selectivity may be completely enclosed on the surface of the cell gate electrode to etch the contact hole of the interlayer insulating layer 26 to secure the plug region. It serves to protect the gate electrode. Since the nitride film 22 in the peripheral circuit region may generate a crack in a subsequent thermal process and may act as an etch stop layer during the contact hole etching, only the portion on the upper surface of the gate electrode is removed.

Then, the space between the gate electrodes is very narrow and deep due to the nitride film 22 and the blocking film 24 that are left in the memory cell region 100, while the space between the gate electrodes of the peripheral circuit region 200 is increased. As a result, when forming the interlayer dielectric layer 26, the deposition rate of BPSG varies depending on the region, thereby generating voids between the gate electrodes of the memory cell region 100.

Such voids cause a bridge between the plug polys in the plug electrode process, thereby lowering the yield of the semiconductor memory device.

There are several ways to improve the buried characteristics of BPSG, the deposition material of the interlayer insulating film. The first method is to widen the space between the gate electrodes, and the second method is to reduce the BPSG deposition depth by lowering the step difference between the gate electrodes. The third method is to reduce the thickness of the blocking film to widen the space between the gate electrodes.

However, the first method has a limitation in reducing the size of the gate electrode due to the design of the semiconductor device, and the second method maintains the minimum gate electrode thickness because the gate electrode is damaged during the SAC etching process if the thickness of the hard mask is reduced. must do it.

Finally, the third method is limited in reducing the blocking film because there is a minimum thickness necessary to prevent diffusion of boron (B) and phosphorus (P) contained in the interlayer insulating film in the source / drain region of the peripheral circuit region during the heat treatment process. there was.

An object of the present invention is to adjust the deposition rate of the top and side portions of the topologies to 1/2 or less when the blocking film is formed using the IPO under the interlayer insulating film of the BPSG to reduce the step coverage of the memory cell region. The present invention provides a method for forming an interlayer insulating film of a composite semiconductor device, in which only the space between the gate electrodes can be selectively widened, and thus the buried property of the interlayer insulating film is excellent.

1 is a vertical cross-sectional view of a semiconductor device in which an interlayer insulating film is formed before forming a contact electrode in a conventional composite semiconductor device;

2A to 2D are flowcharts illustrating a process of manufacturing an interlayer dielectric film of a composite semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

10 silicon substrate 12 device isolation film

14 gate insulating film 16 gate electrode

18: Hard Mask 20: Source / Drain Area

22: insulating film 22 ': sidewall spacer

24a, 24b: blocking film 26: second interlayer insulating film

100: memory cell array area 200: peripheral circuit area

In order to achieve the above object, the present invention provides a method of forming a cell transistor and an analog transistor having a gate electrode and a source / drain region in a memory cell array region and a peripheral circuit region in a semiconductor substrate, and forming an upper portion of the gate electrode in the memory cell array region. Forming a blocking film having a thickness ratio of 1/2 by lowering the pressure and adjusting the amount of gas so that the oxide material is selectively deposited on the surface and the oxide material is deposited on the entire surface of the substrate in the peripheral circuit area. And forming an interlayer insulating film for interlayer insulation of the lower structure on the front surface of the substrate corresponding to the circuit region.

In the manufacturing method of the present invention, the deposition process of the blocking film is formed by reacting SiH ₄ and N ₂ O gas by a low pressure chemical vapor deposition method at a deposition temperature of 750 ℃ or more and a reaction chamber pressure of 0.1 to 0.3 Torr to form a high temperature thermal oxide film or Decomposition of TEOS gas by low pressure chemical vapor deposition under a deposition temperature of 650 ° C. or above and a reaction chamber pressure of 0.1 to 0.3 Torr, to deposit an LP-TEOS film, or to deposit TEOS gas by a plasma enhancement method at a deposition temperature of 500 ° C. or less. It is characterized by depositing a PE-TEOS film by decomposition.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, and embodiments of the present invention use the same reference numerals for the same parts as in the prior art.

2A to 2D are flowcharts illustrating a process of manufacturing an interlayer insulating film of a composite semiconductor device according to the present invention. Referring to this, the manufacturing process of the present invention is as follows.

First, as shown in FIG. 2A, the device isolation film 12 is formed on the silicon substrate 10, and the gate oxide film 14, the doped polysilicon film 16, and the oxide film 18 as a hard mask are formed on the entire surface of the substrate. These layers 18, 16 and 14 are patterned by stacking and performing a photolithography and etching process using a gate mask of a memory cell array and a peripheral circuit. As a result, the gate electrode of the cell transistor 50 is formed on the substrate of the memory cell array region 100, and the gate electrode of the analog transistor 150 is formed on the substrate of the peripheral circuit region 200.

In the embodiment of the present invention, in the gate electrode as described above, silicide having a low specific resistance may be further deposited on the polysilicon film 16 to increase the electrical conductivity, and a photoresist patterning process may be performed on the hard mask oxide film 18. An antireflection film may be further deposited to increase the efficiency of the film.

Subsequently, the source / drain region 20 of the cell transistor is formed by ion implanting conductive impurities into the substrate in which only the memory cell array region 100 is opened.

Next, as illustrated in FIG. 2B, the nitride film 22 is deposited on the entire surface of the substrate, and only the peripheral circuit region 200 is opened, followed by dry etching the nitride film 22 to gate the analog transistor 150. Sidewall spacers 22 'are formed on the electrode sidewalls. The source / drain region 20 ′ of the analog transistor 150 is formed by ion implanting conductive impurities only into the substrate of the peripheral circuit region 200.

Next, as illustrated in FIG. 2C, an IPO deposition process, which is a blocking film of the present invention, is performed to insulate the lower and upper structures on the entire surface of the substrate and to prevent impurities from the upper layer from diffusing into the lower layer. Typically, the IPO is deposited to maintain a uniform thickness even if there is a topography on the wafer surface, but in the present invention, the deposition conditions of the top and side portions of the topologies are adjusted to 1/2 or less as follows.

The blocking film deposition process of the present invention reacts SiH ₄ with N ₂ O gas by a low pressure chemical vapor deposition method at a deposition temperature of 750 ° C. or higher and a reaction chamber pressure of 0.1 to 0.3 Torr to obtain HTO (high temperature oxide), which is a high temperature thermal oxide film. LP-TEOS is formed by decomposing the tetra-ethly-ortho-silicate (TEOS) gas by low pressure chemical vapor deposition at a deposition temperature of 650 ° C. or higher and a reaction chamber pressure of 0.1 to 0.3 Torr. Alternatively, the TEOS gas may be decomposed by a plasma enhanced method at a deposition temperature of 500 ° C. to form PE-TEOS.

Here, the deposition thickness of the blocking film is preferably about 100 to 500 mW so that the concentration gradient of impurities implanted in the silicon substrate in the peripheral circuit region is not disturbed by diffusion of boron, phosphorus, etc. contained in the interlayer insulating film of the BPSG. .

By the IPO deposition process according to the present invention, the blocking film 24a is selectively formed only on the upper surface of the nitride film 22 surrounding the gate electrode in the memory cell array region 100, and the entire structure in the peripheral circuit region 200. The blocking film 24b is formed in the film.

Subsequently, as illustrated in FIG. 2D, a thick BPSG (Boro Phospho Silicate Glass) having excellent gap fill characteristics is deposited on the structure to form an interlayer insulating layer 26, and then planarized by a chemical mechanical polishing process.

As described above, according to the present invention, the step coverage is poor during the deposition of the blocking film, such that the blocking film is not formed on the side of the gate electrode in the memory cell array region, and the blocking film is uniformly deposited on the entire surface of the substrate in the peripheral circuit region.

Therefore, the present invention can secure a large space between the gate electrodes in the memory cell array region, so that the embedding of the insulator becomes good without generation of voids during the deposition of the interlayer insulating film. In addition, it is possible to lower the thickness of the IPO, which serves as a blocking function in the peripheral circuit area.

Claims (6)

A method of forming an interlayer insulating film of a composite semiconductor device in which a memory cell array and its peripheral circuits are integrated, Forming cell transistors and analog transistors each having a gate electrode and a source / drain region in a memory cell array region and a peripheral circuit region in a semiconductor substrate; An oxide material is selectively deposited on an upper surface of the gate electrode of the memory cell array region, and at the same time, a blocking film having a thickness ratio of 1/2 is formed by lowering the pressure and adjusting the amount of gas so that the oxide material is deposited on the entire surface of the substrate in the peripheral circuit region. step; Forming an interlayer insulating film on the front surface of the substrate corresponding to the memory cell array region and the peripheral circuit region for interlayer insulation of the lower structure. The method of claim 1, wherein the deposition process of the blocking film is performed by reacting SiH ₄ with N ₂ O gas by a low pressure chemical vapor deposition method under a deposition temperature of at least 750 ° C. and a reaction chamber pressure of 0.1 to 0.3 Torr to form a high temperature thermal oxide film. An interlayer insulating film forming method of a composite semiconductor device. The composite semiconductor according to claim 1, wherein the blocking film is deposited using a low pressure chemical vapor deposition method at a deposition temperature of 650 ° C. or higher and a reaction chamber pressure of 0.1 to 0.3 Torr to deposit an LP-TEOS film. A method of forming an interlayer insulating film of a device. The method of claim 1, wherein the blocking thin film is deposited by decomposing TEOS gas at a deposition temperature of 500 ° C. or lower by a plasma enhanced method. The method for forming an interlayer insulating film of a composite semiconductor device according to claim 1, wherein the blocking thin film has a thickness of 100 to 500 GPa. The method of claim 1, wherein the interlayer insulating film is BPSG.