KR20010008410A - Method for manufacturing plug line of semiconductor device - Google Patents
Method for manufacturing plug line of semiconductor device Download PDFInfo
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- KR20010008410A KR20010008410A KR1019980058885A KR19980058885A KR20010008410A KR 20010008410 A KR20010008410 A KR 20010008410A KR 1019980058885 A KR1019980058885 A KR 1019980058885A KR 19980058885 A KR19980058885 A KR 19980058885A KR 20010008410 A KR20010008410 A KR 20010008410A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 플러그라인(Plug Line)을 형성하는 방법에 관한 것으로, 특히, 수소플라즈마를 이용하여 웨이퍼를 수소 환원반응시켜 그레인의 성장을 방해하는 물질을 제거한 후 도핑된 비정질실리콘을 증착한 후 열처리 공정으로 플러그 라인의 그레인을 조대화시키므로 도핑된 인(Phosphorous)이 후속열처리공정에서 소오스/드레인영역으로 침투하는 것을 방지하도록 하는 반도체소자의 플러그라인 제조방법에 관한 것이다.The present invention relates to a method for forming a plug line. In particular, a hydrogen reduction reaction is performed on a wafer using hydrogen plasma to remove a material that prevents grain growth, and then a doped amorphous silicon is deposited, followed by a heat treatment process. Therefore, the present invention relates to a method of manufacturing a plug line of a semiconductor device in which grains of a plug line are coarsened to prevent doped phosphorus from penetrating into a source / drain region in a subsequent heat treatment process.
일반적으로, 반도체소자를 반도체기판에 트랜지스터의 게이트전극을 형성하고, 그 위에 절연막을 적층하여 식각을 하여 상부에에 형성되는 비트라인(Bit Line)과 커패시터(Capacitor)의 전하저장전극(Charge Storage Electrode)에 수직으로 형성되는 플러그라인(Plug Line)을 이용하여 양자사이를 전기적으로 도전시키는 역할을 하게 된다.In general, a semiconductor device includes a gate electrode of a transistor formed on a semiconductor substrate, and an insulating layer is stacked on the semiconductor substrate to be etched to form a charge storage electrode of a bit line and a capacitor formed thereon. Using a plug line formed perpendicular to the () to play a role of electrically conducting between the two.
도 1은 일반적인 플러그라인과 그에 관련된 구성을 보인 도면으로서, 반도체기판(10)상에 소자분리막으로서 필드산화막(20)을 형성하고, 후속공정을 진행하여 게이트전극(25)을 형성한 후 상,하부를 절연하기 위한 절연막(30)을 형성하도록 한다.FIG. 1 is a view illustrating a general plug line and a related configuration. A field oxide film 20 is formed as a device isolation film on a semiconductor substrate 10, and a subsequent process is performed to form a gate electrode 25. An insulating film 30 for insulating the lower portion is formed.
그리고, 상기 절연막(30)에 콘택홀을 식각하여 전기적으로 도전되는 물질이 도핑되어 있는 플러그라인(40)을 형성한 후 그 위에 비트라인(50)과 전하를 저장하도록 하는 커패시터의 전하저장전극(60)등이 형성되어지게 된다.Then, the contact hole is etched in the insulating film 30 to form a plug line 40 doped with an electrically conductive material, and then the charge storage electrode of the capacitor to store the bit line 50 and the charge thereon ( 60) is formed.
이러한 공정을 진행할 경우 폴리실리콘내에 도핑된 포스포러스 농도에 따라 소자의 특성 열화현상이 발생되어진다. 즉 인의 농도가 증가하게 되면, 플러그라인의 비저항은 감소하게 되어 반도체소자의 구동속도가 증가하게 되고 바이어스전압(Bias Voltage)의 변화에 따른 전류가 선형적으로 변화하게 되어 안정적인 소자특성을 유지할 수 있다.In this process, deterioration of characteristics of the device may occur depending on the concentration of phosphorus doped in polysilicon. In other words, if the concentration of phosphorus is increased, the resistivity of the plug line is decreased to increase the driving speed of the semiconductor device, and the current is linearly changed according to the change of the bias voltage, thereby maintaining stable device characteristics. .
그러나, 후속열공정 후 소오스/드레인영역 쪽으로 플러그라인(폴리실리콘으로 형성됨)내부에 도핑된 인의 확산(Diffusion)범위가 도 2에 도시된 바와 같이, 소오스/드레인영역(15)의 하측 부분으로 퍼지게 되면서, 인이 확산되어 있는 확장영역(17)을 임의적으로 형성하는 상태를 지니게 된다.However, the diffusion range of the doped phosphorus in the plug line (formed of polysilicon) toward the source / drain region after the subsequent thermal process is spread to the lower portion of the source / drain region 15 as shown in FIG. As a result, the expanded region 17 into which phosphorus is diffused may be formed arbitrarily.
따라서, 트랜지스터의 정션리키지(Junction Leakage) 및 GIDL(Gate Induced Drain Leakage)을 증가시키는 결과를 초래하는 문제를 지니고 있었으며, 또한 이와는 반대로 인의 농도가 감소하는 경우 정션리키지(Junction Leakage) 및 GIDL(Gate Induced Drain Leakage)을 감소시키나 플러그라인의 비저항이 증가하여 소자의 구동속도를 감소시키고 바이어스전압 변화에 따른 전류의 변화가 비선형적이어서 소자의 특성을 안정적으로 유지하지 못하는 문제점을 지니고 있었다.Therefore, it has a problem of increasing the junction junction and gate induced drain leakage (GIDL) of the transistor, and conversely, when the concentration of phosphorus decreases, the junction leakage and GIDL ( Gate Induced Drain Leakage) was reduced, but the resistivity of the plug line was increased to reduce the driving speed of the device and the change of current due to the change of bias voltage was non-linear.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 챔버내부의 안치대에 웨이퍼를 안치시키고, 수소플라즈마발생수단에서 수소플라즈마를 발생하여 수소 환원반응시켜 그레인의 성장을 방해하는 물질을 제거한 후 도핑된 비정질실리콘을 증착하여 열처리 공정으로 플러그 라인의 그레인을 조대화시키므로 도핑된 인(Phosphorous)이 후속열처리공정에서 소오스/드레인영역으로 침투하는 것을 방지하도록 하는 것이 목적이다.The present invention has been made in view of this point, the wafer is placed in the interior of the chamber, the hydrogen plasma generating means by the hydrogen plasma generated by hydrogen reduction reaction to remove the material that interferes with the growth of grains doped amorphous The purpose is to prevent the doped phosphorus from penetrating into the source / drain region in the subsequent heat treatment process by depositing silicon to coarsen the grain of the plug line in the heat treatment process.
도 1은 일반적인 플러그라인을 형성한 반도체소자의 구성을 보인 도면.1 is a view showing a configuration of a semiconductor device having a general plug line.
도 2는 종래의 플러그라인을 형성한 후 후속열공정에 의하여 도핑된 P가 소오스/드레인영역으로 확산되는 상태를 보이고 있는 도면.2 is a view showing a state in which a doped P is diffused into a source / drain region by a subsequent thermal process after forming a conventional plug line.
도 3은 본 발명에 따른 프라즈마발생수단으로 웨이퍼를 플라즈마처리하는 상태를 도시하고 있는 도면.3 is a view showing a state of plasma processing a wafer by the plasma generating means according to the present invention.
도 4는 본 발명에 따른 플러그라인의 구성을 보인 도면.4 is a view showing the configuration of a plug line according to the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 15 : 소오스/드레인영역10: semiconductor substrate 15: source / drain region
20 : 필드산화막 25 : 게이트전극20: field oxide film 25: gate electrode
30 : 절연막 40,40' : 플러그라인30: insulating film 40, 40 ': plug line
50 : 비트라인 60 : 전하저장전극50: bit line 60: charge storage electrode
70 : 웨이퍼안치대 80 : 플라즈마형성지역70 wafer wafer stage 80 plasma forming area
90 : 수소플라즈마발생수단 100 : 챔버90: hydrogen plasma generating means 100: chamber
A : 웨이퍼A: Wafer
이러한 목적은 플러그라인이 형성될 예정인 콘택홀을 갖는 웨이퍼를 챔버의 내부에 있는 웨이퍼안치대에 안치시킨 후 챔버 내부의 가스를 외부로 배출하여 내부의 압력을 낮추는 단계와; 상기 챔버에 설치되는 수소플라즈마발생수단에서 수소플라즈마를 발생하여 웨이퍼에 잔존된 산소를 수소로 환원반응시켜 챔버 외부로 배출하는 단계와; 상기 웨이퍼의 절연막에 형성된 콘택홀내에 도펀트가 도핑된 비정질실리콘을 증착하여 플러그라인을 형성하는 단계와; 상기 상기 결과물에 열공정을 가하여 플러그라인에 결정립을 조대화시키도록 하는 단계를 포함한 반도체소자의 플러그라인제조방법의 일 실시예를 제공하므로써 달성된다.The purpose is to lower the pressure therein by placing a wafer having a contact hole, on which a plug line is to be formed, in a wafer stabilizer inside the chamber and then discharging the gas inside the chamber to the outside; Generating a hydrogen plasma in the hydrogen plasma generating means installed in the chamber to reduce the oxygen remaining on the wafer with hydrogen and to discharge the oxygen to the outside of the chamber; Depositing amorphous silicon doped with a dopant in a contact hole formed in the insulating film of the wafer to form a plug line; It is achieved by providing an embodiment of a method for manufacturing a plug line of a semiconductor device comprising applying a thermal process to the resultant to coarse grains in the plug line.
그리고, 상기 챔버내부의 압력을 웨이퍼 로딩시 10-3Torr이하로 유지하고, 상기 웨이퍼를 수소환원반응시 챔버내부의 압력을 10-1Torr이하로 유지하고, 7000℃이하의 저온에서 진행하도록 한다.Then, maintaining the pressure within the chamber to below 10 -3 Torr during wafer loading and to maintain the hydrogen reduction reaction when the pressure in the chamber below the wafer 10 -1 Torr, and proceeds at a low temperature of less than 7000 ℃ .
그리고, 상기 웨이퍼의 콘택홀내에 비정질실리콘을 적층할 때 SiH4+ PH3가스 혹은 Si2H6+ PH3가스를 적절한 비율로 530℃이하의 온도에서 진행한다.When the amorphous silicon is deposited in the contact hole of the wafer, the SiH 4 + PH 3 gas or the Si 2 H 6 + PH 3 gas is advanced at a temperature of 530 ° C. or less at an appropriate ratio.
그리고, 상기 플러그라인의 비정질실리콘은 산소가스로 패시베이션(Passivation) 처리를 한 후 600℃이상의 온도에서 열처리하도록 한다.In addition, the amorphous silicon of the plug line may be heat treated at a temperature of 600 ° C. or higher after passivation with oxygen gas.
또한, 본 고안의 목적은 플러그라인이 형성될 예정인 콘택홀을 갖는 웨이퍼를 챔버의 내부에 있는 웨이퍼안치대에 안치시킨 후 챔버 내부의 가스를 외부로 배출하여 내부의 압력을 낮추는 단계와; 상기 챔버에 설치되는 플라즈마발생수단에서 플라즈마를 발생하여 웨이퍼에 잔존된 산소를 수소로 환원반응시켜 챔버 외부로 배출하는 단계와; 상기 웨이퍼의 절연막에 형성된 콘택홀내에 보통의 비정질실리콘을 증착하여 플러그라인을 형성하는 단계와; 상기 결과물에 열공정을 가하여 플러그라인에 결정립을 조대화시키도록 하는 단계와; 상기 결과물을 열 도핑공정으로 플러그라인에 인을 도핑하는 단계를 포함한 반도체소자의 플러그라인제조방법의 다른 실시예를 제공하므로써 달성된다.In addition, an object of the present invention comprises the steps of lowering the pressure in the interior by discharging the gas inside the chamber after placing the wafer having a contact hole, the plug line is to be formed in the wafer stabilizer in the chamber; Generating plasma by plasma generating means installed in the chamber and reducing oxygen remaining on the wafer with hydrogen to discharge the oxygen to the outside of the chamber; Depositing ordinary amorphous silicon in a contact hole formed in the insulating film of the wafer to form a plug line; Applying a thermal process to the resultant to coarsen the grains in the plug line; This result is achieved by providing another embodiment of a method for manufacturing a plug line of a semiconductor device comprising the step of doping phosphorus into the plug line in a thermal doping process.
또한, 상기 플러그라인을 열도핑하는 공정은 1 ∼ 30Torr의 압력을 유지하고 600 ∼ 800℃의 온도로 진행하도록 하고, 상기 플러그라인을 열도핑하는 공정은 불활성기체로 희석시킨 PH3가스 혹은 순수한 PH3가스를 챔버로 주입하여 진행하도록 한다.In addition, the process of heat doping the plug line is to maintain a pressure of 1 ~ 30 Torr and proceed to a temperature of 600 ~ 800 ℃, the process of heat doping the plug line is PH 3 gas or pure PH diluted with an inert gas 3 Inject gas into the chamber to proceed.
그리고, 상기 플러그라인을 열도핑하는 공정은 챔버 내부에 질소가스를 주입하여 1 ∼ 30Torr의 압력과, 600 ∼ 800℃의 온도를 유지한 상태에서 어닐링(Annealing)하는 단계를 더 포함한다.In addition, the process of thermally doping the plug line further includes the step of annealing the nitrogen gas in the chamber to maintain a pressure of 1 to 30 Torr and a temperature of 600 to 800 ℃.
이하, 첨부한 도면에 의거하여 본 발명에 바람직한 일실시예에 대하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 프라즈마발생수단으로 웨이퍼를 플라즈마처리하는 상태를 도시하고 있는 도면이고, 도 4는 본 발명에 따른 플러그라인의 구성을 보인 도면이다.3 is a view showing a state of plasma processing the wafer by the plasma generating means according to the present invention, Figure 4 is a view showing the configuration of a plug line according to the present invention.
본 발명의 일실시예에 따른 플러그라인제조방법을 살펴 보면, 플러그라인(Plug Line)이 형성될 예정인 영역을 갖는 웨이퍼(A)를 챔버(Chamber)(100)의 내부에 있는 웨이퍼안치대(70)에 안치시킨 후 챔버(100) 내부의 가스를 외부로 배출하여 내부의 압력을 낮추도록 한다.Looking at the plug line manufacturing method according to an embodiment of the present invention, the wafer A having a region where the plug line (Plug Line) is to be formed, the wafer stabilizer 70 in the chamber (100) ) And the gas inside the chamber 100 to the outside to lower the internal pressure.
그리고, 상기 챔버(100)에 설치되는 플라즈마발생수단(90)에서 플라즈마(Plasma)를 발생하여 웨이퍼(A)에 잔존된 산소를 수소로 환원반응시켜 챔버(100) 외부로 배출하도록 한다.In addition, plasma is generated in the plasma generating means 90 installed in the chamber 100 to reduce the oxygen remaining in the wafer A with hydrogen to discharge the oxygen to the outside of the chamber 100.
이때, 상기 챔버내부의 압력을 웨이퍼(A) 로딩시 10-3Torr이하로 유지하도록 하고, 상기 웨이퍼를 수소환원반응시 챔버내부의 압력을 10-1Torr이하로 유지하여 550℃이하의 저온에서 진행하도록 한다.At this time, the pressure inside the chamber is maintained at 10 -3 Torr or less when the wafer A is loaded, and the pressure inside the chamber is maintained at 10 -1 Torr or less during the hydrogen reduction reaction at a low temperature of 550 ° C. or less. Let's proceed.
그리고, 상기 웨이퍼(A)의 절연막(30)에 형성된 콘택홀(Contact Hole)내에 도펀트(Dopant)가 도핑된 비정질실리콘(Doped Amorphrous Poly-Silicon)을 증착하여 플러그라인(40')을 형성하도록 한다.In addition, a doped Amorphrous Poly-Silicon doped with a dopant is deposited in a contact hole formed in the insulating layer 30 of the wafer A to form a plug line 40 '. .
이때, 상기 웨이퍼의 콘택홀내에 비정질실리콘을 적층할 때 SiH4+ PH3가스 혹은 Si2H6+ PH3가스를 적절한 비율로 530℃이하의 온도에서 진행하도록 한다.At this time, SiH 4 + PH 3 gas or Si 2 H 6 + PH 3 gas in an appropriate ratio when the amorphous silicon is deposited in the contact hole of the wafer to proceed at a temperature of 530 ℃ or less.
또한, 상기 상기 결과물에 열공정을 가하여 플러그라인(40')에 결정립을 조대화시키는 것으로서, 상기 플러그라인(40')의 비정질실리콘은 산소가스로 패시베이션(Passivation) 처리를 한 후 600℃이상의 온도에서 열처리하도록 한다.In addition, the thermal process is applied to the resultant coarse grains in the plug line 40 ', and the amorphous silicon of the plug line 40' is subjected to passivation with oxygen gas at a temperature of 600 ° C. or more. Heat treatment.
본 발명의 다른 실시예에 따른 플러그라인 제조방법을 살펴 보면, 플러그라인을 형성하는 과정까지는 일 실시예와 유사하다.Looking at the plug line manufacturing method according to another embodiment of the present invention, the process of forming the plug line is similar to one embodiment.
우선, 플러그라인이 형성될 예정인 콘택홀을 갖는 웨이퍼(A)를 챔버(100)의 내부에 있는 웨이퍼안치대(70)에 안치시킨 후 챔버(100) 내부의 가스를 외부로 배출하여 내부의 압력을 낮추도록 한다.First, the wafer A having the contact hole, in which the plug line is to be formed, is placed in the wafer support 70 in the chamber 100, and then the gas inside the chamber 100 is discharged to the outside. To lower it.
그리고, 상기 챔버(100)에 설치된 수소플라즈마발생수단(90)에서 수소플라즈마를 발생하여 웨이퍼(A)에 잔존된 산소를 수소 환원반응시켜 챔버(100) 외부로 배출하도록 한다,Then, the hydrogen plasma is generated in the hydrogen plasma generating means 90 installed in the chamber 100 to hydrogen-reduce the oxygen remaining in the wafer A to discharge to the outside of the chamber 100,
그리고, 상기 웨이퍼(A)의 절연막(30)에 형성된 콘택홀내에 도핑되지 않은 비정질실리콘(Undoped Amorphrous Poly-Silicon)을 증착하여 플러그라인(40')을 형성하도록 한다.Then, an undoped amorphous silicon (Undoped Amorphrous Poly-Silicon) is deposited in the contact hole formed in the insulating film 30 of the wafer (A) to form a plug line (40 ').
그리고, 상기 플러그라인의 비정질실리콘을 산소가스로 패시베이션(Passivation) 처리를 한 후 600℃이상의 온도에서 열처리하도록 한다.In addition, after the passivation treatment of amorphous silicon of the plug line with oxygen gas, heat treatment is performed at a temperature of 600 ° C. or higher.
이때, 상기 결과물에 열공정을 가하여 플러그라인(40')에 결정립을 조대화시키도록 한다.At this time, a thermal process is applied to the resultant to coarsen the grains in the plug line 40 '.
그런 후, 상기 결과물을 열 도핑공정으로 플러그라인(40')에 인을 도핑하도록 하는 것으로서, 상기 플러그라인(40')을 열도핑하는 공정은 1 ∼ 30Torr의 압력을 유지하고 600 ∼ 800℃의 온도로 진행한다.Thereafter, the resultant is to be doped phosphorus to the plug line 40 'by a thermal doping process, the step of thermally doping the plug line 40' is maintained at a pressure of 1 ~ 30 Torr and 600 ~ 800 ℃ Proceed to temperature.
그리고, 상기 플러그라인(40')을 열도핑하는 공정은 불활성기체로 희석시킨 PH3가스 혹은 순수한 PH3가스를 챔버(100)로 주입하여 진행하도록 한다.In addition, the process of thermally doping the plug line 40 ′ is performed by injecting PH 3 gas or pure PH 3 gas diluted with an inert gas into the chamber 100.
그리고, 상기 플러그라인(40')을 열도핑하는 공정은 챔버(100) 내부에 질소가스를 주입하여 1 ∼ 30Torr의 압력을 유지하고 600 ∼ 800℃의 온도를 유지한 상태에서 어닐링(Annealing)하여 결정립을 균일화시키도록 한다.In the process of thermally doping the plug line 40 ', nitrogen gas is injected into the chamber 100 to maintain a pressure of 1 to 30 Torr and to anneal while maintaining a temperature of 600 to 800 ° C. Make the grains uniform.
그리고, 상기 플러그라인(40')에 인을 도핑하기 전에 유기물질(자연산화막등)을 제거하기 위하여 H2SO4,H2O2, 및 D.I워터가 혼합된 화학물질, 또는 NH4OH, H2O2, D.I워터가 혼합된 화학물질을 사용하여 웨이퍼를 세정하도록 한다.Then, to remove the organic material (natural oxide film, etc.) before doping phosphorus on the plug line 40 ', H 2 SO 4, H 2 O 2 , and chemicals mixed with DI water, or NH 4 OH, Clean the wafer using a mixture of H 2 O 2 and DI water.
따라서, 상기한 바와 같이 본 발명에 따른 반도체소자의 플러그라인제조방법을 이용하게 되면, 챔버내부의 안치대에 웨이퍼를 안치시키고, 수소플라즈마발생수단에서 발생된 수소플라즈마로 수소 환원반응시켜 그레인의 성장을 방해하는 물질을 제거한 후 도핑된 비정질실리콘을 증착하여 열처리 공정으로 플러그 라인의 그레인(결정립)을 조대화시키므로 도핑된 인(Phosphorous)이 후속 열처리공정에서 소오스/드레인영역으로 침투하는 것을 줄여주어 반도체소자의 전기적인 특성이 저하되는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the plug line manufacturing method of the semiconductor device according to the present invention is used as described above, the grains are deposited by placing the wafer in a support zone inside the chamber and hydrogen reduction reaction with hydrogen plasma generated by the hydrogen plasma generating means. After removing the material that interferes with the deposition process, the doped amorphous silicon is deposited to coarse the grains of the plug line by the heat treatment process. It is a very useful and effective invention to prevent the electrical properties of the device from deteriorating.
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