KR20010007483A - Decoder circuit - Google Patents

Abstract

PURPOSE: A decoder circuit is provided to improve a switching rate from a non-selection to a selection by operating a p-channel active load with feedback of n-channel short circuit level to a gate of p-channel active load. CONSTITUTION: A switch circuit receives an address signal, and connects a node(X) with a grounding line or isolates the node(X) from the grounding line according to the address signal(a, b, c). A p-channel transistor(P1) supplies the node(X) with a power. A gate electrode of the p-channel transistor(P1) connects with the grounding line in case the node(X) connects with the grounding line, and receives a voltage of an appointed level between a source voltage level and a grounding line level in case the node(X) isolates from the grounding line. A decoded signal varies according to a voltage level of the node(X).

Description

Decoder Circuitry {DECODER CIRCUIT}

Field of invention

The present invention relates to a decoder circuit, and more particularly, to a predecoder circuit located between an address decoder circuit of a semiconductor memory device and another decoder circuit.

Description of the related technology

Recently, semiconductor memory devices that perform high-speed operations have played a large role in the rapid performance improvement of personal computers and workstations.

The semiconductor memory device includes an address decoder circuit, a predecoder circuit, and a decoder circuit, which circuit selects word lines as detailed below.

An example of a conventional predecoder circuit will be described with reference to FIG. 14 illustrates an example in which three addresses are input. The predecoder circuit includes first to third P-channel (Pch) transistors P1 to P3 and first to third N-channel (Nch) transistors N1. To N3).

The input signals A, B and C are applied as address signals. When the potential levels of the address signals A, B and C are " high level H ", the first to third Nch transistors N1 to N3 are turned ON and the first to third are turned on. Pch transistors P1 to P3 are turned off. As a result, the charge of the node X is discharged to GND. In addition, the potential of the output / OUT is at the low level L. That is, the output (/ OUT) is in the selected state.

When at least one of the address signals A, B and C has a "L" level, at least one of the first to third Nch transistors N1 to N3 is in an OFF state, and the node X and GND The path between them is blocked. On the other hand, when at least one of the first to third Pch transistors P1 to P3 is in the ON state, the node X is charged with the electric charge from the power supply Vcc to be at the "H" level. The output / OUT is at " H " level, i.e., unselected.

Another example of a conventional predecoder circuit will be described with reference to FIG. The predecoder circuit of Fig. 15 uses a Pch transistor P1 whose gate electrode is connected to GND. Thus, the Pch transistor P1 is in a normally on state. The predecoder circuit is provided with address signals A, B and C in a manner similar to the predecoder circuit shown in FIG. As described with reference to Fig. 14, when the potentials of the address signals A, B, and c are "H", the first to third Nch transistors N1 to N3 are in the ON state. As a result, the electric charge applied to the node X through the Pch transistor P1 is discharged to GND. The potential of the node X is at the "L" level, and the output / OUT is at the "L" level, that is, in a selected state.

On the other hand, when at least one of the address signals A, B and C is at the "L" level, at least one of the first to third Nch transistors N1 to N3 is in the OFF state, and the node X The path between GNDs is blocked. The potential of the node X is brought to the "H" level by the charge provided to the node X through the normally-on transistor P1. Then, the output / OUT takes the "H" level, i.e., the non-select state.

Another example of a conventional predecoder circuit will be described below with reference to FIG. The predecoder circuit of FIG. 16 uses a source drive system. When the potentials of the address signals A and B become " H ", the first and second Nch transistors N1 to N2 are turned ON. On the other hand, the address signal / C, which is an opposite-phase signal of the address signal C, is input to the source of the second Nch transistor N2 at the "L" level. As a result, the potential of the node X becomes "L" level. The output / OUT is brought to the "L" level, that is, the selected state.

If at least one of the address signals A and B is at the "L" level, the path between the second Nch transistor N2 and the node X is blocked. As a result, the potential of the node X becomes "H" due to the electric charge supplied to the node X via the normal-on Pch transistor P1. The potential of the output / OUT is at " H " level, that is, in an unselected state.

In addition, when the potential of the address signal / C is " H " when the first and second Nch transistors N1 and N2 are in the ON state, the " H " level and the normal ON of the address signal / c are The electric potential of the node X becomes "H" by the electric charge supplied to the node X via the Pch transistor P1. As a result, the output / OUT enters the non-select state at the "H" level.

In the predecoder circuits shown in Figs. 14 and 15, the gate width ratio of the Pch / Nch transistors is changed in order to adjust the switching speed from the selected state to the unselected state or vice versa. However, in order to increase the switching speed from the non-selection state to the selection state, when the gate width of the Nch transistor is increased or when the gate width of the Pch transistor is reduced, the switching speed from the select state to the non-select state is reversed. Reduced, unwanted multi-selection may occur. Therefore, the predecoder circuit shown in Figs. 14, 15 and 16 has a problem that it is difficult to increase the selection speed.

Also, in the predecoder circuit shown in Fig. 16, a signal line with a large capacitive load is used as the source input to increase the speed. However, in the predecoder circuit shown in Fig. 16, since amplification is completely performed at the output stage, the charge is discharged from the Vcc level to the GND level during the selection, which results in a slowing down of the selection speed. This also applies to the circuit shown in FIGS. 14 and 15.

In the above-described predecoder circuit, since the P / N ratio is constant according to the dimension during the transition from the selected state to the unselected state, the selection speed without delaying switching from the selected state to the unselected state. It is difficult to increase.

It is an object of the present invention to provide a predecoder circuit capable of increasing the switching speed from a selected state to a non-selected state and a switching speed from a non-selected state to a selected state without causing multiple selection.

To achieve this object, according to the present invention, there is provided a decoder circuit for decoding a plurality of input address signals and outputting a decoded signal on an output terminal, the decoder circuit receiving the address signal and the plurality of addresses. A switch circuit connecting a node to a ground line or disconnecting the node from the ground line according to a signal, and a p-channel transistor providing a power supply voltage to the node, wherein the gate electrode of the p-channel transistor is connected to the node. When connected to a ground line and connected to a ground line and when the node is disconnected from the ground line, a voltage having a predetermined level that is halfway between the level of a power supply voltage and the ground line is received, and the decoded signal is connected to the voltage level of the node. Change accordingly.

According to the present invention, it is possible to increase both the switching speed from the selected state to the non-selected state and the switching speed from the non-selected state to the selected state.

The above and other objects, features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

1 is a circuit diagram showing a first embodiment of the predecoder circuit of the invention.

2 is a diagram illustrating an example of an address initial-stage.

3 is a diagram showing an example of the configuration of an address decoder circuit located at the front end of the predecoder circuit and the next end of the address ultrastage circuit;

Fig. 4 is a circuit diagram showing an example of the address circuit shown in Fig. 3 when three inputs are present.

Fig. 5 is a circuit diagram showing an example of the address circuit shown in Fig. 3 when two inputs are present.

6 is a diagram illustrating an example of a predecoder circuit configuration.

FIG. 7 is a waveform diagram for comparing the operation of the predecoder circuit shown in FIG. 1 with the predecoder circuit of the prior art. FIG.

8 is a diagram showing an example of a decoder circuit configuration located at a next stage of the predecoder circuit.

9 is a circuit diagram showing an example of a decoder circuit shown in FIG. 8;

Fig. 10 shows a second embodiment of the predecoder circuit according to the present invention when there are two inputs.

FIG. 11 shows a third embodiment of the predecoder circuit of the present invention used in redundancy; FIG.

Fig. 12 shows a fourth embodiment of the predecoder circuit of the present invention using the source drive system.

FIG. 13 is a diagram showing another example of the decoder circuit shown in FIG. 8; FIG.

14 is a circuit diagram showing an example of a conventional predecoder circuit.

15 is a circuit diagram showing another example of a conventional predecoder circuit.

Fig. 16 is a circuit diagram showing still another example of the conventional predecoder circuit.

♠ Explanation of the symbols for the main parts of the drawings.

11 to 18: address ultrashort circuit

21 to 28, 31 to 34: address decoder circuit

41: predecoder circuit

51: decoder circuit

As shown in FIG. 1, the predecoder circuit includes first to fifth Nch transistors N1 to N5 and Pch transistor P1, receives an address signal from an address decoder circuit, and outputs an output signal (/ OUT). )

Here, with reference to FIG. 2, it is assumed that the number of cells per digit is 1024. The external circuit (control circuit) supplies the addresses X1 to X8 to the address initial-stage circuits 11 to 18, and the address first-stage circuits 11 to 18 provide True and Bar signals necessary for decoding. Output In this embodiment, the True and Bar signals output from the address ultrashort circuit 11 are represented by X1T and X1B, respectively, and the True and Bar signals output from the address ultrashort circuit 12 are represented by X2T and X2B, respectively. . Specifically, the True and Bar signals output from the address ultrashort circuit 1n (n is an integer between 1 and 8) are represented by XnT and XnB, respectively. Subsequently, the True signal XnT and the Bar signal XnB are provided to the address decoder circuit.

Referring to FIG. 3, there are actually 20 address decoder circuits, but only 12 address decoder circuits 21 to 28 and 31 to 34 are shown in FIG. Circuits not shown are referred to as missing address circuits below.

As shown in Fig. 3, the address decoder circuit 21 receives the True signals X3T, X2T and X1T, and outputs the address signal Xadd8. Similar to the address circuit 21, the missing address decoder circuit is also provided with the True signals X6T, X5T and X4T, and outputs the address signal Xadd16.

Specifically, as shown in FIG. 3, the True signals X1T to X8T and the Bar signals X1B to X8B include the address circuits 21 to 28, the address decoder circuits 31 to 34, and the missing address decoder circuits. Is provided to the address signals Xadd1 to Xadd20.

4 and 5, the address decoder circuits 21 to 28 and the missing address decoder circuit include the circuit configuration shown in FIG. 4, and the address decoder circuits 31 to 34 are shown in FIG. Circuit configuration.

As shown in FIG. 4, the address decoder circuit 21 includes first to third Pch transistors P1 to P3 and first to third Nch transistors N1 to N3. The node Q is also connected to an output end via an inverter 21a. The address decoder circuit 21 is inverse to the circuit shown in Fig. 14 in the output phase, but its description is omitted because it performs a similar operation.

As shown in FIG. 5, the address decoder circuit 31 includes first and second Pch transistors P1 and P2 and first and second Nch transistors N1 and N2. The node R is also connected to an output end via an inverter 31. Since the operation of the address decoder circuit 31 is similar to that of the address decoder circuit 21 except that there are two inputs, the description thereof is omitted.

Referring to FIG. 6, address signals Xadd1 to Xadd20 are provided to the plurality of predecoder circuits 41. In Fig. 6, only one predecoder circuit 41 is shown for simplicity, but since 1024 cells are assumed, for the address signals Xadd1 to Xadd20, the address signals Xadd1 to Xadd8, the address signal The combination of (Xadd9 to Xadd16) and address signals (Xadd17 to Xadd20) is input to the plurality of predecoder circuits 41, and the number of the predecoder circuits 41 is 8x8x4 = 256.

Returning to Fig. 1, one of the predecoder circuits 41 is shown, where the input address signal is a signal output from the front end address decoder circuit and is represented by a, b and c. Also, as described below, only one predecoder circuit is selected from a plurality of predecoder circuits by a combination of address signals.

The predecoder circuit shown in FIG. 1 includes fourth and fifth Nch transistors N4 and N5 (hereinafter referred to as type NN), which are used as pull-up and pull-down sides at the output of the circuit. As a result, the amplitude of the output signal is lowered and the selection speed is increased as detailed below. In addition, the output signal is fed back to the gate of the Pch transistor P1 used as the normal on Pch transistor, so that the switching speed to the selected state is increased without delaying the switching speed to the non-selected state.

The operation of the predecoder circuit shown in FIG. 1 will be described with reference to FIG. 7. Also, in the output (/ OUT) of Fig. 7, the solid line represents the output of the predecoder circuit shown in Fig. 1 and the broken line shows the output of the conventional predecoder circuit for comparison.

When at least one of the address signals a, b and c (e.g., the address signal a) has the "L" level, the first Nch transistor N1 is turned off, and the node X is The charge is supplied to the "H" level by the power supplied from the power supply Vcc via the normal-on Pch transistor P1.

Since node X is connected to node Y via first and second inverters 41a and 41b, and also to node Z via first inverter 41a, the node ( Y) takes the "H" level, and node Z takes the "L" level. Then, the fourth Nch transistor N4 is turned ON, the fifth Nch transistor N5 is turned OFF, and the Nch short-circuit Vcc-Vtn level (unselected "H") is "/ OUT. &Quot; (wherein, Vtn is the threshold voltage of the Nch transistor).

This output is fed back to the Pch transistor (Pch active load) P1, so that the Nch short (Vcc-Vtn) level voltage is provided to the gate of the Pch transistor P1, so that the conductivity of the Pch transistor P1 is low but in the ON state. Is maintained.

When all the address signals a, b and c are at the "H" level, the first to third Nch transistors N1 to N3 are turned ON. Therefore, the charge of the node X is discharged to GND. In this case, since the conductivity of the Pch transistor P1 is lowered as described above, the charge of the node X is easily discharged via the first to third Nch transistors N1 to N3, and the The potential easily reaches the "L" level.

When node X is at the "L" level as described above, node Y is at the "L" level, and node Z is at the "H" level. Therefore, the fourth Nch transistor N4 is turned off, the fifth Nch transistor N5 is turned on, and the output / OUT is at the GND level. In this case, since the charge can be discharged from the Nch short (Vcc-Vt) level to the GND level, the speed of selection ("L") can be increased as compared with the case where the charge is discharged from Vcc to the GND level.

When the output is fed back to the Pch transistor (Pch active load) P1, the gate of the Pch transistor P1 is provided with a GND level, the conductivity of the Pch transistor P1 is improved and its ON state is maintained.

In this state, even when at least one of the address signals a, b and c (e.g., the address signal a) is at the "L" level, the conductivity of the Pch transistor (Pch active load) P1 is achieved. Is improved. In addition, since the Pch transistor P1 has a normal ON state, the non-selection is not delayed.

Since the Pch active load P1 operates as a normal on Pch transistor as described above, the switching speed from the selected state to the non-selected state is not delayed. Therefore, the gate width of the Pch transistor P1 can be minimized.

Here, referring to FIG. 8, the plurality of predecoder circuits 41 output the predecoder output signals AWL1 to AWL256 as described above. These predecoder output signals AWL1 to AWL256 are supplied to a plurality of decoder circuits 51. In FIG. 8, only one decoder circuit 51 is shown for simplicity, but there are substantially 256 decoder circuits 51. A control circuit (not shown) provides control signals PWD1 to PWD4 to each decoder circuit 51, and each decoder circuit 51 outputs word select signals WORD1 to WORD4. Since word select signals WORD1 to WORD4 are present for each of the predecoder output signals AWL1 to AWL256, either of 256x4 = 1024 cells is selected.

Referring to Fig. 9, the output from only one selected predecoder circuit is input to the decoder circuit 51 of the next stage, and word selection is performed in accordance with the outputs WORD1 to WORD4 of the decoder circuit.

In the decoder circuit 51, when the NN-type transistor is used at the output stage as in the predecoder circuit and the amplitude of the output is low, the output is used as the gate input Vg to the transfer gate of the memory cell during word selection. , Transistor conductivity is degraded. Therefore, the output stage circuit is configured such that the NN type is not used.

The decoder circuit 51 shown in FIG. 9 includes the first to fifth Nch transistors N1 to N5 and the first to fourth Pch transistors P1 to P4. The selected predecoder circuit 41 sends the " L (selection) " level to the decoder circuit 51. Specifically, as shown in FIG. 9, the "H" level is provided to the gate of the fifth Nch transistor N5 via the inverter INV1.

On the other hand, control signals PWD1 to PWD4 are supplied to the first to fourth Nch transistors N1 to N4. Nodes S, T, U, and V are connected to output terminals of word select signals WORD1, WORD2, WORD3, and WORD4 via inverters 51a, 51b, 51c, and 51d. In the decoder circuit 51 shown in Fig. 9, when any one of the control signals PWT1 to PWT4 is selected and becomes the "H (selection)" level, any one of the word selection signals WORD1 to WORD4. Becomes the "H" level. The H level word select signal is used as the gate input to the transfer gate of the memory cell, whereby the memory cell is selected.

In the predecoder circuit, the number of input addresses is not limited to three as shown in FIG. 1, but instead, a circuit having two input addresses as shown in FIG. 10 can be configured in a manner similar to that of FIG. A circuit with four or more addresses can also be constructed in a manner similar to that of FIG.

For example, in the predecoder circuit shown in FIG. 10, when the address signals a and b as the gate inputs to the first and second Nch transistors N1 and N2 have an "H" level, the predecoder The output / OUT of the circuit has an "L" level (selection state).

In addition, as shown in FIG. 11, by connecting the node X to the first Nch transistor N1 via FUSE, the path from the input address signal is interrupted, whereby the circuit is used as redundancy. Can be. Specifically, in the circuit shown in Fig. 11, when FUSE is disconnected, the node X continues to have the "H" level because the Pch active load P1 is an address output from the address decoder circuit. This is because it is in a normal on state regardless of the input voltages of the signals a, b and c.

Then, the node Y is at the "H" level, the node Z is at the "L" level, the output terminal Nch transistor N4 is turned ON, and the Nch transistor N5 is turned OFF. Therefore, Vcc-Vtn (the Vt short level of the Nch transistor) is output as the output / OUT, resulting in an unselected state.

This output is fed back to the Pch active load P1, the conductivity of the Pch transistor is degraded, but the Pch transistor is in a normal on state, and the charge is continuously provided to the node X from the power supply Vcc and the "H" level. Is maintained. As a result, this circuit performs circuit operation so that the output remains unselected.

As can be seen from the above description, when the fuse is disconnected, this circuit always remains in the non-selected state.

Referring to Fig. 12, one input of input from the address decoder circuit (" / C " in this embodiment) is used as the source input. The address signal / C has a phase opposite to that of the other address signals a and b, and is generated in the address decoder circuit so that the "L" level is in an unselected state.

The transistor parasitic capacitance includes a gate capacitance and a diffusion layer capacitance, in which the diffusion layer capacitance is smaller than the gate capacitance in the present embodiment with respect to the gate capacitance and the diffusion layer capacitance. Therefore, for a signal line having a large transistor gate load for the address signal, by the gate input, the capacitive load can be reduced and the speed can be increased.

First, the non-selection state of the predecoder circuit shown in FIG. 12 will be described.

First and second Nch, when the input to the predecoder circuit source (address signal) is set to / c = H (non-selected) level and the remaining input signals are set to a = b = H (selected) level. The transistors N1 and N2 are turned ON, and the electric charge applied from the power supply Vcc via the H (non-selected) level applied to the source of the second Nch transistor N2 and the normal on Pch transistor P1 is applied. Let node X be at the H level.

Then, the node Y is at the H level, the node Z is at the L level, the third Nch transistor N3 at the output terminal is turned on, and the fourth Nch transistor N4 is turned off. The Nch short-circuit (Vcc-Vtn) level (unselected ("H")) is output via / OUT.

When this output is fed back to the Pch active load P1, an Nch short (Vcc-Vtn) level voltage is provided to the gate, and the conductivity of the Pch transistor is degraded but remains ON.

The selection state will now be described.

The gate input signals of the first and second Nch transistors N1 and N2 remain a = b = H (selection), and the source input of the second Nch transistor n2 is / C = L (selection). When set, the first and second Nch transistors N1 and N2 remain in the ON state, the conductivity of the Pch transistor P1 is degraded as described above, and the charge of the node X is first and second. By easily taking the L level via the Nch transistors N1 and N2, the speed can be increased.

When the node X becomes L level, the node Y becomes L level, the node Z becomes H level, the third Nch transistor N3 is turned OFF, and the fourth Nch transistor ( N4) turns ON and / OUT goes GND level. In this case, since the charge can be discharged from the Nch short level (Vcc-Vt) to the GND level, the rate of selection ("L") can be increased as compared with the case where the charge is discharged from Vcc to the GND level.

When this output is fed back to the Pch active load, the GND level is provided to the gate, thus improving the conductivity of the Pch transistor and maintaining the ON state.

Now, a non-selection state different from the above-described non-selection state will be described.

The input to the source of the second Nch transistor N2 is held at / c = L (selection), and at least one of the inputs to the gates of the first and second Nch transistors N1 and N2 is L (non- Selection) (e.g., when the address signal a = L), the path between the node X and the source of the second Nch transistor N2 is blocked. On the other hand, since the Pch active load P1 having improved conductivity is kept in the ON state, switching to non-selection is not delayed, and charges to the node X via the Pch active load P1 from the power supply Vcc. Is provided, the node X is at the H level.

Therefore, the node Y is at the "H" level, the node Z is at the L level, the third Nch transistor N3 is turned ON, and the fourth Nch transistor N4 is turned OFF. do. As a result, the Nch short (Vcc-Vt) level (unselected "H") is output to / OUT.

When this output is fed back to the Pch active load P1, a voltage of Nch short-circuit level is provided to the gate, so that the conductivity of the Pch transistor P1 is degraded but the ON state is maintained.

The above-described operation is the same as the unselected state in which all inputs to the gates of the first and second Nch transistors N1 and N2 are H (selection), and input to the source of the second Nch transistor N2. Is / c = H (not optional).

Since the Pch active load P1 operates as a normal on Pch transistor as described above, the transition from the selected state to the unselected state is not delayed, and the gate width of the Pch transistor P1 can be minimized.

In addition, by inputting a signal line with a large transistor gate load as an input to the source of the second Nch transistor N2, the capacitance load can be reduced, and the efficiency of speed increase is large.

Similar to the case where the source driving system is used for the predecoder circuit as shown in FIG. 12, the source driving system may also be used for the decoder circuit shown in FIG. 13.

When the source driving system shown in the predecoder circuit of Fig. 12 is used in the decoder circuit shown in Fig. 9, the output during the non-selection continues to have the Nch short (Vcc-Vtn) level, and the through current of the decoder circuit. It flows to the inverter circuit INV1. However, when the decoder circuit of the source driving system is used as shown in Fig. 13, the through current is cut off. In addition, as shown in FIG. 12, for signal lines having a large transistor gate load for the input signal, by applying a source input instead of applying a gate input, the capacitive load can be reduced and the operating speed can be increased. have.

Here, Table 1 shows a relative comparison of the operating speeds of the predecoder circuits (FIGS. 14 and 16) of the prior art to the operating speeds of the predecoder circuits (FIG. 12) of the present invention.

type Selection (unit: ns) No selection (unit: ns) 14 0.00 0.00 Figure 16 -0.20 -0.60 Figure 12 -0.35 -0.60

As shown in Table 1, in the predecoder circuit shown in Fig. 12, in comparison with the circuits shown in Figs. 14 and 16, a speed increase of 0.15 ns is selected on the selected side without delaying switching to non-selection. Is realized. For modern memory products, the operating frequency is high speed, and the speed of 0.1 ns is worth the speed of several to tens of percent of the cycle width.

As described above, according to the present invention, there is an effect that the amplitude of the output can be lowered and the selection speed can be increased. Also, by feeding back the Nch short (Vcc-Vtn) level to the gate of the Pch active load, operating the Pch active load as a normally on Pch transistor lowers the conductivity of the transistor during non-selection, thus making the transition from non-selection to selection at high speed. It can be performed efficiently.

Also, in the present invention, during the selection, since the GND level is fed back to the gate of the Pch active load, the conductivity of the Pch transistor is improved. During the transition from selection to non-selection, the switching is not delayed.

As described above, the present invention provides the effect that the switching speed to the selected state can be improved without delaying the switching speed to the non-selected state.

It is apparent that the present invention is not limited to the above embodiments, and other modifications may be made within the spirit and scope of the present invention.

Claims (12)

A decoder circuit for decoding a plurality of input address signals and outputting the decoded signals to an output terminal, A switch circuit that receives the address signal and connects a node to a ground line or blocks the node from the ground line according to the plurality of address signals; And A p-channel transistor providing a power supply voltage to said node, The gate electrode of the p-channel transistor is connected to the ground line when the node is connected to the ground line, and receives a voltage having a predetermined level that is halfway between the level of the power supply voltage and the ground line when the node is disconnected from the ground line. , And the decoded signal varies according to the voltage level of the node. 2. The decoder circuit of claim 1, wherein when all signals of the plurality of address signals are at a high level, the node and the decoded signal are at a low level. The decoder circuit of claim 1, wherein the gate electrode of the p-channel transistor receives the decoded signal. 2. The apparatus of claim 1, further comprising first and second inverters and first and second n-channel transistors, wherein the input terminals of the first inverter are connected to the node, An output terminal is connected to an input terminal of the second inverter and a gate electrode of the second n-channel transistor, and an output terminal of the second inverter is connected to a gate electrode of the first n-channel transistor; And the drain electrode of the first n-channel transistor and the source electrode of the second n-channel transistor are connected to the output terminal, and the source electrode of the first n-channel transistor receives the power supply voltage. And the drain electrode of the second n-channel transistor is connected to the ground line. The decoder circuit of claim 4, wherein the drain electrode of the first n-channel transistor is connected to the gate electrode of the p-channel transistor. 2. The switch circuit of claim 1, wherein the switch circuit comprises a plurality of cascaded n-channel transistors, wherein each gate electrode of the cascaded n-channel transistor receives each one of the plurality of address signals. A decoder circuit characterized by the above-mentioned. 7. The decoder circuit of claim 6 wherein the plurality of cascaded n-channel transistors connect the node to a ground line. 7. The decoder circuit of claim 6 wherein the plurality of cascaded n-channel transistors couple the node to terminals, the terminal receiving an inverted signal of an address signal. The decoder circuit of claim 1, further comprising a fuse between the node and the switch circuit. The decoder circuit of claim 1, wherein the decoded signal is input to another decoder circuit, and the another decoder circuit receives the decoded signal and a control signal and outputs a word line selection signal. The decoder circuit of claim 10, wherein the word line select signal selects a word line of a memory cell array in a semiconductor memory device. 2. The decoder circuit of claim 1, wherein the plurality of address signals are generated from a plurality of external input address signals by an address decoder circuit.