KR20010006057A - Class D Amplifier With Reduced Clock Requirement And Related Methods - Google Patents

Abstract

A class D amplifier includes a separation circuit for separating a pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; A PCM / PWM converter for converting L MSB signals to PWM signals; And an LSB processor for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal. The PCM input signal may be an N-1 bit PCM magnitude signal. The amplifier includes a sine and magnitude extraction circuit for extracting a sine bit signal and an N-1 bit size signal from the N bit 2 complementary PCM input signal. In addition, the class D amplifier includes a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal, respectively, to control the polarity and the on time. PCM / PWM converters include symmetric PCM / PWM converters; Trailing edge PCM / PWM converter; And a leading edge PCM / PWM converter.

Description

Class D Amplifier With Reduced Clock Requirement And Related Methods

Amplifiers are widely used in many electronic devices to increase the input signal level to the desired output level. The class D amplifier includes an active element used as an on-off switch, and a change in output power is achieved by pulse width modulation. Class D amplifiers may be used in radio broadcast transmitters and audio amplifiers. For example, due to the very high switching efficiency of power metal-oxide-field effect transistors (MOSFETs), they can be used in Class-D audio amplifiers that produce high-fidelity signals in relatively compact, high-performance circuits.

A typical digital input Class D amplifier 10 is shown in FIG. The amplifier 10 includes a digital format converter 11 for receiving an input signal of a standard type. A sample rate converter 12 converts the output of the digital format converter for input to a pulse code modulation (PCM) / PWM converter 13. The output of the PCM / PWM converter 13 is coupled to the illustrated level shifter 14, the bridge, and ultimately the transducer 16, for example a loudspeaker. Reference numeral 17 shows a number of possible feedback paths for the amplifier 10.

Unfortunately, serious difficulties arise in converting high resolution PCM signals into corresponding high resolution PWM signals. This is because the DC content increases in a one-to-one relationship as the pulse width increases. Each individual pulse has a synchronous (x) frequency response. If the pulse repetition number is high enough, the low pass filter essentially passes only the dc component of each pulse and facilitates the transition from one dc level to another as the dc value changes as a function of time. Since this system is a sample time system, the pulse width is quantized with time as shown in the plot graph of FIG. 2, where P1-P5 is the pulse shown and upper plot 18 shows the pulse resolution clock edge. This PWM width quantization goes directly to dc amplitude quantization. There is a practical limit to the pulse resolution clock 18, which limits the pulse width quantization. This in turn places inherent limitations on the pulse width resolution that limits the total harmonic distortion (THD) of the output signal.

For example, assuming 350KHz pulse repetition, this iteration is such that the lowpass filter at the amplifier's output is not high enough to prohibit high pulse resolution clocks for low resolution, while only passing close dc signal components. High enough to support the family. The high resolution is quite different. For example, if it is desirable to preserve 16 bits of accuracy via PCM / PWM conversion, the required pulse repetition clock rate is 350 KHz × 2 ¹⁶ or 23 GHz. This high clock speed is impractical.

The prior art approach to overcome this difficulty is to add a noise shaper or filter 21 upstream of the processing chain of the PCM / PWM converter 13 of the circuit 20 as shown in FIG. 3. . Since the noise shaper 21 reduces the required resolution of the PCM signal, it reduces the time resolution of the subsequent PWM signal. The noise shaper 21 does this by ultimately weighting the quantization noise towards the high frequency that is blocked, and uses high frequency noise to dither important signals through a low resolution PCM / PWM converter 13. do. The input signal has N bits of resolution and the output signal has M bits of resolution, where N is greater than M. The ability of the noise shaper 21 to shape noise is based on the fact that adjacent input samples are highly correlated. This correlation is supported by previous interpolation of the sample rate conversion block 12.

The output signal-to-noise ratio (SNR) can be increased by increasing the oversampling degree of the input signal or by increasing the order of the noise shaping filter 21. Unfortunately, increasing the degree of oversampling drastically increases the overall system complexity, while increasing the order of the noise shaping filter by more than 3 degrades the performance improvement at an appropriate oversampling rate. One cause of the increased system complexity is that interpolation filter complexity must be increased.

Another difficulty arises because increasing oversampling increases the number of PWM iterations. Thus, to maintain the same pulse resolution clock rate, less than one bit is allowed in the quantizer for each of the two factors where the sampling rate is increased. This may mean that for a third-order noise shaping filter, a net noise floor gain of about 1.6 bits is realized for each of the two factors at which the sampling rate is increased and assumes ideal interpolation.

However, another difficulty with conventional noise shaping filter 21 is based on dithering noise that must be performed through PCM / PWM converter 13 to reduce the required PWM timer resolution. This dithering may later be removed with the low pass filter 22. However, there may be a perceptible impact on sound quality resulting from dithering.

The present invention relates to electronic circuits and devices, in particular class D amplifiers and related methods.

1 is a schematic block diagram of a class-D amplifier according to the prior art.

FIG. 2 is a plot of PWM pulse and pulse resolution clock signal for the class D amplifier of the prior art of FIG.

3 is a schematic block diagram of a class-D amplifier including a noise shaper according to the prior art.

4 is a schematic block diagram of an embodiment of a class D amplifier according to the present invention;

5 is a timing diagram of a signal generated by the embodiment of the present invention shown in FIG.

6 is a schematic block diagram of another embodiment of a class D amplifier according to the present invention;

7 is a timing diagram of a signal generated by the embodiment of the present invention shown in FIG.

8 is a timing diagram of a signal generated by the modification of the embodiment of the present invention shown in FIG.

<Explanation of symbols for main parts of drawing>

10: amplifier 20: circuit 30,30 ': class D amplifier

The present invention

Input means for receiving an N-bit two's complement pulse code modulation (PCM) input signal;

Sine and magnitude extracting means for extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2's complement PCM input signal;

Separating means for separating the N-1 bit size signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal;

A PCM / PWM converter for converting L MSB signals to PWM signals;

LSB processing means for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal; And

And a class D amplifier including a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal.

The object of the present invention is

Separating means for separating the pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal;

A PCM / PWM converter for converting L MSB signals to PWM signals; And

Reduced or eliminated requirements for class D amplifiers and noise shaping circuits including LSB processing means for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal. It is to provide a related method having a matter. In particular, the PCM input signal may be an N-1 bit PCM magnitude signal. Accordingly, the amplifier preferably further includes sine and magnitude extraction means for extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2 complementary PCM input signal. In addition, the class D amplifier may include a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal, respectively, to control the polarity and the on time.

PCM / PWM converters include symmetric PCM / PWM converters; Trailing edge PCM / PWM converter; And a leading edge PCM / PWM converter. Thus, the LSB processing means preferably includes means for cooperating with each type of PCM / PWM converter.

LSB processing means includes a sawtooth generator for generating a sawtooth wave signal; A digital-to-analog converter (DAC) for converting a signal associated with a K LSB magnitude signal into an analog signal; And a comparator for generating a threshold signal based on the comparison of the sawtooth signal with the analog signal. The LSB processing means may further include logic means for generating a PWM control signal based on the threshold signal and the PWM signal. The amplifier also includes a reference clock connected to the sawtooth generator; And clock extraction means operatively connected between the sawtooth generator and the PCM / PWM converter for synchronous conversion. In addition, the present invention comprises the steps of separating a pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; Converting the L MSB signal to a PWM signal; And proportionally changing the PWM signal based on the K LSB signal to define the PWM output control signal, wherein the PCM input signal is an N-1 bit PCM magnitude signal; And extracting a sine bit signal and an N-1 bit size signal from the N bit 2's complement PCM input signal, and operating a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal. It includes a method for operating a class D amplifier.

The method of the present invention is for operating a class D amplifier. The method includes separating a pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; Converting the L MSB signal to a PWM signal; And proportionally changing the PWM signal based on the K LSB signal to define the PWM output control signal. This PCM input signal may be an N-1 bit PCM magnitude signal. Thus, the method comprises the steps of: extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2 complementary PCM input signal; The method may further include operating a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal.

The present invention will now be described with reference to the accompanying drawings by way of example.

Like numbers refer to like elements throughout.

4 and 5, the first embodiment of the class D amplifier 30 includes an input means 32 for generating the N-bit 2 complementary PCM signal in the illustrated embodiment. The present invention also predicts differently from the two's complement input. The first embodiment of the class D amplifier 30 is also configured for symmetric modulation for the purpose of illustration.

The N-bit PCM input signal is first processed urbanly by a sine and magnitude extraction circuit 34 that generates a sinusoidal bit signal, and the N-1 bit magnitude signal will also be readily understood by those skilled in the art. . Downstream from the sine and magnitude extraction circuit 34, separation means 35 are provided for separating the N-1 bit PCM signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal. The sine bit signal is supplied to the switch driver 45, where the final PWM signal interval is properly formatted. The magnitude of L and K is determined based on the tradeoff between the complexity of the circuit used to act on two words.

Class D amplifier 30 also includes a PCM / PWM converter 37 schematically shown for converting the L MSB signal. The PCM / PWM converter 37 may include one or more counters that are used for the L dependent value clocked by the pulse resolution clock and depend on the type of preset PWM. This counter turns the modulation pulses on or off at a predetermined time depending on L and the number of pulse repetitions. In this embodiment, the counter of the PCM / PWM converter 37 is driven by a clock signal synchronized with the sawtooth generator 42 used to process the K LSB word or signal. The PCM / PWM converter 37 generates a PWM signal.

In addition, the amplifier 30 processes LSB to proportionally change the PWM signal from the PCM / PWM converter 37 based on the K LSB signal to limit the PWM output control signal input to the switch driver 45. Means; The switch driver 45 responds to the extracted sine bit signal and the PWM output control signal to control the polarity and the on time for the switch driver, respectively. The switch drive 45 may be coupled to the power switch 47 shown schematically, which in turn may be coupled to a transducer, such as the audio speaker 48 shown.

PCM / PWM converters include symmetric PCM / PWM converters; Trailing edge PCM / PWM converter; And a leading edge PCM / PWM converter. Thus, the LSB processing means preferably includes means for cooperating with each type of PCM / PWM converter. For the class D amplifier 30, the PCM / PWM converter 37 is a symmetrical converter.

LSB processing means includes a sawtooth generator 42 for generating a sawtooth wave signal; A digital-to-analog converter (DAC) 43 for converting a signal associated with a K LSB magnitude signal into an analog signal; And a comparator 44 for generating a threshold signal based on the comparison of the sawtooth signal with the analog signal. The LSB processing means may further include logic means for generating a PWM control signal based on the threshold signal and the PWM signal. In addition, the class D amplifier 30 includes a reference clock 52 shown connected to the sawtooth generator 42; And clock extraction means 53 operatively connected between the sawtooth generator and the PCM / PWM converter 37 for synchronous conversion.

For the illustrated embodiment of symmetric PWM, the LSB processing result is enabled one clock edge before the start of the pulse resulting from the MSB process, and one clock edge is disabled after the pulse is turned off by the MSB process. This is illustrated by blocks 61 and 62 in FIG. This figure also shows the sawtooth wave 67 generated in the sawtooth generator 42. For example, if all MSB size bits are zero, the LSB processing circuitry is enabled for only two clock cycles.

The K LSB signal of the N-1 PCM signal is used to drive the analog threshold circuit, which is a PWM pulse with a pulse resolution clock time immediately before or after the start or end of the PCM / PWM converter 37 generation pulse. It is used to turn on and off. The actual on and off time is directly proportional to the LSB PCM value and will be readily understood by those skilled in the art. Thus, the combination of sine bit, MSB and LSB signal processing chains provides accurate N bit PCM / PWM conversion.

Class D amplifier 30 will be understood with reference to the following example. Assuming a pulse repetition number of 352.8 KHz with a dead time of 177 ns (1/16 of a pulse repetition period), the maximum pulse duration is 15/16 × 1 / 352.8 KHz = 2.657 ㎲. In addition, assuming that L is selected as 7 bits, the pulse resolution clock frequency is 48.16896 MHz and the clock period is 20.76 ns. Assume the desired pulse width is 238.74ns or 11.5 clock periods, and assume that this pulse is negative. The input binary value is 1111010010000000. As described above, the sine bit is stripped off and sent to the switch drive 45. Thus, when the pulse output is off, the output of the class D amplifier will be zero volts, and when the pulse output is turned on, the output of the class D amplifier will be V volts. The sine extraction circuit 34 accepts the input size and sends 0001011 to the PCM / PWM converter 37 and 10000000 to the divider 65.

Since the pulse width provided by the LSB needs to be equally divided between the leading and trailing pulse edges, the divider 65 is used for symmetrical PWM. This division may be considered merely schematic and may be performed by threshold scaling.

The PCM / PWM converter 37 turns on one pulse for 11 clock coefficients, as indicated by the vertical mark 66 in FIG. Also, as shown in Fig. 5, the task of LSB processing generates 3/4 outputs of the method in the first enable clock period, and turns 1/4 outputs of the method off to the last enable clock.

The sawtooth wave 67 used in this example rises to the leading edge. The K-bit digital word is the first two by the circuit 71 because the analog comparator 44 compares the converted version of the K-bit PCM signal with the sawtooth wave, and the smaller the PCM value, the earlier the comparator should trigger. It's conservative. The two's complement output is used only during the leading edge enable period. Because of the special case where all K bits are equal to zero, the two's complement performance signal is used to disable the output of comparator 44 through the inverter 73 and AND gate 74 shown. In other words, if a K-bit value of zero is received, the LSB processing circuit should not operate. However, since the complement value of K bit 2 of 0 is 0, and this circuit triggers at the beginning of the clock signal cycle, a disable signal is required.

During the trailing edge enable period, the output of comparator 44 is inverted to compensate for leading edge rise on sawtooth wave 67. FIG. 5 describes that the sawtooth wave 67 is below the comparator threshold during the period when the LSB processing circuit needs to enable the trailing portion of the output pulse. It also describes the case when the LSB is equal to zero. Of course, the output of the two's complement circuit 71 is passed to the low resolution DAC 43, where the PCM signal is converted to analog format, whether enabled (repaired) or disabled (passed). The output of the DAC 43 may require some filtering to smooth the output signal. Just as an output filter is not used for signal reconstruction, but for signal accuracy, the output filter does not have the same binding force as a typical DAC anti-imaging filter.

The analog signal is supplied to the comparator 44 and compared to the linearly increasing waveform 67 of this embodiment shown. When one input is greater than or equal to another signal, an output signal is produced. The leading edge enable signal from the PCM / PWM converter 37 is also coupled to the exclusive OR gate 81 through the inverter 82 shown. The exclusive OR gate 81 also receives the output of the comparator 44 as an input.

The combination of DAC 43, comparator 44, and sawtooth generator 42 described herein can be replaced with any device / circuit that generates a delayed output signal from a time reference, where this delay Is linearly proportional to the input digital value.

Once the output of comparator 44 is gated with the above enabling signal, it is ORed with the output of PCM / PWM converter 37 at OR gate 77 shown to form the desired final pulse width. Assume that two input signals for the OR gate 77 are synchronized to the clock extraction circuit 53. The switch driver 45 transforms the PWM signal into a format compatible with the actual power switch 47. The power switch 47 may be coupled to a transducer such as the loudspeaker 48 shown through the low pass filter 49 shown.

6 and 7, a second embodiment of a class D amplifier 30 'will now be described. This embodiment includes similar parts as described above and indicated by one prime notation. This embodiment is also a description that points to two's complement input. This embodiment of a class D amplifier 30 'also assumes trailing edge modulation and three pulses.

The N bit 2's complement PCM signal is supplied to the sine and magnitude extraction circuit 34 '. This signal is supplied to the switch drive 45 '. This magnitude output is divided into N-bit MSB words and K-bit LSB words by an isolation circuit 35 'as an N-1 bit size value. The selection of K and L may be made based on tradeoff considerations between circuit complexity in the various parts of class D amplifier 30 '.

The truncated PCM size value L is supplied to the L-bit PCM / PWM converter 37 '. The counter of the converter 37 'is driven by a clock synchronized with the waveform generator used to process the LSB word as shown in the timing diagram of FIG. For this illustrated embodiment, the trailing edge PWM is used to disable the LSB processing result to one clock edge after the pulse is turned off by MSB processing. This is understood with reference to block 80 of FIG. If all MSB size bits are zero, the LSB processing circuit is enabled for only one clock period.

A K LSB signal of N-1 bit PCM size is used to drive an analog threshold circuit, which in turn PWMs the pulse resolution clock period immediately after the end of the pulse generated by the PCM / PWM converter 37 '. Used to turn off the pulse. The actual off time is directly proportional to the LSB PCM value. In short, the combination of sine bit, MSB and LSB signal processing chains provides accurate N-bit PCM / PWM conversion.

For example, assuming a pulse repetition number of 352.8 KHz having a non-operation time of 177 ns (1/16 of the pulse repetition period), the maximum pulse duration is 15/16 x 1 / 352.8 KHz = 2.657 kHz. In addition, assuming that L is selected as 7 bits, the pulse resolution clock frequency is 48.16896 MHz and the clock period is 20.76 ns.

In addition, assume a desired pulse width of 238.74 ns or 11.5 clock periods, and assume that this pulse is positive. The input binary value is 0000101110000000. The sine bit is stripped off and sent to the switch drive 45 '. Thus, when the pulse output is off, the output of the class D amplifier will be zero volts, and when the pulse output is turned on, the output of the amplifier will be V volts. The sine and magnitude extraction circuit 34 'and separation circuit 35' send 0001011 to the PCM / PWM converter 37 'and 10000000 to the DAC 43' of the LSB processing circuitry. The output of the DAC 43 'may be advantageous to do some filtering to smooth the output signal.

The analog signal is supplied to a comparator 44 'and compared to a linearly increasing waveform as shown in FIG. When the input from the DAC 43 'is greater than or equal to the sawtooth waveform 67', an output signal is produced. The combination of DAC 43 ', comparator 44', and sawtooth generator 42 'can be replaced by an equivalent circuit that generates a delayed output signal from a time reference, where this delay is linearly proportional to the input digital value. do.

In the illustrated embodiment and example, the PCM / PWM converter 37 'turns on one pulse for 11 clock coefficients and enables the LSB processing circuit output to one clock edge after 11 clock cycles. The LSB process generates half the output of this method in the first enable clock time as shown in FIG. 7, and turns off the output.

Once the output of the comparator 44 'is gate controlled with the enabling signal via the AND gate 81 described above, it is ORed with the output of the PCM / PWM converter 37' at the OR gate 82, and the desired final The pulse width is formed. Assume that two input signals for the OR gate 82 are synchronized with the clock extraction circuit. This result signal is supplied to the switch drive 45 '. These devices, designated one prime and not described in detail with reference to FIG. 6, are described above fully in connection with FIG. 4, and therefore, these devices will not be described further.

Further referring to the timing diagram of Fig. 8, another embodiment of a class D amplifier 30 " will now be described. This embodiment refers to leading edge modulation. This circuit represents a circuit similar to that shown in Fig. 6. However, for leading edge modulation, the sawtooth generator generates a sawtooth wave 85 that decreases from the leading edge as shown in Figure 8. In this embodiment, the LSB processing circuit is a PCM / PWM The converter 37 'is enabled one clock cycle before triggering the start of the pulse.The LSB enable area is shown by box 86 in Figure 8. As can be readily determined in Figure 8, the LSB circuit is a DAC 43. Fire when the voltage output of ') is greater than the counterpart of the sawtooth wave 85.

The method aspect of the invention is for operating a class D amplifier. This way

Separating the pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; Converting the L MSB signal to a PWM signal; And proportionally changing the PWM signal based on the K LSB signal to define the PWM output control signal. The PCM input signal may be an N-1 bit PCM magnitude signal. Therefore, the method extracts a sine bit signal and an N-1 bit size signal from the N bit 2 complementary PCM input signal, and operates a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal. It may also be included.

A class D amplifier includes a separation circuit for separating a pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; A PCM / PWM converter for converting L MSB signals to PWM signals; And an LSB processor for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal. The PCM input signal may be an N-1 bit PCM magnitude signal. The amplifier includes a sine and magnitude extraction circuit for extracting a sine bit signal and an N-1 bit size signal from the N bit 2 complementary PCM input signal. In addition, the class D amplifier includes a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal, respectively, to control the polarity and the on time. PCM / PWM converters include symmetric PCM / PWM converters; Trailing edge PCM / PWM converter; And a leading edge PCM / PWM converter.

As described above, according to the present invention, a class-D amplifier having a reduced clock demand and a related method may be provided.

Claims (11)

Input means for receiving an N-bit two's complement pulse code modulation (PCM) input signal; Sine and magnitude extracting means for extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2's complement PCM input signal; Separating means for separating the N-1 bit size signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; A PCM / PWM converter for converting L MSB signals to PWM signals; LSB processing means for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal; And A class D amplifier comprising a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal. The method of claim 1, The PCM / PWM converter is a symmetric PCM / PWM converter; Said LSB processing means comprises means for cooperating with said symmetrical PCM / PWM converter. The method of claim 1, The PCM / PWM converter is a trailing edge PCM / PWM converter; The LSB processing means comprises means for cooperating with the trailing edge PCM / PWM converter. The method of claim 1, The PCM / PWM converter is a leading edge PCM / PWM converter; The LSB processing means comprises means for cooperating with the leading edge PCM / PWM converter. The method of claim 1, The LSB processing means Sawtooth generator for generating sawtooth signal; A digital-to-analog converter (DAC) for converting a signal associated with the K LSB signal into an analog signal; And A comparator for generating a threshold signal based on the comparison of the sawtooth signal with the analog signal, The LSB processing means further includes logic means for generating a PWM output control signal based on the threshold signal and the PWM signal, wherein the logic means comprises an "OR" gate. The method of claim 5, A reference clock connected to the sawtooth generator; And clock extraction means operatively connected between the sawtooth generator and the PCM / PWM converter to synchronize with the conversion of the PCM / PWM converter, The PCM / PWM converter includes first enable means for generating a first enable signal for use by the logic means, and the LSB processing means divides by 2 for dividing the K LSB magnitude signal by two. Means, and two's complement means connected between said dividing means by said two and said DAC, said two's complement means having a carry output, said logic means being connected to a carry output. A first inverter, wherein the PCM / PWM converter comprises second enable means coupled to the second repair means and the logic means to generate a second enable signal, the logic means being a second enable signal; Class D amplifier comprising a second inverter for receiving a. The method of claim 1, The switch drive device has a controllable polarity corresponding to the extracted sine bit signal, and the switch drive device has an on time corresponding to a PWM output control signal with at least one power switch connected to the switch drive device. Class D amplifier comprising a. Separating means for separating the pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; A PCM / PWM converter for converting L MSB signals to PWM signals; And LSB processing means for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to limit the PWM output control signal, The PCM input signal is an N-1 bit PCM magnitude signal, And sine and magnitude extraction means for extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2's complement PCM input signal, and a switch driving device corresponding to the extracted sine bit signal and PWM output control signal. , And the switch driving device has a controllable polarity corresponding to the extracted sine bit signal and an on time corresponding to the PWM output control signal. Sine and magnitude extracting means for extracting a sine bit signal and an N-1 bit magnitude signal from the N bit 2's complement PCM input signal; Separating means for separating the N-1 bit size signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; A PCM / PWM converter for converting L MSB signals to PWM signals; LSB processing means for proportionally changing the PWM signal from the PCM / PWM converter based on the K LSB signal to define a PWM output control signal; Wherein the LSB processing means includes a sawtooth generator for generating a sawtooth wave signal; A digital-to-analog converter (DAC) for converting a signal associated with a K LSB magnitude signal into an analog signal; A comparator for generating a threshold signal based on the comparison of the sawtooth wave signal with the analog signal; Logic means for generating a PWM output control signal based on the threshold signal and the PWM signal; And clock extraction means operatively connected between the sawtooth generator and the PCM / PWM converter to synchronize with the conversion of the PCM / PWM converter; And A switch driving device corresponding to the extracted sine bit signal and the PWM output control signal, The PCM / PWM converter is a symmetric PCM / PWM converter; The LSB processing means comprises means for cooperating with the symmetric PCM / PWM converter, The PCM / PWM converter is a trailing edge PCM / PWM converter; The LSB processing means comprises means for cooperating with the trailing edge PCM / PWM converter. Separating the pulse code modulation (PCM) signal into a K least significant bit (LSB) signal and an L most significant bit (MSB) signal; Converting the L MSB signal to a PWM signal; And proportionally changing the PWM signal based on the K LSB signal to define the PWM output control signal, wherein the PCM input signal is an N-1 bit PCM magnitude signal; Extracting a sine bit signal and an N-1 bit size signal from the N bit 2's complement PCM input signal; And operating a switch driving device corresponding to the extracted sine bit signal and the PWM output control signal. The method of claim 10, The converting step includes symmetrically converting the L MSB signal into a PWM signal, wherein the converting step includes a class D amplifier including a transform using a trailing edge transform and a transform using a leading edge transform. How to get it working.