KR20010004573A - Liquid crystal panel having test pattern - Google Patents

Liquid crystal panel having test pattern Download PDF

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Publication number
KR20010004573A
KR20010004573A KR1019990025265A KR19990025265A KR20010004573A KR 20010004573 A KR20010004573 A KR 20010004573A KR 1019990025265 A KR1019990025265 A KR 1019990025265A KR 19990025265 A KR19990025265 A KR 19990025265A KR 20010004573 A KR20010004573 A KR 20010004573A
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South Korea
Prior art keywords
liquid crystal
crystal panel
electrode
test pattern
panel
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KR1019990025265A
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Korean (ko)
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심민수
박지연
박규창
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김영환
현대전자산업 주식회사
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Priority to KR1019990025265A priority Critical patent/KR20010004573A/en
Publication of KR20010004573A publication Critical patent/KR20010004573A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE: A liquid crystal panel with a test pattern is provided to improve a yield and an image quality of the liquid crystal panel by measuring a holding ratio using an actual process parameter. CONSTITUTION: A liquid crystal panel with a test pattern consists of a lower substrate and an upper substrate. The lower substrate is formed with a signal line and an electrode portion using a transparency electrode film, and is formed with a pad portion on the left side thereof for applying a signal voltage to the lower substrate and the upper substrate. The upper substrate is formed with an electrode portion using the transparency film to consistent with the electrode portion of the lower substrate. The electrode portions of the upper substrate and the lower substrate is consistent at the vicinity of a seal, a liquid crystal injection opening, and a center portion of the panel. Therefore, since the electrode portions of the substrates is positioned at the vicinity of the seal, the liquid crystal injection opening, and the center portion of the panel, A liquid crystal layer is charged with the signal voltage by applying the signal voltage to the upper substrate and the lower substrate via the electrode portion of the pad portion

Description

테스트 패턴을 구비한 액정패널{Liquid crystal panel having test pattern}Liquid crystal panel having test pattern

본 발명은 테스트 패턴을 구비한 액정패널에 관한 것으로, 보다 상세하게는 실제 액정패널에서의 셀(cell) 공정과 동일한 공정을 갖는 패널을 설계하여 실제 공정변수에 의한 전압보지율을 측정함으로써 수율 및 액정패널의 화면품질을 향상시킨 테스트 패턴을 구비한 액정패널에 관한 것이다.The present invention relates to a liquid crystal panel having a test pattern, and more particularly, by designing a panel having the same process as a cell process in an actual liquid crystal panel and measuring the voltage holding ratio according to actual process variables. The present invention relates to a liquid crystal panel having a test pattern for improving the screen quality of the liquid crystal panel.

일반적으로, 액정셀(liquid crystal cell)은 두개의 유리기판으로 구성되고 그 사이에 액정이 주입되어 있는 액정표시소자의 구성품이다. 두 유리기판 안쪽에는 화소를 구성하는 투명전극이 있으며, 그 위에 액정분자를 한 방향으로 배향시키기 위한 배향막이 있다. 능동행렬 액정 디스플레이는 아래 기판에 능동소자인 다이오드 또는 트랜지스터가 화소의 측면에 형성되어 있다. 컬러 액정 표시소자는 윗 기판에 컬러를 표시할 수 있도록 컬러 필터가 장착되어 있다. 컬러 필터는 투명전극과 유리기판 사이에 놓이며 유리기판에 안료분산법, 염색법 등으로 제작된다. 유리기판 사이에는 액정이 주입될 수 있도록 일정한 간격이 유지되며 넓은 면적의 표시소자인 경우에는 스페이서에 의해서 그 간격이 유지된다. 그 공간에 액정이 주입되어 배향된다. 셀의 측면에는 투명전극과 연결된 전극 패턴이 있으며 이 패턴을 통해서 외부 전압이 액정에 전달된다. 능동행렬 액정 디스플레이에는 능동소자를 구동하기 위한 패턴들이 형성되어 있으며 이 패턴들을 통해서 능동소자가 구동되며 동시에 액정에 외부 전압이 인가된다.In general, a liquid crystal cell is a component of a liquid crystal display device composed of two glass substrates and liquid crystal injected therebetween. Inside the two glass substrates are transparent electrodes constituting pixels, and there is an alignment layer thereon for aligning liquid crystal molecules in one direction. In an active matrix liquid crystal display, a diode or a transistor, which is an active element, is formed on a side of a pixel on a lower substrate. The color liquid crystal display device is equipped with a color filter to display color on the upper substrate. The color filter is placed between the transparent electrode and the glass substrate, and is produced by pigment dispersion, dyeing, or the like on the glass substrate. A constant gap is maintained between the glass substrates so that liquid crystal can be injected, and in the case of a display device having a large area, the gap is maintained by a spacer. The liquid crystal is injected and aligned in the space. The side of the cell has an electrode pattern connected to the transparent electrode through which the external voltage is transmitted to the liquid crystal. In the active matrix liquid crystal display, patterns for driving the active elements are formed. The active elements are driven through the patterns, and at the same time, an external voltage is applied to the liquid crystal.

도 1a 및 도 1b는 종래 기술에 의한 전압보지율 측정을 위한 상하판 셀을 도시한 것이고, 도 2는 종래 기술에 의한 상하판 셀이 합착된 상태를 도시한 것이다.1A and 1B illustrate upper and lower cells for measuring a voltage holding ratio according to the prior art, and FIG. 2 illustrates a state in which the upper and lower cells according to the prior art are bonded.

여기서, 전압보지율(holding ratio)이라함은 박막 트랜지스터(Thin Film Transistor ; 이하 'TFT'라 칭함)의 Ioff 특성, 기생 커패시턴스, 배향막과 LC의 유전율, 비저항 변화등에 의한 동일 프레임(frame)내의 신호전압의 변화비를 나타내는 중요한 요소이다.Here, the voltage holding ratio refers to a signal in the same frame due to Ioff characteristics, parasitic capacitance, dielectric constant of the alignment film and LC, and resistivity change of a thin film transistor (hereinafter, referred to as TFT). It is an important factor that shows the ratio of change of voltage.

종래에서는 전압보지율의 측정을 위해서 상하판 각각에 아이티오(ITO ; 투명전극)가 코팅(coating)된 작은 크기의 단위 셀을 제작하여 액정 주입후 상하판에 신호전압을 인가하여 액정에 그 신호전압까지 충전되게 한 다음, 충전된 액정 커패시터에서 누설되는 양만큼을 모니터함으로써 초기 신호전압과 최종 신호의 비로 전압보지율을 측정하였다.Conventionally, in order to measure the voltage holding ratio, a small unit cell having an ITO (ITO) coated on each of the upper and lower plates is manufactured, and a signal voltage is applied to the upper and lower plates after injecting the liquid crystal to give the signal to the liquid crystal. The voltage holding ratio was measured by the ratio of the initial signal voltage and the final signal by monitoring the amount of leakage from the charged liquid crystal capacitor after allowing it to be charged to the voltage.

그런데, 이와 같은 종래의 전압보지율 측정을 위한 액정패널에 있어서는, 작은 크기로 제작된 단위 셀을 이용했기 때문에 실제 양산 공정에서의 변수들에 의한 전압보지율 값이 아니라, 액정 자체만의 특성을 분석하는 것이므로 실제 액정패널에서의 전압보지율과는 차이가 있었다. 이로 인해, 실제 액정에 인가된 신호전압보다도 작게 액정층에 충전됨으로서 화면품질을 저하시키는 문제점이 있었다.However, in the conventional liquid crystal panel for measuring the voltage holding ratio, since the unit cell fabricated in a small size is used, the characteristics of the liquid crystal itself, not the value of the voltage holding ratio due to the variables in the actual mass production process, are obtained. As a result of analysis, there was a difference from the actual voltage holding ratio of the liquid crystal panel. For this reason, there is a problem in that the screen quality is lowered by being charged in the liquid crystal layer smaller than the signal voltage actually applied to the liquid crystal.

따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 실제 액정패널에서의 셀 공정과 동일한 공정을 갖는 패널을 설계하여 실제 공정변수에 의한 전압보지율을 측정함으로써 수율 및 액정패널의 화면품질을 을 향상시킨 테스트 패턴을 구비한 액정패널을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to design a panel having the same process as a cell process in an actual liquid crystal panel and to measure the yield rate and liquid crystal panel by measuring the voltage holding ratio according to actual process variables. The present invention provides a liquid crystal panel having a test pattern which improves the screen quality.

도 1은 종래 기술에 의한 전압보지율 측정을 위한 상하판 셀의 사시도Figure 1 is a perspective view of the upper and lower plate cells for measuring the voltage holding ratio according to the prior art

도 2는 종래 기술에 의한 상하판 셀의 합착도2 is a view of the bonding of the upper and lower plate cells according to the prior art

도 3은 본 발명에 의한 액정패널의 하판 전극 형성도3 is a bottom electrode formation diagram of the liquid crystal panel according to the present invention

도 4는 본 발명에 의한 액정패널의 상판 전극 형성도4 is a top electrode formation of the liquid crystal panel according to the present invention

도 5는 본 발명에 의한 액정패널의 상하판 셀의 합착도5 is a view of the bonding of the upper and lower cells of the liquid crystal panel according to the present invention

도 6은 본 발명에서 사용된 테스트 패턴을 구비한 액정패널의 구성도6 is a block diagram of a liquid crystal panel having a test pattern used in the present invention

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 상판 글라스 2 : 하판 글라스1: upper glass 2: lower glass

3 : ITO막 4 : 테스트 셀3: ITO membrane 4: test cell

5 : 패드부 7 : 하판 ITO 전극부5: pad portion 7: lower ITO electrode portion

8 : 하판 ITO 신호선 9,10 : 전압접속용 패드8: Lower ITO signal line 9,10: Voltage connection pad

11 : 상판 ITO 전극부 20 : 제너레이터 및 레코더부11 top plate ITO electrode portion 20 generator and recorder portion

22 : 증폭부 24 : 오프세트부22: amplification section 24: offset section

26 : 정류부 28 : 측정부26 rectifier 28 measuring unit

상기 목적을 달성하기 위하여, 본 발명에 의한 테스트 패턴을 구비한 액정패널은,In order to achieve the above object, the liquid crystal panel provided with a test pattern according to the present invention,

적어도, 투명전극막으로 신호선 및 전극부가 형성되어 있고 좌측부에 하판 및 상판으로 신호전압을 인가하기 위한 패드부가 형성된 하판과,At least a lower plate having a signal line and an electrode portion formed of a transparent electrode film and a pad portion for applying a signal voltage to the lower plate and the upper plate at a left side thereof;

상기 하판의 전극부와 일치하도록 투명전극막으로 전극부를 형성한 상판을 구비하여 이루어진 것을 특징으로 한다.It characterized in that it comprises a top plate formed of an electrode portion with a transparent electrode film to match the electrode portion of the lower plate.

상기 구성에서, 상기 상하판에 일치되는 전극부는 실(seal) 주변부, 액정 주입부구 및 패널 중앙부에 각각 위치한 것이 바람직하고, 상기 패드부는 하판의 가장 아랫부분에 형성된 것이 바람직하다.In the above configuration, the electrode portion corresponding to the upper and lower plates is preferably located at the periphery of the seal, the liquid crystal injection hole, and the center portion of the panel, and the pad portion is preferably formed at the bottom of the lower plate.

이하, 본 발명의 실시예에 관하여 첨부도면을 참조하면서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

또, 실시예를 설명하기 위한 모든 도면에서 동일한 기능을 갖는 것은 동일한 부호를 사용하고 그 반복적인 설명은 생략한다.In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

도 3은 본 발명에 의한 액정패널의 하판 전극 형성도로서, ITO막으로 신호선(8) 및 전극부(7)가 형성되어 있으며, 좌측부에 하판 및 상판으로 신호전압이 인가될 수 있도록 패드(PAD)부(9,10)가 형성되어 있다. 여기서, 부호 9는 상판으로 신호전압이 인가될 수 있도록 한 패드이고, 부호 10은 하판으로 신호전압이 인가될 수 있게 한 패드이다.3 is a bottom electrode formation diagram of a liquid crystal panel according to the present invention, in which a signal line 8 and an electrode portion 7 are formed of an ITO film, and a pad (PAD) is applied to a lower plate and an upper plate on a left side thereof. (9) and (10) are formed. Here, reference numeral 9 denotes a pad for allowing a signal voltage to be applied to the upper plate, and reference numeral 10 denotes a pad for allowing a signal voltage to be applied to the lower plate.

도 4는 본 발명에 의한 액정패널의 상판 전극 형성도로서, ITO막(11)으로 패턴이 형성되어 있다. 그리고, 도 5는 본 발명에 의한 액정패널의 상하판 셀의 합착도로서, 실(seal) 주변부, 액정 주입구부 및 패널 중앙부에 상하판의 ITO 전극부가 일치되어 있는 구조이다.4 is a top electrode formation diagram of the liquid crystal panel according to the present invention, in which a pattern is formed of the ITO film 11. FIG. 5 is a view illustrating the bonding of the upper and lower plate cells of the liquid crystal panel according to the present invention in which the ITO electrode portions of the upper and lower plates coincide with the seal peripheral portion, the liquid crystal injection port portion, and the panel center portion.

전압보지율은 신호전압의 알엠에스(RMS) 값과 액정에 걸린 전압이 감소하는 만큼의 RMS 값에 의해 구해진다. 따라서 측정원리는 우선, 액정에 인가된 신호전압까지 충전되게 하고나서, 충전된 액정 커패시터에서 누설되는 량 만큼을 모니터함으로써 전압보지율을 구한다.The voltage holding ratio is determined by the RMS value of the signal voltage and the RMS value as much as the voltage applied to the liquid crystal decreases. Therefore, the measurement principle first obtains the voltage holding ratio by charging the signal voltage applied to the liquid crystal and then monitoring the amount of leakage from the charged liquid crystal capacitor.

도 6은 본 발명에서 사용한 전압보지율 측정 장치의 구성도로서, FET의 게이트는 스캔 펄스 출력(Vscan)에 의해 제어된다. 또한, 액정에 가해지는 신호전압(Vdata)은 제너레이터 및 레코더 장치(20)의 아날로그 출력에 의해 제어되며, 액정 커패시터에서 충전량의 누설 없이 액정에 걸리는 전압을 모니터 해주기 위해서 증폭기를 사용한다. 액정 커패시터에 걸리는 신호전압의 RMS값과 전압보지율 측정 결과는 호스트 피씨(Host PC)에 표시된다.6 is a configuration diagram of the voltage holding ratio measuring device used in the present invention, in which the gate of the FET is controlled by the scan pulse output Vscan. In addition, the signal voltage Vdata applied to the liquid crystal is controlled by the analog output of the generator and recorder device 20, and an amplifier is used to monitor the voltage applied to the liquid crystal without leakage of the charge amount from the liquid crystal capacitor. The RMS value of the signal voltage applied to the liquid crystal capacitor and the measurement result of the voltage holding ratio are displayed on the host PC.

상기와 같은 측정원리를 이용해서 실제 액정패널과의 동일 공정조건으로 테스트 패턴을 제작하기 위해서 도 3, 4에서와 같이 상판과 하판 각각에서 신호선과 전극부(7,8,11)를 ITO로 패턴을 형성하고, 하판의 패드부에는 전압보지율 측정을 위한 전극부를 하판에 형성(9,10)한다. 여기서 패드부의 양끝과 가운데 부분의 전극부(9)는 상판의 신호선과 연결되게 설계한다.In order to fabricate the test pattern under the same process conditions as the actual liquid crystal panel using the measurement principle as described above, as shown in FIGS. 3 and 4, the signal lines and the electrode parts 7, 8, and 11 are respectively patterned as ITO on the upper and lower plates. The lower portion of the pad portion, the electrode portion for measuring the voltage holding ratio is formed on the lower plate (9, 10). Here, both ends of the pad portion and the electrode portions 9 in the center portion are designed to be connected to the signal line of the upper plate.

상기 도 5에서의 상하판 합착도에서 처럼, 측정한 위치, 즉 실(seal) 주변부, 액정 주입구부, 중앙부에 상하판의 전극부가 위치하게 되어 하판 패드부의 전극부를 통해 상하판으로 신호전압이 인가되어 액정층에 충전되게 한다.As shown in the upper and lower plate bonding diagram in FIG. 5, the upper and lower electrode parts are positioned at the measured position, that is, the seal peripheral part, the liquid crystal injection hole part, and the center part, and a signal voltage is applied to the upper and lower plate parts through the electrode part of the lower pad part. To be filled in the liquid crystal layer.

이렇게 해서 제작된 패널을 도 6에서 도시한 전압보지율을 측정 장치를 이용하여 측정할 수 있다.In this way, the manufactured panel can be measured using the measuring device.

이상에서 설명한 바와 같이, 본 발명의 테스트 패턴을 구비한 액정패널에 의하면, 종래의 단위 셀에서 액정 자체만의 특성이 아닌 실제 공정에서의 여러가지 변수들을 포함한 전압보지율을 측정할 수 있기 때문에 공정에서의 문제점을 찾아내어 실제 액정패널 제작시 개선된 공정으로 양산 진행을 할 수 있기 때문에 고수율을 획득할 수 있으며, 액정패널의 품질을 향상시킬 수 있다.As described above, according to the liquid crystal panel having the test pattern of the present invention, since the voltage holding ratio including various variables in the actual process is measured in the conventional unit cell, not only the liquid crystal itself, By finding the problem of the actual production of the liquid crystal panel can proceed to mass production improved process can be obtained a high yield, and can improve the quality of the liquid crystal panel.

아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (3)

액정패널에 있어서,In the liquid crystal panel, 적어도, 투명전극막으로 신호선 및 전극부가 형성되어 있고 좌측부에 하판 및 상판으로 신호전압을 인가하기 위한 패드부가 형성된 하판과,At least a lower plate having a signal line and an electrode portion formed of a transparent electrode film and a pad portion for applying a signal voltage to the lower plate and the upper plate at a left side thereof; 상기 하판의 전극부와 일치하도록 투명전극막으로 전극부를 형성한 상판을 구비하여 이루어진 것을 특징으로 하는 테스트 패턴을 구비한 액정패널.A liquid crystal panel having a test pattern, the upper plate having an electrode portion formed of a transparent electrode film so as to match the electrode portion of the lower plate. 제 1항에 있어서, 상기 상하판에 일치되는 전극부는,According to claim 1, The electrode unit corresponding to the upper and lower plates, 실(seal) 주변부, 액정 주입부구 및 패널 중앙부에 각각 위치한 것을 특징으로 하는 테스트 패턴을 구비한 액정패널.A liquid crystal panel having a test pattern, each of which is positioned around a seal periphery, a liquid crystal injection hole, and a central portion of the panel. 제 1항에 있어서, 상기 패드부는 하판의 가장 아랫부분에 형성된 것을 특징으로 하는 테스트 패턴을 구비한 액정패널.The liquid crystal panel according to claim 1, wherein the pad part is formed at the bottom of the lower plate.
KR1019990025265A 1999-06-29 1999-06-29 Liquid crystal panel having test pattern KR20010004573A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100958624B1 (en) * 2007-12-26 2010-05-19 주식회사 동부하이텍 Test Pattern for Analyzing Capacitance Characterization of Interconnection Line

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161722A (en) * 1981-03-30 1982-10-05 Fujitsu Ltd Positioning method for liquid crystal display device
KR950003864A (en) * 1993-07-22 1995-02-17 이헌조 Repair panel of LCD panel
KR960038441A (en) * 1995-04-24 1996-11-21 김광호 Liquid Crystal Display with Short Pattern

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161722A (en) * 1981-03-30 1982-10-05 Fujitsu Ltd Positioning method for liquid crystal display device
KR950003864A (en) * 1993-07-22 1995-02-17 이헌조 Repair panel of LCD panel
KR960038441A (en) * 1995-04-24 1996-11-21 김광호 Liquid Crystal Display with Short Pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100958624B1 (en) * 2007-12-26 2010-05-19 주식회사 동부하이텍 Test Pattern for Analyzing Capacitance Characterization of Interconnection Line

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