CN107589601B - Liquid crystal display panel and control method thereof - Google Patents
Liquid crystal display panel and control method thereof Download PDFInfo
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- CN107589601B CN107589601B CN201710896773.6A CN201710896773A CN107589601B CN 107589601 B CN107589601 B CN 107589601B CN 201710896773 A CN201710896773 A CN 201710896773A CN 107589601 B CN107589601 B CN 107589601B
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Abstract
The invention provides a liquid crystal display panel and a control method thereof, wherein the liquid crystal display panel comprises: an upper substrate, a lower substrate, and a liquid crystal layer; the liquid crystal layer is sealed between the upper substrate and the lower substrate; the lower substrate sequentially comprises a TFT substrate, a thin film transistor and a pixel electrode from bottom to top; the surface of the upper substrate is provided with a first common electrode and a second common electrode, wherein the first common electrode is opposite to the thin film transistor, the second common electrode is opposite to the pixel electrode, and the first common electrode and the grid electrode of the thin film transistor have the same potential. The liquid crystal display panel and the control method thereof can control the liquid crystal molecules at the edge of the grid electrode of the liquid crystal display panel not to leak light.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a liquid crystal display panel and a control method thereof.
Background
When a VA (vertical alignment) display panel is powered on, liquid crystal molecules between an upper substrate and a lower substrate of the VA display panel are aligned and rotated in a vertical electric field direction, and the rotation size of the liquid crystal molecules is adjusted by a voltage between the upper substrate and the lower substrate, so as to control the backlight transmittance of the display panel, thereby achieving brightness control of different gray scales of L0-L255. However, in the VA display panel, when the gray scale (i.e. black scale) is low, such as L0, the pixel electrode has no voltage, and the display panel is opaque, but the gate of the Thin Film Transistor (TFT) is still energized, so that the gate drive generates an electric field to control the rotation of the liquid crystal, and the backlight passes through the edge of the gate, thereby causing light leakage. In order to solve the problem of light leakage, a BM (Black Matrix) process is added on the upper substrate to block light, so that the edge of the VA display panel does not leak light at low gray scales such as L0, but the BM process affects the dark state performance of the display panel at low gray scales such as L0.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a liquid crystal display panel and a control method thereof, which can control liquid crystal molecules at the edge of a gate of the liquid crystal display panel not to leak light.
The invention provides a liquid crystal display panel, comprising: an upper substrate, a lower substrate, and a liquid crystal layer;
the liquid crystal layer is sealed between the upper substrate and the lower substrate;
the lower substrate sequentially comprises a TFT substrate, a thin film transistor and a pixel electrode from bottom to top;
the surface of the upper substrate is provided with a first common electrode and a second common electrode, wherein the first common electrode is opposite to the thin film transistor, the second common electrode is opposite to the pixel electrode, and the first common electrode and the grid electrode of the thin film transistor have the same potential.
Preferably, the distance between the first common electrode and the second common electrode ranges from 2 micrometers to 4 micrometers;
the distance range between the projection of the first common electrode and the second common electrode on the lower substrate and the pixel electrode is 2-4 microns, and the projection of the first common electrode on the lower substrate is not overlapped with the pixel electrode. .
Preferably, the potential of the first common electrode is controlled to have the same potential as the gate electrode according to a fixed frequency of a gate voltage.
Preferably, the lower substrate further comprises a color filter layer located above the thin film transistor, a first passivation layer is arranged between the thin film transistor and the color filter layer, a second passivation layer is arranged on the color filter layer, and the pixel electrode is located above the second passivation layer;
the thin film transistor sequentially comprises from bottom to top: the semiconductor device comprises a grid, an insulating layer, an amorphous silicon layer and a semiconductor conducting layer, wherein a source electrode and a drain electrode are further arranged on the semiconductor conducting layer.
Preferably, the TFT substrate and the upper substrate are both glass plates;
the first common electrode, the second common electrode and the pixel electrode are all made of semiconductor transparent conductive film materials.
Preferably, a plurality of gate scanning lines and a plurality of data lines are further arranged above the TFT substrate, the gate scanning lines and the data lines are vertically and alternately insulated to define pixel regions arranged in an array, and the lower end of each of the red, green and blue filtering units of the color filtering layer corresponding to each of the pixel regions is correspondingly provided with one of the thin film transistors.
Preferably, a columnar spacer is disposed above the second passivation layer.
Preferably, a line width of the first common electrode is at least 3 micrometers greater than a line width of the gate electrode.
The invention also provides a liquid crystal display panel control method, which comprises the following steps:
providing an upper substrate, and preparing a first common electrode and a second common electrode on the surface of the upper substrate;
providing a TFT substrate, preparing a thin film transistor on the TFT substrate, preparing a color filter layer on the thin film transistor, preparing a pixel electrode on the color filter layer, and forming a lower substrate;
and sealing a liquid crystal layer between the upper substrate and the lower substrate to obtain a liquid crystal display panel, and providing the same potential for the first common electrode and the grid electrode of the thin film transistor.
Preferably, the disposing a first common electrode and a second common electrode on the surface of the upper substrate specifically includes:
plating a semiconductor transparent conductive film material on the surface of the upper substrate;
coating a photoresist material on the surface of the semiconductor transparent conductive film material;
and carrying out exposure, development and etching treatment on the surface of the semiconductor transparent conductive film material to obtain the first common electrode and the second common electrode.
The implementation of the invention has the following beneficial effects: the first common electrode and the second common electrode are prepared on the upper substrate, the first common electrode is opposite to the thin film transistor, the same potential is arranged between the first common electrode and the grid electrode of the thin film transistor, the first common electrode and the grid electrode of the thin film transistor are used for controlling the liquid crystal molecules at the edge of the grid electrode of the liquid crystal display panel to be positioned in the direction vertical to the upper substrate and the lower substrate, deflection does not occur, and light leakage of the liquid crystal molecules at the edge of the grid electrode is prevented when the L0 gray scale state is achieved. The BM process is reduced and the pattern definition process of the common electrode is added, so that the dark state performance of the display panel at the low gray level of L0 is not affected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a structural view of a liquid crystal display panel according to the present invention.
Fig. 2 is a structural diagram of a thin film transistor provided by the present invention.
Detailed Description
The present invention provides a liquid crystal display panel, as shown in fig. 1, the liquid crystal display panel includes: upper substrate 1, lower substrate, liquid crystal layer 3.
The liquid crystal layer 3 is sealed between the upper substrate 1 and the lower substrate.
The lower substrate includes a Thin Film Transistor (TFT) substrate 2, a TFT 4, and a pixel electrode 6 in this order from bottom to top. As shown in fig. 2, the thin film transistor 4 includes a gate electrode 41.
The surface of the upper substrate 1 is provided with a first common electrode 7 and a second common electrode 8, wherein the first common electrode 7 is opposite to the thin film transistor 4, the second common electrode 8 is opposite to the pixel electrode 6, and the first common electrode 7 and the gate electrode 41 of the thin film transistor 4 have the same potential.
An electric field is formed between the first common electrode 7 and the thin film transistor 4 to control the liquid crystal molecules between the first common electrode 7 and the thin film transistor 4 to deflect, and light leakage of the liquid crystal layer 3 is prevented. The second common electrode 8 and the pixel electrode 6 form an electric field to control the liquid crystal molecules between the second common electrode 8 and the pixel electrode 6 to deflect, so as to control the gray scale display of the liquid crystal display panel.
Generally, the electric field formed between the first common electrode 7 and the gate electrode 41 of the thin film transistor 4 is a vertical electric field, and the electric potentials between the first common electrode 7 and the gate electrode 41 of the thin film transistor 4 are controlled to be the same, so that the direction of the liquid crystal molecules between the first common electrode 7 and the gate electrode 41 is controlled to be a vertical direction, and when the liquid crystal molecules between the upper substrate 1 and the lower substrate are in the L0 gray scale (i.e. black level), the electric potentials of the first common electrode 7 and the gate electrode 41 can be controlled, so as to control the liquid crystal molecules at the edge of the gate electrode 41 of the liquid crystal display panel not to leak light.
The upper substrate 1 and the lower substrate are sealed and bonded by a frame sealing adhesive, and the frame sealing adhesive is a conductive frame sealing adhesive.
Specifically, the potential of the first common electrode 7 is controlled to be the same as the potential of the gate 41 of the thin film transistor 4, for example, the upper substrate 1 and the lower substrate are connected by the conductive frame sealing adhesive, the first common electrode 7 can be electrically connected with the frame sealing adhesive, and the gate 41 of the thin film transistor 4 can be electrically connected with the frame sealing adhesive, so that the first common electrode 7 and the gate 41 can be electrically connected to realize the same potential.
Preferably, the lower substrate further includes a common voltage signal line (not shown), and the second common electrode 8 is connected to the common voltage signal line through a conductive sealant.
Further, the distance D1 between the first common electrode 7 and the second common electrode 8 is in the range of 2-4 microns. The distance D2 between the projection of the first common electrode 7 on the lower substrate and the pixel electrode 6 is in the range of 2-4 micrometers, and the distance D3 between the projection of the second common electrode 8 on the lower substrate and the pixel electrode 6 is also in the range of 2-4 micrometers, wherein the projection of the first common electrode 7 on the lower substrate is not overlapped with the pixel electrode 6, and the projection of the second common electrode 8 on the lower substrate can be partially overlapped with the pixel electrode 6. The distance between the projection of the second common electrode 8 and the pixel electrode 6 is the distance between two sides of the projection opposite to the pixel electrode 6; the distance between the projection of the second common electrode 8 and the pixel electrode 6 is the distance between the projection and the same side of the pixel electrode 6, for example, the distance between the left side of the projection of the second common electrode 8 and the left side of the pixel electrode 6.
Further, the potential of the first common electrode 7 is controlled to have the same potential as the gate electrode 41 of the thin film transistor 4 in accordance with the fixed frequency of the gate voltage. The gate voltage is the voltage of the gate 41.
For example, the fixed frequency of the gate voltage may be 60 hz or 120 hz, at which the switching between VGH and VGL is performed, and the potential of the first common electrode 7 may be controlled to have the same potential as the gate electrode 41 of the thin film transistor 4 according to the fixed frequency.
Further, the lower substrate further comprises a color filter layer 5 located above the thin film transistor 4, a first passivation layer 9 is disposed between the thin film transistor 4 and the color filter layer 5, a second passivation layer 10 is disposed on the color filter layer 5, and the pixel electrode 6 is located above the second passivation layer 10.
Further, as shown in fig. 2, the thin film transistor 4 includes, in order from bottom to top: a gate electrode 41, an insulating layer 42, an amorphous silicon layer 43, a semiconductor conductive layer 44 (i.e., an active layer, a conductive channel), and a source electrode 45 and a drain electrode (not shown) on the semiconductor conductive layer 44. The amorphous silicon layer 43 is an a-Si layer, the insulating layer 42 is a SiNx layer, and the semiconductor conductive layer 44 is used for conducting and breaking between the drain and the source 45. Preferably, the first passivation layer 9 and the second passivation layer 10 are provided with openings through which the pixel electrodes 6 are connected to the drain electrodes.
Further, the TFT substrate 2 and the upper substrate 1 are both glass plates.
The first common electrode 7, the second common electrode 8 and the pixel electrode 6 are all made of semiconductor transparent conductive film materials. For example, the semiconductor transparent conductive film material may be ITO (Indium Tin oxide, Indium Tin oxide semiconductor transparent conductive film).
Furthermore, a plurality of grid scanning lines and a plurality of data lines are further arranged above the TFT substrate 2, the grid scanning lines and the data lines of the grid scanning lines are vertically and alternately insulated to define pixel regions arranged in an array, and a thin film transistor 4 is correspondingly arranged at the lower end of each of the red, green and blue filtering units of the color filtering layer 5 corresponding to each pixel region. The red, green and blue light filtering units are made of red, green and blue light resistance materials respectively.
Further, a pillar spacer is disposed over the second passivation layer 10. Preferably, the columnar spacer is a tapered columnar body.
Further, the line width of the first common electrode 7 is at least 3 micrometers greater than the line width of the gate electrode 41 to prevent an electric field from being formed between the second common electrode 8 and the gate electrode 41 of the thin film transistor 4, and to control the deflection of the liquid crystal molecules between the first common electrode 7 and the thin film transistor 4, which results in light leakage of the liquid crystal molecules at the edge of the gate electrode 41 of the liquid crystal display panel.
The invention also provides a liquid crystal display panel control method, which comprises the following steps:
providing an upper substrate 1, and preparing a first common electrode 7 and a second common electrode 8 on the surface of the upper substrate 1;
providing a TFT substrate 2, preparing a thin film transistor 4 on the TFT substrate 2, preparing a color filter layer 5 on the thin film transistor 4, preparing a pixel electrode 6 on the color filter layer 5, and forming a lower substrate;
the liquid crystal layer 3 is sealed between the upper substrate 1 and the lower substrate to obtain a liquid crystal display panel, and the same potential is supplied to the first common electrode 7 and the gate electrode 41 of the thin film transistor 4.
Further, the disposing of the first common electrode 7 and the second common electrode 8 on the surface of the upper substrate 1 specifically includes:
plating a semiconductor transparent conductive film material on the surface of the upper substrate 1;
coating a photoresist material on the surface of the semiconductor transparent conductive film material;
and carrying out exposure, development and etching treatment on the surface of the semiconductor transparent conductive film material to obtain a first common electrode 7 and a second common electrode 8, wherein the distance between the first common electrode 7 and the second common electrode 8 is 2-4 microns.
Preferably, the preparing the pixel electrode 6 on the color filter layer 5 specifically includes:
plating a semiconductor transparent conductive film material on the surface of the color filter layer 5;
coating a photoresist material on the surface of the semiconductor transparent conductive film material;
and carrying out exposure, development and etching treatment on the surface of the semiconductor transparent conductive film material to obtain the pixel electrode 6. Preferably, the distance between the projection of the first common electrode 7 and the second common electrode 8 on the lower substrate and the pixel electrode 6 ranges from 2 micrometers to 4 micrometers, and the projection of the first common electrode 7 on the lower substrate is not coincident with the pixel electrode 6.
In summary, according to the liquid crystal display panel and the control method thereof provided by the invention, the first common electrode 7 and the second common electrode 8 are prepared on the upper substrate 1, the first common electrode 7 is opposite to the thin film transistor 4, and the same potential is provided between the first common electrode 7 and the gate 41 of the thin film transistor 4, so that the liquid crystal molecules at the edge of the gate 41 of the liquid crystal display panel are controlled to be positioned in a direction vertical to the upper substrate 1 and the lower substrate, no deflection occurs, and light leakage of the liquid crystal molecules at the edge of the gate 41 is prevented when the liquid crystal display panel is in the L0 gray scale state.
The invention carries out pattern division on the common electrode on the upper substrate 1, designs an independent first common electrode 7 pattern (utilizing ITO pattern exposure, development and etching and the like) at the upper substrate 1 corresponding to the grid 41 of the thin film transistor 4 of the lower substrate, can independently control the voltage between the grid 41 of the lower substrate and the first common electrode 7 corresponding to the upper substrate 1, and further controls the liquid crystal molecules at the edge of the grid 41 of the liquid crystal display panel not to transmit light when the liquid crystal molecules at the edge of the grid 41 of the liquid crystal display panel are at the low gray scale of L0. The invention reduces a BM process and adds a pattern definition process of the common electrode, thereby not affecting the dark state performance of the display panel at the low gray level of L0.
Further, the line width of the first common electrode 7 is at least 3 micrometers greater than the line width of the gate electrode 41 to prevent the electric field formed between the second common electrode 8 and the thin film transistor 4 from interfering with the liquid crystal molecules at the edge of the gate electrode 41.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A liquid crystal display panel, comprising: an upper substrate (1), a lower substrate, and a liquid crystal layer (3);
the liquid crystal layer (3) is sealed between the upper substrate (1) and the lower substrate;
the lower substrate sequentially comprises a TFT substrate (2), a thin film transistor (4) and a pixel electrode (6) from bottom to top; the lower substrate further comprises a color filter layer (5) positioned above the thin film transistor (4), a first passivation layer (9) is arranged between the thin film transistor (4) and the color filter layer (5), a second passivation layer (10) is arranged on the color filter layer (5), and the pixel electrode (6) is positioned above the second passivation layer (10);
a first common electrode (7) and a second common electrode (8) are arranged on the surface of the upper substrate (1), wherein the first common electrode (7) is opposite to the thin film transistor (4), the second common electrode (8) is opposite to the pixel electrode (6), and the potential of the first common electrode (7) is controlled according to the fixed frequency of the grid voltage so as to have the same potential as the grid electrode (41);
the liquid crystal layer (3) is filled between the second passivation layer (10) and the first common electrode (7);
the line width of the first common electrode (7) is at least 3 micrometers greater than the line width of the gate electrode (41).
2. The liquid crystal display panel according to claim 1, wherein the distance between the first common electrode (7) and the second common electrode (8) is in the range of 2 to 4 μm;
the distance range between the projection of the first common electrode (7) and the second common electrode (8) on the lower substrate and the pixel electrode (6) is 2-4 micrometers, and the projection of the first common electrode (7) on the lower substrate is not coincident with the pixel electrode (6).
3. The lcd panel according to claim 1, wherein the tft (4) comprises, in order from bottom to top: the transistor comprises a grid electrode (41), an insulating layer (42), an amorphous silicon layer (43) and a semiconductor conducting layer (44), wherein a source electrode (45) and a drain electrode are further arranged on the semiconductor conducting layer (44).
4. The liquid crystal display panel according to claim 1, wherein the TFT substrate (2) and the upper substrate (1) are both glass plates;
the first common electrode (7), the second common electrode (8) and the pixel electrode (6) are all made of semiconductor transparent conductive film materials.
5. The lcd panel according to claim 3, wherein a plurality of gate scan lines and a plurality of data lines are further disposed above the TFT substrate (2), the gate scan lines and the data lines are vertically and alternately insulated to define pixel regions arranged in an array, and one of the thin film transistors (4) is disposed at a lower end of the red, green, and blue filter units of the color filter layer (5) corresponding to each pixel region.
6. The liquid crystal display panel according to claim 3, wherein a columnar spacer is disposed over the second passivation layer (10).
7. A control method of a liquid crystal display panel is characterized by comprising the following steps:
providing an upper substrate (1), and plating a semiconductor transparent conductive film material on the surface of the upper substrate (1); coating a photoresist material on the surface of the semiconductor transparent conductive film material; carrying out exposure, development and etching treatment on the surface of the semiconductor transparent conductive film material to obtain a first common electrode (7) and a second common electrode (8);
providing a TFT substrate (2), preparing a thin film transistor (4) on the TFT substrate (2), preparing a color filter layer (5) on the thin film transistor (4), preparing a pixel electrode (6) on the color filter layer (5), arranging a first passivation layer (9) between the thin film transistor (4) and the color filter layer (5), and arranging a second passivation layer (10) on the color filter layer (5) so that the pixel electrode (6) is positioned above the second passivation layer (10) to form a lower substrate;
and sealing a liquid crystal layer (3) between the upper substrate (1) and the lower substrate to obtain a liquid crystal display panel, and providing the same potential for the first common electrode (7) and the grid electrode (41) of the thin film transistor (4).
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| CN113920957B (en) * | 2021-10-29 | 2022-07-26 | 重庆惠科金渝光电科技有限公司 | Liquid crystal display device and driving method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650776A (en) * | 2011-08-02 | 2012-08-29 | 北京京东方光电科技有限公司 | Liquid crystal display panel and liquid crystal display |
| CN105511189A (en) * | 2016-02-16 | 2016-04-20 | 深圳市华星光电技术有限公司 | VA-type COA liquid crystal display panel |
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| CN1971385A (en) * | 2005-11-23 | 2007-05-30 | 群康科技(深圳)有限公司 | LCD device and its manufacturing method |
| JP5645203B2 (en) * | 2010-11-25 | 2014-12-24 | 三菱電機株式会社 | Liquid crystal display panel and liquid crystal display device |
| CN102736332B (en) * | 2012-02-22 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display panel and liquid crystal display |
| CN105047722A (en) * | 2015-08-19 | 2015-11-11 | 京东方科技集团股份有限公司 | Film transistor, manufacturing method therefor, array substrate, and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650776A (en) * | 2011-08-02 | 2012-08-29 | 北京京东方光电科技有限公司 | Liquid crystal display panel and liquid crystal display |
| CN105511189A (en) * | 2016-02-16 | 2016-04-20 | 深圳市华星光电技术有限公司 | VA-type COA liquid crystal display panel |
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