KR20010004239A - A method for fabricating semiconductor memory device with decreased step between cell region and peripheral region - Google Patents

Abstract

PURPOSE: A method of fabricating a semiconductor memory device is to prevent a burying fail of a metal interconnection and a short-circuit between a capacitor and a metal interconnection due to a topology between a cell region and a periphery circuit region. CONSTITUTION: A method for manufacturing a semiconductor memory device comprises the steps of: forming a capacitor(63) at a cell region of a substrate with a predetermined lower layer formed thereon; forming an interlayer dielectric(62) on an upper portion of the whole substrate; forming a cell topology reduction mask on the interlayer dielectric, the mask being formed to cover a slope start point of the cell region; and wet etching the interlayer dielectric by using the mask as a barrier. The interlayer dielectric is a BPSG(borophospho silicate glass). The wet etching is performed by using a buffered oxide etchant or a HF solution. The interlayer dielectric includes the BPSG film and a protective film of 200-500 angstroms.

Description

A method for fabricating semiconductor memory device with decreased step between cell region and peripheral region}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor fabrication technology, and more particularly, to a method of fabricating a semiconductor memory device capable of alleviating a step between a cell region and a peripheral circuit region due to the formation of a capacitor in a cell region.

In manufacturing a semiconductor memory device such as a DRAM, a step is caused between the cell region and the peripheral circuit region because capacitors are not formed in the cell region or capacitors in the peripheral circuit region.

As a method of alleviating the step difference caused between the cell region and the peripheral circuit region, a conventional interlayer insulating film front surface etching process is used, and recently, a CRT process using a cell topology reduction (CTR) mask and wet etching is used.

1A through 1C are scanning electron microscope (SEM) photographs of a conventional interlayer insulating film front etching process and a subsequent metallization process. First, FIG. 1A illustrates a capacitor 2 formed in a cell region. The interlayer insulating film (BPSG) is formed on the entire structure, and a step of about 10000Å is induced between the cell region and the peripheral circuit region. It is a step angle of about degrees.

Next, FIG. 1B shows a state in which the interlayer insulating film 1 is etched for a predetermined time. The step difference between the cell region and the peripheral circuit region is almost insignificant due to the characteristics of the etch process. It can be seen that is slightly relaxed.

FIG. 1C illustrates the interlayer insulating film SOG (silicon-silicon) between the first metal wiring 5 and the second metal wiring 3 due to the high level of difference between the cell region and the peripheral circuit region despite the entire surface etching of the interlayer insulating film 1. The thickness of the on-glass 4 is relatively high in the peripheral circuit region having a low topology, and thus out-gassing from the interlayer insulating film SOG 4 when the second metal wiring 3 is buried after via hole etching. There is a problem in that a void 6 is formed in the via contact by the phenomenon.

In order to solve this problem, after forming the capacitor 23 and the interlayer dielectric layer (BPSG) 22, as shown in FIG. 2A, the remaining portions except for the cell are covered with the photoresist (CTR mask) 21 and the cell region is shown in FIG. 2A. The wet etching of only the interlayer insulating film 22 is applied to the CTR process to significantly reduce the step difference between the cell region and the peripheral circuit region.

When the CTR process is applied, the maximum step between the cell area and the peripheral circuit area is about 7000 to 8000 Å and the step angle is about 20 ° due to excessive side etching during wet etching, compared to the front etching process. The step reduction effect is great. Unexplained reference numeral 24 denotes a photoresist for subsequent processing.

However, when the metallization process is performed after the CRT process, as shown in FIGS. 3A and 3B, the void 32 problem due to the poor embedding of the second metallization 31 in the peripheral circuit region having a low topology is generated. Although not completely solved, an excessive etching of the interlayer insulating layer 36 is caused at the edge of the cell block, thereby shorting the plate electrode 34 and the first metal wiring 33 as shown in FIG. 3C. (35) may be found.

Accordingly, the side and etching of the wet etching process may be performed by changing the impurity concentration of the interlayer insulating layer or by controlling the thickness of a capping layer (usually a nitride layer) deposited on the interlayer insulating layer 42 to prevent water absorption. By suppressing the phenomenon as much as possible, the step difference between the cell region and the peripheral circuit region could be reduced to about 5000 to 7000 Å, and the bit line (not shown) and the first metal wiring 44 were adjusted by appropriately adjusting the etching thickness during wet etching. The short distance can be prevented by controlling the minimum distance of the liver to 1000 to 2000Å. Reference numeral '41' denotes a CRT mask.

However, even in this case, as shown in FIG. 4B, the thickness of the inter-metal interlayer insulating film (SOG) 45 in the peripheral circuit region is considerably high, about 3000 kW, so that the subsequent second metal wiring (not shown) is buried. Poor deposition of the metal wiring due to the gas ejection from the inter-metal interlayer insulating film (SOG) 45 into the via contact is still a problem. Reference numeral 43 denotes a capacitor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of preventing a short circuit between a capacitor and a metal wiring due to a step between a cell region and a peripheral circuit region, and a poor filling of the metal wiring.

1A to 1C are scanning electron microscope (SEM) photographs of a conventional interlayer insulating film front etching process and a subsequent metallization process.

2A and 2B are cross-sectional SEM photographs after the conventional CRT process, respectively.

Figure 3a and Figure 3b is a SEM image of the cross-section after the subsequent metallization process after the conventional CRT process.

4A and 4B are SEM images of a cross section of the CRT process and the subsequent metallization process according to another prior art, respectively.

Figure 5 is a cross-sectional SEM photograph showing the wet etching profile during the CTR process.

6A and 6B are SEM photographs illustrating a step mitigation process between a cell region and a peripheral region according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

61: CTR Mask

62: interlayer insulating film

63: capacitor

In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method including: forming a capacitor in a cell region on a substrate on which a predetermined lower layer is formed; A second step of forming an interlayer insulating film on the entire substrate structure; Forming a mask for reducing the cell topology on the interlayer insulating layer, wherein the mask covers the starting point of the inclination of the cell region; And a fourth step of wet etching the interlayer insulating layer using the mask as a barrier.

The present invention relates to a wet etching method for minimizing the step difference between the cell region and the peripheral circuit region due to the formation of a capacitor in the cell region of the semiconductor memory device. By applying the optimization of the mask position at the same time, it minimizes the step between the cell area and the peripheral circuit area and optimizes the step angle.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

FIG. 5 is a cross-sectional SEM view of a profile after depositing an interlayer dielectric layer (BPSG) 52 on a substrate of a flat plate, forming a CTR mask 51, and performing wet etching using a buffered oxide etchant (BOE). The photograph shows the side and the etching characteristics of wet etching well. The wet etch forms a right triangle with an inclination of about 15 ° and can be seen to be etched about four times more laterally than the depth etched downward. The degree of overetching varies according to the concentration of impurities added to the interlayer insulating film 52 and the type of photoresist constituting the CRT mask 51. From this, the degree of side etching is different from the interlayer insulating film. It can be deduced that it depends on the degree of adsorption force between photoresists. This side surface and etching characteristics of the interlayer insulating film 52 may be most suitably applied to alleviate the step difference between the cell region and the peripheral circuit region of the interlayer insulating film 52.

6A and 6B are SEM photographs showing a step relaxation process between a cell region and a peripheral region according to an embodiment of the present invention, wherein the process is first shown in FIG. 6A in terms of wet etching and side etching characteristics. In order to apply the CTR mask 61, the CTR mask 61 is formed from the point where the step of the cell region starts, not the boundary between the cell region and the peripheral circuit region. The depth of the wet etching is lowered as much as 1500 to 2000 mW from 4500 to 5000 mW based on the thickness of the interlayer insulating layer 62 of the cell area to minimize the step between the cell area and the peripheral circuit area. Positioning of the CTR mask 61 is based on the outermost capacitor of the cell region, and by applying a hard bake treatment to the CTR mask 61, the degree of side and degree of etching during wet etching can be adjusted. have. In addition, the thickness of the protective film (mainly a nitride film) (not shown) together with the interlayer insulating film 62 may be adjusted to 200 to 500 kPa to control the degree of side and drawing etching during wet etching, and the impurities contained in the interlayer insulating film 62. By adjusting the concentration of (B, P), the degree of side etching and degree of etching can be controlled.

Next, Figure 6b is a cross-sectional view after performing the process shown in Figure 6a, as shown in the step height between the cell region and the peripheral circuit region is greatly relaxed to about 3000Å, thereby reducing the step angle significantly can confirm.

When the step mitigation process as described above, the step and the step angle can be significantly reduced as described above, thereby preventing the short circuit between the capacitor 63 and the metal wiring (not shown) during the subsequent metal wiring process. have. Reference numeral 64 denotes that the interlayer insulating film 62 having a sufficient thickness exists in the portion where the short circuit between the capacitor 63 and the metal wiring has occurred in the case of the present embodiment, so that the short circuit can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention has the effect of greatly alleviating the step difference between the cell region and the peripheral circuit region by using the reverse side and the etching characteristics of the wet etching using the CRT mask, thereby preventing the poor embedded wiring during the subsequent metal wiring process. As a result, the reliability and yield of the device can be expected.

Claims (6)

Forming a capacitor in a cell region on a substrate on which a predetermined lower layer is formed; A second step of forming an interlayer insulating film on the entire substrate structure; Forming a mask for reducing the cell topology on the interlayer insulating layer, wherein the mask covers the starting point of the inclination of the cell region; And A fourth step of wet etching the interlayer insulating layer using the mask as a barrier Method of manufacturing a semiconductor memory device comprising a. The method of claim 1, The interlayer insulating film, Method of manufacturing a semiconductor memory device, characterized in that the BPSG (borophpospho silicate glass) film. The method according to claim 1 or 2, The wet etching, A method of manufacturing a semiconductor memory device, characterized in that performed using a buffer oxide etch (BOE) or HF solution. The method of claim 3, And the etching target of the interlayer insulating layer is 1500 to 2000 microseconds during the wet etching. The method according to claim 1 or 2, And performing a hard bake treatment on the mask after performing the third step. The method of claim 1, The interlayer insulating film, A method of fabricating a semiconductor memory device, comprising a BPSG (borophpospho silicate glass) film and a protective film of 200 to 500 microns.