KR20010001996A - Method for Processing Node Obstacle in IPC Network of Exchange system - Google Patents

Abstract

PURPOSE: A method for processing node failures of an inter process communication(IPC) network in an exchange is provided to quickly inform an operator of a failure message through a telephony device bus(TD-bus) which is a detour route, so that the operator can quickly recognize a failure to minimize a loss. CONSTITUTION: A communication inter-working process(CIP) collects failure information generated in an inter process communication(IPC) network, and stores the failure information in a dual port RAM. A peripheral processor connected with the CIP through a telephony device bus(TD-bus) scans a critical alarm state register of the CIP at a set cycle, and identifies whether related bits are set up. If so, the peripheral processor reads a handshake register stored in the dual port RAM, to inform an operation and maintenance processor(OMP) of the failure information through a P bus.

Description

Method for Processing Node Obstacle in IPC Network of Exchange System

The present invention relates to a method for handling node failure in an IPC (Inter Process Communication) network of an exchange. In particular, the fault information of nodes providing a plurality of communication paths on an IPC network of an exchange can be bypassed through a TD-BUS device control bus. It is about a method of processing.

Typically, in the exchange system, the CIN (Communication Inter Working Network) block, which is responsible for switching messages between service systems of data generated between processors in an IPC network, manages the OMP ( It reports to the Operation Maintenance Processor so that the operators of the exchange can be notified of the failure status.

1 is a system configuration diagram showing a path for delivering a node failure message in a conventional switching system.

In the switching system, a plurality of subsystems 1 to m (P1 to Pn) based on processors are connected to the IPC network 16 through a plurality of nodes ND1 to NDm, and CIP (Communication) to the IPC network 16 is performed. An Inter-working Processor is connected, and an Operation Maintenance Processor (OMP) is connected to the IPC network 16 through the node ND0.

Interprocessor communication (IPC) data generated between the plurality of subsystems ND1 to NDm is exchanged with each other through the nodes connected to the IPC network 16. In order to secure the reliability of the IPC network, the nodes connected to the corresponding ones of the plurality of subsystems (ND1 to NDm) are redundant and the CIP (10) on the IPC network (16) for control and management of these nodes. Is connected. At this time, the CIP 10 collects the failure status of the nodes generated on the IPC network 16 and reports the failure status to the OMP 14 through the node ND0. Therefore, the operators refer to the fault message and perform the replacement of the corresponding head, the transfer to the redundant node, or the initialization of the node. In this case, fault messages of the nodes reported by the CIP 10 include faults, alarms, and service states of the nodes, and use the IPC communication path. Since the IPC network 16 is used as a path for reporting the error messages, when the IPC communication is disconnected due to a serious failure of the IPC network 16, the failure is not informed to the OMP 14 and the communication is lost. There was.

Therefore, an object of the present invention is to provide a node failure handling method that can notify the operator of the failure information through the TD bus when the IPC communication path is interrupted due to the failure on the IPC network in the switching system.

The present invention for achieving the above object is a process of collecting the fault information generated on the IPC network in the CIP and storing in the dual port RAM, and the period within the CIP set in the peripheral processor connected via the CIP and TD bus Scanning the critical alarm status register to verify that the relevant bit is set, and reading the critical alarm status register from the peripheral processor and the handshake register stored in the dual port RAM of the CIP when the relevant bit is set. It is characterized in that the process consists of reading the fault information to the OMP via the P bus.

1 is a system diagram showing a path for delivering a node failure message in a conventional switching system.

2 is a system configuration diagram for delivering a node failure message of an exchange system according to an embodiment of the present invention;

3 is a control flowchart for notifying node failure information through a TD bus according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a system configuration diagram for delivering a node failure message of an exchange system according to an embodiment of the present invention.

In the switching system, a plurality of subsystems 1 to m (P1 to Pn) based on processors are connected to the IPC network 16 through a plurality of nodes ND1 to NDm, and CIP (Communication) to the IPC network 16 is performed. An Inter-working Processor is connected, and an Operation Maintenance Processor (OMP) is connected to the IPC network 16 through the node ND0. A PP (Peripheral Processor) 12 is connected through a TD bus (Telephoney Device Bus) connected to the CIP 10, and the PP 14 is connected to the OMP 14 through a P bus.

The CIP 10 collects the failure states of the nodes generated on the IPC network 16 and reports them to the OMP 14 through the TD bus and the PP 12 so that the exchange operators can know the failure states. The PP 14 performs low-level work requiring real-time processing of signals detected and instantaneously analyzed from telephony devices or I / O devices, and generates alarm messages, faults, and subsystem boards. It performs the function of notifying OMP 14 by collecting installation status and function fail information. The OMP 14 performs functions such as operation and maintenance of the system, billing and statistics.

3 is a control flowchart for notifying node failure information through a TD bus according to an embodiment of the present invention.

2 to 3, the operation of the preferred embodiment of the present invention will be described in detail.

First, in step 101, the CIP 10 checks hmnc_equip and hmnc_ffail to check whether a node failure occurs, and proceeds to step 102. In step 102, the CIP 10 checks whether there is a change in the function fail and the board demounting information of the subsystem. In other words, if hmnc_equip = 1 and hmnc_ffail = 1, and if it is not 1, it is determined that there is no change in function fail and board mounting information, and the operation ends. However, if there is a change in the function fail and the mounting information, proceed to step 103. If the handshake register (dpwhncr → Hand Shake Control Register) as shown in Table 1 is cleared (dpwhmnc & x02), check and proceed to step 104. .

D7-D4 D3-D2 D1 D0 ADRESS LENGTH STATE TYPE

TYPE: Dual Port Ram TEST MODE (0), Dual Port Ram Normal MODE (1)

STATUS: Read not allow (0), Read allow (1)

Length (xx): Address read range

Address (yyy): Address read start point offset (0x0 ∼ 0xF)

In step 104, the CIP 10 records the address of the unmounted information and the function fail address in the dual port RAM as shown in Table 2 below, and records the unmounted information in the address areas 0x400002 to 0x400005 (dphmnc_off) of the dual port RAM. The function fail information is recorded in the address areas 0x400006 to 0x400009 (dpmnc_off) of the dual port RAM.

Here, dphmnc_off is an area for storing unmounting information of nodes in the dual port memory of the CIP 10, and dphmnc_ff is an area for storing function fail information of nodes in the dual port memory of the CIP 10.

D31 D30 D29 D28 D27 D26 D25 D24 - - - - Node 27 Node 26 Node 25 Node 24 D23 D22 D21 D20 D19 D18 D17 D16 Node 23 Node 22 Node 21 Node 20 Node 19 Node 18 Node 17 Node 26 D15 D14 D13 D12 D11 D10 D9 D8 Node 15 Node 14 Node 13 Node 12 Node 11 Node 10 Node 9 Node 8 D7 D6 D5 D4 D3 D2 D1 D0 Node 7 Node6 Node 5 Node 4 Node3 Node2 Node 1 Node 0

In Table 2, the mounting and function fail states of the corresponding nodes are stored bit by bit in the corresponding address area of the dual port RAM.

dphmnc_off: Node Delete Alarm [27..0], dphmnc_ff: Node Function fail [27..0]

Then, the board unmounting information and the function fail are recorded in the dual port RAM handshake register (dpwhncr), that is, dpwhncr = ((int) dphmnc_off & 0x0f << 4) / 3) → unmounting, dpwhncr = (( int) dphmnc_ff & 0x0f << 4) / 3)? In the case of board demounting in the CASR (Critical Alarm Status Register) as shown in Table 3, the CASR bit 0 (ISC) is set to '1', and the function fail bit 2 (BFF) is set to '1'.

D7 D6 D5 D4 D3 D2 D1 D0 - - - - - BFF - ISC

ISC: Node Delete (1) → Board Hernia Status

BFF: Node Function Fail (1)

If the D0 (ISC: Insertion status change) of CASR in TD bus specification is '1' (Status change) or D2 (BFF: Block function fail) is set to '1', Model 1 (Byte operation) Becomes That is, when the failure information is to be stored in the dual port RAM, the CIP 10 writes the information in the corresponding address areas dphmnc_off and dphmnc_off and sets the TD bus handshake register dphmncr as follows and writes it in 0x400000.

dpwhncr (D7 ∼ D0): yyyyxx (yyyy: address, xx: length)

The CIP 10 then waits for a time set in step 105, for example 800 msec. At this time, waiting for 800msec is a time for the PP 12 to read the unmounting information and the function fail information stored in the dual port RAM embedded in the CIP (10) via the TD bus. Therefore, PP (12) scans CASR at 50msec period and reads the handshake register (dpwhncr) if the relevant bit is set and if it is set to D1 (bit 1) '1' (Read Allow Mode), the handshake register (dpwhncr). After reading the information indicated by the address value of (0x400000) + (0x02 to 0x0f) with reference to the addresses D7 to D4 of, dpwhncr (D7 to D0): 00000001 to the handshake register (dpwhncr) of CIP (10). Set to indicate that communication has been completed normally.

Then, in step 106, the CIP 10 checks whether the handshake register is clear. That is, it is checked whether the handshake register dpwhncr (D7 to D0) is set to 00000001. In this case, if the handshake register is not set to 'I', the process proceeds to step 110 and the CIP 10 processes the TD bus access fail and proceeds to step 107. In step 107, the CIP 10 clears CASR0 (bit 0) = 0 and CASR2 (bit 2) = 0 and ends the operation. However, if the handshake register is cleared in step 106, the unmounting information and the function fail information are read from the PP 12, and the process proceeds to step 107. In step 107, the CIP 10 returns CASR0 (bit 0) = 0 and CASR2 (bit 2). ) = 0 Clear the operation.

If the handshake register is not cleared in step 103, the process proceeds to step 108 and the CIP 10 waits for a set time, for example, 800 msec. At this time, waiting for 800msec is a waiting time for the PP 12 to read the unmounting information and the function fail information stored in the dual port RAM embedded in the CIP 10 through the TD bus. Therefore, PP (12) scans CASR at 50msec period and reads the handshake register (dpwhncr) if the relevant bit is set and if it is set to D1 (bit 1) '1' (Read Allow Mode), the handshake register (dpwhncr). After reading the information indicated by the address value of (0x400000) + (0x02 to 0x0f) with reference to the addresses D7 to D4 of, dpwhncr (D7 to D0): 00000001 to the handshake register (dpwhncr) of CIP (10). Set to indicate that communication has been completed normally.

Thereafter, in step 109, the CIP 10 checks whether the handshake register is clear. That is, it is checked whether the handshake register dpwhncr (D7 to D0) is set to 00000001. At this time, if the handshake register is not set to 'I', the process proceeds to step 110 and the CIP 10 processes the TD bus access fail. Then, in step 107, the CIP 10 clears CASR0 (bit 0) = 0 and CASR2 (bit 2) = 0 and ends the operation. However, in step 109, if the handshake register (dpwhncr → Hand Shake Control Register) is cleared (dpwhmnc & x02), the CIP 10 proceeds to step 104 and the PP 12 removes the mounting information through the TD bus as described above. And function fail information can be read.

As described above, the present invention, in order to secure the reliability of the nodes that provide communication paths to a plurality of subsystems on the IPC network, in the event of a failure through the TD bus, which is a bypass path, the operator promptly informs the operator to the failure message on the IPC network As a result, the operator does not grasp the failure state and thus has the advantage of minimizing the loss caused by the failure.

Claims (2)

A plurality of subsystems are connected on an IPC network through a plurality of nodes, a CIP is connected to the IPC network, an OMP is connected through a node ND0 to the IPC network, and ferries through a TD bus connected to the CIP. In a method of handling node failure of an IPC network in a switch in which a parallel processor (PP) is connected and the peripheral processor (PP) is connected to an OMP through a P bus, Collecting fault information generated on the IPC network from the CIP and storing the fault information in the dual port RAM; Scanning the critical alarm status register in the CIP at a period set by the peripheral processor connected through the CIP and the TD bus to determine whether a related bit is set; In the peripheral processor, the critical alarm status register is read and when the relevant bit is set, the handshake register stored in the dual port RAM of the CIP is read and the fault information is notified to the OMP through the P bus. Node failure handling method in the IPC network of the exchange characterized in that. The method of claim 1, The failure information is a node failure handling method in an IPC network of a switch, characterized in that the information on the removal, mounting and function of the subsystem board.