KR20010001963A - Method of forming a storage node in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a charge storage electrode of a semiconductor device is provided to easily form the charge storage electrode and to simplify a manufacturing process, by forming a hole pattern using a photoresist layer pattern. CONSTITUTION: A bit line electrically connected to a drain(22) through a plug is formed on a substrate(100) having a gate electrode(1), a source(21) and the drain for forming a semiconductor device. A photoresist layer pattern is formed in a selected region on the entire surface for forming a charge storage electrode. A low temperature oxidation layer is formed on the entire structure having the photoresist layer pattern. After the photoresist layer pattern is eliminated to form a hole pattern, the hole pattern is filled with a metal material. The low temperature oxidation layer is eliminated to form the charge storage electrode electrically connected to the source through the plug.

Description

Method of forming a charge storage electrode of a semiconductor device {Method of forming a storage node in a semiconductor device}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a hole pattern using a photoresist pattern when forming a charge storage electrode, thereby facilitating the formation of the charge storage electrode and simplifying the process steps. A storage electrode forming method.

Ideal capacitors are small in size and large in capacity, and are increasingly needed as devices become more integrated. In general, research is focused on the introduction of new materials having a large capacitor surface area and a dielectric constant of a capacitor.

Currently, widely used dynamic random access memory (DRAM) has a cell structure consisting of one transistor and one capacitor, and this cell structure has remained unchanged until now. However, as the high integration of the devices proceeds rapidly, the size of the area of device isolation, which is responsible for the isolation between the transistors, capacitors, and cells that make up a cell, is greatly reduced, thereby causing various problems in each semiconductor component. have.

The conventional effort to increase the capacitor area is to secure the area and spacing of the device by first cell designing the capacitor in three dimensions to form a stacked structure or a trench structure. Second, it is an attempt to secure the amount of electricity by increasing the effective area by giving unevenness to the surface of the charge storage, a method of depositing a metastable polysilicon (MPS) on the electrode. MPS is also known as hemispherical shaped grains (HSG), which is deposited as a hemispherical polysilicon surface when silicon is deposited near 580 ° C in a low pressure chemical vapor deposition (LPCVD) system. The temperature of 580 ° C. corresponds to a transition zone where the structure of the deposited silicon changes from amorphous to polycrystalline, which is a function of deposition parameters such as temperature and pressure and the flow rate of SiH ₄ . When the surface of the electrode is made of such irregularities to increase the surface area, it is possible to increase the storage amount by about 2 times compared to the planarized electrode structure.

In addition, in order to obtain a large capacitance (capacitance) in accordance with the miniaturization of the device when forming the capacitor structure, the adoption of a high dielectric constant thin film as a capacitor material is increasing.

However, when forming a charge storage electrode of a device of 0.13 μm or less, the difficulty of the contact hole forming process of the charge storage electrode according to the fine patterning, and the difficulty of the etching process of the metal layer (Pt or W, etc.) as the charge storage electrode material As a result, it is difficult to form a charge storage electrode. Due to the above-mentioned difficulties, many constraints have been drawn to increase the height of the capacitor or change the metal layer in order to secure the capacitor characteristics.

Accordingly, an object of the present invention is to solve the problem of the conventional method for forming the charge storage electrode contact hole by using the contact hole etching process, the charge storage electrode through the MLR (multi layer resist) process using a photosensitive film After forming the photoresist pattern for the semiconductor, the formation of the same hole pattern as the conventional charge storage electrode contact hole by the deposition of the oxide film and the removal of the photoresist pattern, thereby forming an electrode and simplifying subsequent steps To provide.

The method for forming a charge storage electrode of a semiconductor device according to the present invention for achieving the above object is a bit electrically connected to the drain through a plug on a substrate formed with a gate electrode, a source and a drain to form a semiconductor device Forming a line; Forming a photoresist pattern on a selected region of the entire upper surface to form a charge storage electrode; Forming a low temperature oxide film on the entire structure of the photoresist pattern; Removing the photoresist pattern to form a hole pattern, and then embedding a metal material in the hole pattern; And removing the low temperature oxide layer to form a charge storage electrode electrically connected to the source through a plug.

1A to 1G are cross-sectional views sequentially illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.

2 is a cross-sectional view illustrating a method of forming a charge storage electrode of a semiconductor device in accordance with another embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

100 semiconductor substrate 1 gate electrode

2 and 7: hard masks 3 and 8: spacer

4: Polysilicon-Plug 5A, 5B and 5C: Bitline Contact Hole

6A and 6B: Charge Storage Electrode Contact Holes

9: bit line 10: photosensitive film

11 oxide film 12 and 13 photosensitive film pattern

14: oxide film pattern 15: low temperature oxide film

16 and 160: charge storage electrode 21: source

22: drain 23 and 25: interlayer insulating film

24: insulated oxide film

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (g) are cross-sectional views sequentially illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.

Referring to FIG. 1A, a plurality of gate electrodes 1 are formed on a semiconductor substrate 100 on which various elements for forming a semiconductor device are formed. After forming the hard mask layer 2 using the nitride films on the plurality of gate electrodes 1, the nitride film spacers 3 are formed on both sides of the gate electrodes 1, respectively. A plurality of sources and drains 21 and 22 are formed in the exposed semiconductor substrate 100. After the first interlayer insulating film 23 is formed on the entire structure, selected portions of the first interlayer insulating film 23 are etched to expose the drains and the sources 22 and 21, respectively. Three bit line contact holes 5A, 5B and 5C, and first and second charge storage electrode contact holes 6A and 6B are formed. A mask layer (not shown) is formed on a selected region over the first interlayer insulating layer 23 including the first bit line contact hole 5A and the first and second charge storage electrode contact holes 6A and 6B. Afterwards, an insulating oxide film 24 and a second interlayer insulating film 25 are formed on the second and third charge storage electrode contact holes 5B and 5C and the first interlayer insulating film 23. After removing the mask layer, polysilicon is embedded in the first bit line contact hole 5A and the first and second charge storage electrode contact holes 6A and 6B to form a polysilicon plug 4. After forming the bit line 9 above the first bit line contact hole 5A, a hard mask layer 7 using a nitride film is formed on the bit line 9, and both sides of the bit line 9 are formed. An insulating film spacer 8 is formed in the portion to complete a bit line electrically connected to the drain 22 through the polysilicon plug 4.

Referring to FIG. 1 (b), after the first photoresist film 10 and the oxide film 11 having appropriate thicknesses are sequentially formed through a multi-layer resist (MLR) process on the entire upper surface including the bit line. The second photosensitive film pattern 12 is formed in the selected region on the oxide film 11.

Referring to FIGS. 1C and 1D, after the oxide film 11 is etched through an etching process using the second photoresist pattern 12 as a mask, an oxide film pattern 11 is formed. The first photoresist layer 10 is etched through an etching process using the oxide layer pattern 11 as a mask to form a first photoresist layer pattern 13 in the form of a charge storage electrode, and the second photoresist layer pattern 12 is formed. Removed through wet etching process.

Referring to FIG. 1 (e), after forming the low temperature oxide film 15 on the entire upper surface including the first photoresist pattern 13, a chemical mechanical polishing (CMP) process is performed with an appropriate target. The low temperature oxide film 15 is polished so that the upper portion of the first photoresist pattern 13 is exposed.

The chemical mechanical polishing process may be replaced by an etchback process.

Referring to FIGS. 1F and 1G, the first photoresist layer pattern 13 is removed to form a hole pattern (not shown), and then the entire upper surface including the hole pattern is formed on the substrate. The metal layer 16 for the charge storage electrode is formed. After performing a chemical mechanical polishing process on the entire upper surface, the low temperature oxide film 15 is removed to form a charge storage electrode 16.

The charge storage electrode metal layer 16 uses platinum (Pt) or tungsten (W), and the chemical mechanical polishing process may be replaced by an etch-back process.

FIG. 2 is a cross-sectional view illustrating a method of forming a charge storage electrode of a semiconductor device according to another exemplary embodiment of the present invention. Instead of the stack type charge storage electrode 16 illustrated in FIG. It shows that the electrode 160 is formed. This is to deposit the material for the charge storage electrode (Pt or W, etc.) in the hole pattern formed in the step of FIG. 1 (e) and to adjust the thickness so that it remains only on the sidewall of the hole pattern, chemical mechanical polishing (CMP) process Alternatively, after performing an etch-back process, the oxide film is removed to form the cylinder-shaped charge storage electrode 160.

As described above, according to the present invention, the charge storage electrode can be easily formed, the subsequent process can be simplified, and the process margin can be broadly formed to obtain reproducible results. In addition, by effectively integrating new materials (Pt, W, etc.), which are currently being proposed as charge storage electrode materials of 4G or more, it is easy to early development of high density devices of 4G or more.

Claims (7)

Forming a bit line electrically connected to the drain through a plug on a substrate on which various elements of a gate electrode, a source and a drain for forming a semiconductor device are formed; Forming a photoresist pattern on a selected region of the entire upper surface to form a charge storage electrode; Forming a low temperature oxide film on the entire structure of the photoresist pattern; Removing the photoresist pattern to form a hole pattern, and then embedding a metal material in the hole pattern; And forming a charge storage electrode electrically connected to the source through a plug by removing the low temperature oxide film. The method of claim 1, The charge storage electrode forming method of the semiconductor device, characterized in that formed in the form of a stack or cylinder. The method of claim 1, And the photosensitive film uses an oxide film for patterning. The method of claim 3, wherein The oxide film is a method of forming a charge storage electrode of a semiconductor device, characterized in that to use a photosensitive film pattern for patterning. The method of claim 1, The metal material is a method of forming a charge storage electrode of a semiconductor device, characterized in that using one of platinum and tungsten. The method of claim 1, And depositing the low temperature oxide film, followed by a chemical mechanical polishing process or an etch-back process. The method of claim 1, After the metal material is deposited on the hole pattern, a chemical mechanical polishing process or an etch-back process is performed.