KR20010001485A - System duplication apparatus and method by memorypartition&control - Google Patents

Abstract

PURPOSE: A device and a method are provided to double a system using a memory by separating a part of the memory in a processor board and controlling the separated memory without an additional device or an exclusive software. CONSTITUTION: A normal operated state of a processor board is individually tested. A doubled state of the corresponding processor is set as an active or a stand-by through a serial channel path according to the individual test. A data path is generated to connect two shared memories to access the shared memories between the active processor and the stand-by processor. A data path is blocked to block the connection of two shared memories not to access from the stand-by processor.

Description

System Redundancy Implementation Apparatus and Method Using Memory {SYSTEM DUPLICATION APPARATUS AND METHOD BY MEMORYPARTITION & CONTROL}

The present invention relates to system redundancy, and in particular, system redundancy using memory that implements processor redundancy using memory to improve redundancy and reliability of a communication system using an Ultra SPARC CPU board, which is a high performance RISK CPU. An apparatus and method are provided.

In general, a duplex configuration method of a processor board for a communication system using a RISC type CPU mainly uses a hard disk as shown in FIG. 1 and a method using a local area network as shown in FIG. It was. In the duplexing system of the conventional system, the redundant processors perform independent processing with each other, and additional devices capable of exchanging data with each other in order to share newly updated data with each other and software using the same (S / W) ) Was required. As the additional device shown in FIG. 2 and FIG. 3, a disk, a disk switching board and a LAN matching device capable of communicating with an active processor and a standby processor are applicable. It includes redundancy monitoring and data synchronization functions.

However, the conventional system redundancy has a problem in that the structure of the system is complicated due to functions such as additional devices and dedicated software added to configure the redundancy, and the system configuration is also enormous.

Accordingly, an object of the present invention is to solve the above problems by separating the memory part of the processor board consisting of redundancy without the use of an additional device and dedicated software when configuring the processor redundancy of the communication system, and controlling the separated memory. The present invention provides a method for implementing system redundancy.

In order to achieve the above object, in each of the two redundant processor boards according to the present invention, the redundant memory board is provided with its own memory accessible only by itself and shared memory that can be shared with the other processor board, and a serial channel path between processors is provided. System redundancy using memory in the system; During initialization, separately diagnosing a normal operating state of the processor board; setting a redundancy state of the corresponding processor to be active or standby through the serial channel path according to the individual diagnosis of the processor board; and setting the active processor A process of creating a data path connecting two shared memories to access the shared memory of the shared memory and the standby memory of the processor set to standby, and the two shared memories to prevent access to both shared memories from the standby processor. It is characterized in that the data path blocking process to block the connection of the memory.

1 is a diagram illustrating a system redundancy using a conventional disk (DISK)

2 is a diagram illustrating a system redundancy using a conventional LAN

3 is a diagram illustrating a system redundancy using a memory according to the present invention.

4 is a control flowchart for system redundancy using a memory according to a preferred embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same reference numerals as much as possible even if they are displayed on different drawings. In addition, in the following description, numerous specific details, such as specific process flows, are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

3 is a diagram illustrating a system redundancy using a memory according to the present invention. 3 is explained;

The redundancy of the processor board according to the present invention is performed in the active processor board 100 and the standby processor board 200, and the active processor board 100 and the standby processor board 200 are redundant. The processor uses an Ultra SPARC CPU, which is a RISK CPU.

The active processor board 100 includes a processor A 110, a memory A 120, a shared memory A 140, a transceiver A 130, and a controller A 150 in its own board. The standby processor board 200 also includes a processor B 210, a memory B 220, a shared memory B 240, a transceiver B 230, and a controller B 250 in its own board.

Each processor board separates and operates two memories, where one memory (refering to shared memory) is configured to pass through the transceiver, and structurally accessible to each processor of the active and standby processor boards. That is, the processor A 110 of the active processor board 100 may access its own memory A 120 and the shared memory A 140, as well as the shared memory B 240 of the standby processor board 200. Can be accessed through the transceivers 130 and 230 of each board.

The transceiver applied to the present invention is a block configured to control the data progress path of the shared memory, and the data can be bidirectionally progressed and the path can be opened / closed freely. In addition, the path at the rear end of the transceiver is directly connected to the shared memory on its own side and the shared memory on the other side.

Path 301 is a serial channel path for two processor boards to set active and standby, and path 302 is set to allow processor A 110 set to be active to access shared memory 140 and 240. The path 303 is a path configured to set the processor B 210 set to standby to be inaccessible to the shared memory. The controller A 150 may control the transceiver A 130 to enable / disable through the path 302, and the controller B 250 may control the transceiver B 230 to enable / disable through the path 303. can do.

On the other hand, the 304 path represents the memory usage path of the processor that is active and the path 305 represents the memory usage path of the processor that is operating in standby.

In FIG. 3, each of the processor boards is configured by dividing the memory into two, in order to configure a memory that can be shared by the two processor boards. This memory separation is possible by separating the memory address areas in software.

Since the shared memory areas of the two processor boards are configured to be accessible by the two processors, the active processor board is authorized to be used during system operation. Configuring the shared memory to pass through the transceiver provides a device capable of controlling the shared memory to control data flow to the shared memory at the rear of the transceiver, thereby preventing two processors from simultaneously accessing the data path. This is to prevent collisions. In this case, the transceiver is designed using a switching chip with a low data delay.

4 is a control flowchart for system redundancy using a memory according to a preferred embodiment of the present invention.

3 and 4, a preferred embodiment of the present invention will be described in detail with reference to FIG. 4.

First, when the power is applied in step 401, the two processors A and B proceed to step 403 to perform an individual diagnosis function. The individual diagnostic function refers to a function of diagnosing whether the two processor boards can operate normally.

When the individual diagnosis is completed in each of the two processors, the serial channel 301 is driven in step 405 to set active or standby. At this time, the setting method is performed by the handshake method, and all programs up to this time are performed only in the memory 120 or 220 of each processor.

When the two processor boards are configured to be active and standby by the above process, each processor board controls its controller according to the following conditions. This process starts from step 407.

Condition of the mode settable by the controller of the processor board

1. Diagnostic mode: Each processor can only use its own memory

2. Redundant active mode: magnetic memory and shared memory and partner shared memory can be used

3. Redundant standby mode: only magnetic memory is available

4. Dual independent operation mode: magnetic memory and shared memory available

Accordingly, if the magnetic processor board is set to the active state in step 407, the controller proceeds to step 409 to control the controller in the active mode. If the magnetic processor board is set to the standby state, the controller proceeds to step 421. To control.

Referring to the case in which the magnetic processor board is set to the active state in step 407; In step 409, the active processor first sets the controller to the active mode in order to secure the path 304 of the shared memory. This may be done by setting the register value of the controller to be active.

When the controller is set to the active mode in step 409, the path of the transceiver is enabled by the active setting value of the register described above in step 411. The data path at this time is connected not only to the own side shared memory but also to the counterpart shared memory. In this case, as shown in step 413, the memory area that can be used by the active processor is the magnetic memory, the shared memory on the magnetic side, and the shared memory on the other side.

If the active processor is transferred to standby during operation in step 415, the processor returns to step 405 to transmit the current processor state (program count information, stack point, CPU internal register value, etc.) using the serial channel. , The transfer is performed.

On the other hand, referring to the case where the magnetic processor board is set to the standby state in step 407; In operation 421, the standby processor first sets the controller to the standby mode to block the path of the shared memory. This may be done by setting the register value of the control unit to standby.

When the controller is set to the standby mode in step 421, the path of the transceiver is disabled by the standby setting value of the register described above in step 411. In this case, since all data progress paths provided for redundancy are blocked, the memory area that the standby processor can use is only the magnetic memory as shown in step 425.

When the processor operating in the standby is switched to active during the operation in step 427, the process returns to step 405 to perform the transfer using the serial channel.

On the other hand, the detailed description of the present invention has been described with reference to specific embodiments, of course, various modifications are possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, by implementing a system redundancy implementing apparatus using a separate memory according to the present invention, by implementing the system redundancy, there is an effect of simplifying and simplifying the structure of the system.

Claims (17)

In the system redundancy implement apparatus using a memory, A serial channel path formed between the redundant processor boards as a path that transfers the processor statuses for setting active and standby when switching operation states of two processor boards operated by redundancy; A processor for determining whether the processor board to which the processor board belongs is an active state or a standby state, and controlling the controller to a specific mode according to the redundancy state setting; A first memory allowing only the access of the redundant processor on its own side and a second memory configured to pass through the transceiver so that all the redundant processors can be shared structurally. With the memory to operate separately A transceiver configured to enable bi-directional progression of data, free to open / close a data path, and to control a data progress path of the second memory; Control the transceiver to enable the redundant processor set to the active access to the second memory, and control the transceiver to disable the redundant processor set to the standby access to the second memory. System redundancy implementation apparatus using a memory, characterized in that for configuring an active / standby dual processor board having a control unit. The method of claim 1, And the processor controls the controller to enable the magnetic first memory, the magnetic second memory, and the counterpart second memory when the duplex state is set to the active mode. The method of claim 2, And the processor controls the controller to use only its own memory when the duplex state is set to the standby mode. The method of claim 3, wherein And the processor controls the controller to use only its own first memory during the individual diagnosis. The method of claim 1, The processor may be configured to control the controller to operate in a redundant independent operation mode so that only a magnetic first memory and a magnetic second memory may be used. The method of claim 1, And the transceiver uses a switching chip with low data delay. The method of claim 6, And if the controller controls the transceiver with enable, the data path is connected to allow the processor to simultaneously access the first memory, the second memory, and the second memory of the counterpart. The method of claim 7, wherein And if the controller controls the transceiver to disable, blocking the data paths provided for the redundancy. The method of claim 8, And the transceiver controls a data path to a second memory to prevent all of the duplication processors from accessing the second memory at the same time to prevent a data path collision. The method of claim 9, And the memory divides the memory address area into software and separates the memory address into two memories. In each of the two redundant processor boards, each system is divided into its own memory that can be accessed by itself and the shared memory that can be shared with the other processor boards. Individual processor board diagnostic procedures for determining the normal operation state of the processor board upon initialization; Setting a redundancy state of a corresponding processor to an active or standby state through a serial channel path of each of the redundant processors according to an individual diagnosis of the processor board; A data path generation process of connecting two shared memories to allow the active processor to access its shared memory and the shared memory of the processor set to standby; And a data path blocking process for disconnecting the two shared memories so that the two shared memories cannot be accessed by the processor set as the standby. The method of claim 11, And the active processor accesses its own memory, its own shared memory, and shared memory of a standby processor board. The method of claim 12, And the standby processor can access and use only its own memory. It forms the serial channel path between the redundant processors as the processor status transfer path for setting the operation status between the redundant processor boards.The two redundant processors distinguish and share the shared memory that can be shared by only the own side processor. In a system redundancy implementation method using a memory in a redundant processor board comprising a transceiver for controlling a data progress path to the shared memory according to the redundant operation state of the processor, and a control unit for controlling the operation of the transceiver, Determining whether the redundant state of the processor board is active or standby in each of the processors of the two redundant processor boards; A duplication state setting process of setting a duplication state to an active or standby state in response to the duplication state determination in each processor when the duplication state determination is completed; Connecting the data path by enabling the transceiver through the control unit to access the magnetic side memory, the magnetic side shared memory, and the counterpart shared memory in the processor having the redundancy set to active; Blocking all data paths provided for redundancy by controlling the transceiver to be disabled through the control unit so that the corresponding processor having the redundancy state set to standby cannot access the shared memory on its own side and its counterpart; And a process of transferring the current processor state to a counterpart processor through the serial channel to perform a switchover when an operation state change occurs in the processor operating due to the duplication. The method of claim 14, And the transceiver controls a data path to the shared memory to prevent the two processors from accessing the shared memory at the same time. The method of claim 15, The duplexing state determination and duplication state setting of the processor is performed by the magnetic memory provided in each of the processor system redundancy implementation method using a memory. The method of claim 16, And a corresponding processor configured as the standby can access only its own memory.